1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2//
3// Copyright(c) 2022 Mediatek Inc. All rights reserved.
4//
5// Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
6//         Tinghan Shen <tinghan.shen@mediatek.com>
7
8/*
9 * Hardware interface for audio DSP on mt8186
10 */
11
12#include <linux/delay.h>
13#include <linux/firmware.h>
14#include <linux/io.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17#include <linux/of_platform.h>
18#include <linux/of_reserved_mem.h>
19#include <linux/module.h>
20
21#include <sound/sof.h>
22#include <sound/sof/xtensa.h>
23#include "../../ops.h"
24#include "../../sof-of-dev.h"
25#include "../../sof-audio.h"
26#include "../adsp_helper.h"
27#include "../mtk-adsp-common.h"
28#include "mt8186.h"
29#include "mt8186-clk.h"
30
31static int mt8186_get_mailbox_offset(struct snd_sof_dev *sdev)
32{
33	return MBOX_OFFSET;
34}
35
36static int mt8186_get_window_offset(struct snd_sof_dev *sdev, u32 id)
37{
38	return MBOX_OFFSET;
39}
40
41static int mt8186_send_msg(struct snd_sof_dev *sdev,
42			   struct snd_sof_ipc_msg *msg)
43{
44	struct adsp_priv *priv = sdev->pdata->hw_pdata;
45
46	sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
47			  msg->msg_size);
48
49	return mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_REQ, MTK_ADSP_IPC_OP_REQ);
50}
51
52static void mt8186_dsp_handle_reply(struct mtk_adsp_ipc *ipc)
53{
54	struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc);
55	unsigned long flags;
56
57	spin_lock_irqsave(&priv->sdev->ipc_lock, flags);
58	snd_sof_ipc_process_reply(priv->sdev, 0);
59	spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags);
60}
61
62static void mt8186_dsp_handle_request(struct mtk_adsp_ipc *ipc)
63{
64	struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc);
65	u32 p; /* panic code */
66	int ret;
67
68	/* Read the message from the debug box. */
69	sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4,
70			 &p, sizeof(p));
71
72	/* Check to see if the message is a panic code 0x0dead*** */
73	if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
74		snd_sof_dsp_panic(priv->sdev, p, true);
75	} else {
76		snd_sof_ipc_msgs_rx(priv->sdev);
77
78		/* tell DSP cmd is done */
79		ret = mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_RSP, MTK_ADSP_IPC_OP_RSP);
80		if (ret)
81			dev_err(priv->dev, "request send ipc failed");
82	}
83}
84
85static struct mtk_adsp_ipc_ops dsp_ops = {
86	.handle_reply		= mt8186_dsp_handle_reply,
87	.handle_request		= mt8186_dsp_handle_request,
88};
89
90static int platform_parse_resource(struct platform_device *pdev, void *data)
91{
92	struct resource *mmio;
93	struct resource res;
94	struct device_node *mem_region;
95	struct device *dev = &pdev->dev;
96	struct mtk_adsp_chip_info *adsp = data;
97	int ret;
98
99	ret = of_reserved_mem_device_init(dev);
100	if (ret) {
101		dev_err(dev, "of_reserved_mem_device_init failed\n");
102		return ret;
103	}
104
105	mem_region = of_parse_phandle(dev->of_node, "memory-region", 1);
106	if (!mem_region) {
107		dev_err(dev, "no memory-region sysmem phandle\n");
108		return -ENODEV;
109	}
110
111	ret = of_address_to_resource(mem_region, 0, &res);
112	of_node_put(mem_region);
113	if (ret) {
114		dev_err(dev, "of_address_to_resource sysmem failed\n");
115		return ret;
116	}
117
118	adsp->pa_dram = (phys_addr_t)res.start;
119	if (adsp->pa_dram & DRAM_REMAP_MASK) {
120		dev_err(dev, "adsp memory(%#x) is not 4K-aligned\n",
121			(u32)adsp->pa_dram);
122		return -EINVAL;
123	}
124
125	adsp->dramsize = resource_size(&res);
126	if (adsp->dramsize < TOTAL_SIZE_SHARED_DRAM_FROM_TAIL) {
127		dev_err(dev, "adsp memory(%#x) is not enough for share\n",
128			adsp->dramsize);
129		return -EINVAL;
130	}
131
132	dev_dbg(dev, "dram pbase=%pa size=%#x\n", &adsp->pa_dram, adsp->dramsize);
133
134	mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
135	if (!mmio) {
136		dev_err(dev, "no ADSP-CFG register resource\n");
137		return -ENXIO;
138	}
139
140	adsp->va_cfgreg = devm_ioremap_resource(dev, mmio);
141	if (IS_ERR(adsp->va_cfgreg))
142		return PTR_ERR(adsp->va_cfgreg);
143
144	adsp->pa_cfgreg = (phys_addr_t)mmio->start;
145	adsp->cfgregsize = resource_size(mmio);
146
147	dev_dbg(dev, "cfgreg pbase=%pa size=%#x\n", &adsp->pa_cfgreg, adsp->cfgregsize);
148
149	mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
150	if (!mmio) {
151		dev_err(dev, "no SRAM resource\n");
152		return -ENXIO;
153	}
154
155	adsp->pa_sram = (phys_addr_t)mmio->start;
156	adsp->sramsize = resource_size(mmio);
157
158	dev_dbg(dev, "sram pbase=%pa size=%#x\n", &adsp->pa_sram, adsp->sramsize);
159
160	mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sec");
161	if (!mmio) {
162		dev_err(dev, "no SEC register resource\n");
163		return -ENXIO;
164	}
165
166	adsp->va_secreg = devm_ioremap_resource(dev, mmio);
167	if (IS_ERR(adsp->va_secreg))
168		return PTR_ERR(adsp->va_secreg);
169
170	adsp->pa_secreg = (phys_addr_t)mmio->start;
171	adsp->secregsize = resource_size(mmio);
172
173	dev_dbg(dev, "secreg pbase=%pa size=%#x\n", &adsp->pa_secreg, adsp->secregsize);
174
175	mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bus");
176	if (!mmio) {
177		dev_err(dev, "no BUS register resource\n");
178		return -ENXIO;
179	}
180
181	adsp->va_busreg = devm_ioremap_resource(dev, mmio);
182	if (IS_ERR(adsp->va_busreg))
183		return PTR_ERR(adsp->va_busreg);
184
185	adsp->pa_busreg = (phys_addr_t)mmio->start;
186	adsp->busregsize = resource_size(mmio);
187
188	dev_dbg(dev, "busreg pbase=%pa size=%#x\n", &adsp->pa_busreg, adsp->busregsize);
189
190	return 0;
191}
192
193static void adsp_sram_power_on(struct snd_sof_dev *sdev)
194{
195	snd_sof_dsp_update_bits(sdev, DSP_BUSREG_BAR, ADSP_SRAM_POOL_CON,
196				DSP_SRAM_POOL_PD_MASK, 0);
197}
198
199static void adsp_sram_power_off(struct snd_sof_dev *sdev)
200{
201	snd_sof_dsp_update_bits(sdev, DSP_BUSREG_BAR, ADSP_SRAM_POOL_CON,
202				DSP_SRAM_POOL_PD_MASK, DSP_SRAM_POOL_PD_MASK);
203}
204
205/*  Init the basic DSP DRAM address */
206static int adsp_memory_remap_init(struct snd_sof_dev *sdev, struct mtk_adsp_chip_info *adsp)
207{
208	u32 offset;
209
210	offset = adsp->pa_dram - DRAM_PHYS_BASE_FROM_DSP_VIEW;
211	adsp->dram_offset = offset;
212	offset >>= DRAM_REMAP_SHIFT;
213
214	dev_dbg(sdev->dev, "adsp->pa_dram %pa, offset %#x\n", &adsp->pa_dram, offset);
215
216	snd_sof_dsp_write(sdev, DSP_BUSREG_BAR, DSP_C0_EMI_MAP_ADDR, offset);
217	snd_sof_dsp_write(sdev, DSP_BUSREG_BAR, DSP_C0_DMAEMI_MAP_ADDR, offset);
218
219	if (offset != snd_sof_dsp_read(sdev, DSP_BUSREG_BAR, DSP_C0_EMI_MAP_ADDR) ||
220	    offset != snd_sof_dsp_read(sdev, DSP_BUSREG_BAR, DSP_C0_DMAEMI_MAP_ADDR)) {
221		dev_err(sdev->dev, "emi remap fail\n");
222		return -EIO;
223	}
224
225	return 0;
226}
227
228static int mt8186_run(struct snd_sof_dev *sdev)
229{
230	u32 adsp_bootup_addr;
231
232	adsp_bootup_addr = SRAM_PHYS_BASE_FROM_DSP_VIEW;
233	dev_dbg(sdev->dev, "HIFIxDSP boot from base : 0x%08X\n", adsp_bootup_addr);
234	mt8186_sof_hifixdsp_boot_sequence(sdev, adsp_bootup_addr);
235
236	return 0;
237}
238
239static int mt8186_dsp_probe(struct snd_sof_dev *sdev)
240{
241	struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev);
242	struct adsp_priv *priv;
243	int ret;
244
245	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
246	if (!priv)
247		return -ENOMEM;
248
249	sdev->pdata->hw_pdata = priv;
250	priv->dev = sdev->dev;
251	priv->sdev = sdev;
252
253	priv->adsp = devm_kzalloc(&pdev->dev, sizeof(struct mtk_adsp_chip_info), GFP_KERNEL);
254	if (!priv->adsp)
255		return -ENOMEM;
256
257	ret = platform_parse_resource(pdev, priv->adsp);
258	if (ret)
259		return ret;
260
261	sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev,
262						       priv->adsp->pa_sram,
263						       priv->adsp->sramsize);
264	if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {
265		dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",
266			&priv->adsp->pa_sram, priv->adsp->sramsize);
267		return -ENOMEM;
268	}
269
270	priv->adsp->va_sram = sdev->bar[SOF_FW_BLK_TYPE_IRAM];
271
272	sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap(sdev->dev,
273						       priv->adsp->pa_dram,
274						       priv->adsp->dramsize);
275
276	if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {
277		dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",
278			&priv->adsp->pa_dram, priv->adsp->dramsize);
279		return -ENOMEM;
280	}
281
282	priv->adsp->va_dram = sdev->bar[SOF_FW_BLK_TYPE_SRAM];
283
284	sdev->bar[DSP_REG_BAR] = priv->adsp->va_cfgreg;
285	sdev->bar[DSP_SECREG_BAR] = priv->adsp->va_secreg;
286	sdev->bar[DSP_BUSREG_BAR] = priv->adsp->va_busreg;
287
288	sdev->mmio_bar = SOF_FW_BLK_TYPE_SRAM;
289	sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
290
291	/* set default mailbox offset for FW ready message */
292	sdev->dsp_box.offset = mt8186_get_mailbox_offset(sdev);
293
294	ret = adsp_memory_remap_init(sdev, priv->adsp);
295	if (ret) {
296		dev_err(sdev->dev, "adsp_memory_remap_init fail!\n");
297		return ret;
298	}
299
300	/* enable adsp clock before touching registers */
301	ret = mt8186_adsp_init_clock(sdev);
302	if (ret) {
303		dev_err(sdev->dev, "mt8186_adsp_init_clock failed\n");
304		return ret;
305	}
306
307	ret = mt8186_adsp_clock_on(sdev);
308	if (ret) {
309		dev_err(sdev->dev, "mt8186_adsp_clock_on fail!\n");
310		return ret;
311	}
312
313	adsp_sram_power_on(sdev);
314
315	priv->ipc_dev = platform_device_register_data(&pdev->dev, "mtk-adsp-ipc",
316						      PLATFORM_DEVID_NONE,
317						      pdev, sizeof(*pdev));
318	if (IS_ERR(priv->ipc_dev)) {
319		ret = PTR_ERR(priv->ipc_dev);
320		dev_err(sdev->dev, "failed to create mtk-adsp-ipc device\n");
321		goto err_adsp_off;
322	}
323
324	priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev);
325	if (!priv->dsp_ipc) {
326		ret = -EPROBE_DEFER;
327		dev_err(sdev->dev, "failed to get drvdata\n");
328		goto exit_pdev_unregister;
329	}
330
331	mtk_adsp_ipc_set_data(priv->dsp_ipc, priv);
332	priv->dsp_ipc->ops = &dsp_ops;
333
334	return 0;
335
336exit_pdev_unregister:
337	platform_device_unregister(priv->ipc_dev);
338err_adsp_off:
339	adsp_sram_power_off(sdev);
340	mt8186_adsp_clock_off(sdev);
341
342	return ret;
343}
344
345static void mt8186_dsp_remove(struct snd_sof_dev *sdev)
346{
347	struct adsp_priv *priv = sdev->pdata->hw_pdata;
348
349	platform_device_unregister(priv->ipc_dev);
350	mt8186_sof_hifixdsp_shutdown(sdev);
351	adsp_sram_power_off(sdev);
352	mt8186_adsp_clock_off(sdev);
353}
354
355static int mt8186_dsp_shutdown(struct snd_sof_dev *sdev)
356{
357	return snd_sof_suspend(sdev->dev);
358}
359
360static int mt8186_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
361{
362	mt8186_sof_hifixdsp_shutdown(sdev);
363	adsp_sram_power_off(sdev);
364	mt8186_adsp_clock_off(sdev);
365
366	return 0;
367}
368
369static int mt8186_dsp_resume(struct snd_sof_dev *sdev)
370{
371	int ret;
372
373	ret = mt8186_adsp_clock_on(sdev);
374	if (ret) {
375		dev_err(sdev->dev, "mt8186_adsp_clock_on fail!\n");
376		return ret;
377	}
378
379	adsp_sram_power_on(sdev);
380
381	return ret;
382}
383
384/* on mt8186 there is 1 to 1 match between type and BAR idx */
385static int mt8186_get_bar_index(struct snd_sof_dev *sdev, u32 type)
386{
387	return type;
388}
389
390static int mt8186_pcm_hw_params(struct snd_sof_dev *sdev,
391				struct snd_pcm_substream *substream,
392				struct snd_pcm_hw_params *params,
393				struct snd_sof_platform_stream_params *platform_params)
394{
395	platform_params->cont_update_posn = 1;
396
397	return 0;
398}
399
400static snd_pcm_uframes_t mt8186_pcm_pointer(struct snd_sof_dev *sdev,
401					    struct snd_pcm_substream *substream)
402{
403	int ret;
404	snd_pcm_uframes_t pos;
405	struct snd_sof_pcm *spcm;
406	struct sof_ipc_stream_posn posn;
407	struct snd_sof_pcm_stream *stream;
408	struct snd_soc_component *scomp = sdev->component;
409	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
410
411	spcm = snd_sof_find_spcm_dai(scomp, rtd);
412	if (!spcm) {
413		dev_warn_ratelimited(sdev->dev, "warn: can't find PCM with DAI ID %d\n",
414				     rtd->dai_link->id);
415		return 0;
416	}
417
418	stream = &spcm->stream[substream->stream];
419	ret = snd_sof_ipc_msg_data(sdev, stream, &posn, sizeof(posn));
420	if (ret < 0) {
421		dev_warn(sdev->dev, "failed to read stream position: %d\n", ret);
422		return 0;
423	}
424
425	memcpy(&stream->posn, &posn, sizeof(posn));
426	pos = spcm->stream[substream->stream].posn.host_posn;
427	pos = bytes_to_frames(substream->runtime, pos);
428
429	return pos;
430}
431
432static void mt8186_adsp_dump(struct snd_sof_dev *sdev, u32 flags)
433{
434	u32 dbg_pc, dbg_data, dbg_inst, dbg_ls0stat, dbg_status, faultinfo;
435
436	/* dump debug registers */
437	dbg_pc = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGPC);
438	dbg_data = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGDATA);
439	dbg_inst = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGINST);
440	dbg_ls0stat = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGLS0STAT);
441	dbg_status = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGSTATUS);
442	faultinfo = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PFAULTINFO);
443
444	dev_info(sdev->dev, "adsp dump : pc %#x, data %#x, dbg_inst %#x,",
445		 dbg_pc, dbg_data, dbg_inst);
446	dev_info(sdev->dev, "ls0stat %#x, status %#x, faultinfo %#x",
447		 dbg_ls0stat, dbg_status, faultinfo);
448
449	mtk_adsp_dump(sdev, flags);
450}
451
452static struct snd_soc_dai_driver mt8186_dai[] = {
453{
454	.name = "SOF_DL1",
455	.playback = {
456		.channels_min = 1,
457		.channels_max = 2,
458	},
459},
460{
461	.name = "SOF_DL2",
462	.playback = {
463		.channels_min = 1,
464		.channels_max = 2,
465	},
466},
467{
468	.name = "SOF_UL1",
469	.capture = {
470		.channels_min = 1,
471		.channels_max = 2,
472	},
473},
474{
475	.name = "SOF_UL2",
476	.capture = {
477		.channels_min = 1,
478		.channels_max = 2,
479	},
480},
481};
482
483/* mt8186 ops */
484static struct snd_sof_dsp_ops sof_mt8186_ops = {
485	/* probe and remove */
486	.probe		= mt8186_dsp_probe,
487	.remove		= mt8186_dsp_remove,
488	.shutdown	= mt8186_dsp_shutdown,
489
490	/* DSP core boot */
491	.run		= mt8186_run,
492
493	/* Block IO */
494	.block_read	= sof_block_read,
495	.block_write	= sof_block_write,
496
497	/* Mailbox IO */
498	.mailbox_read	= sof_mailbox_read,
499	.mailbox_write	= sof_mailbox_write,
500
501	/* Register IO */
502	.write		= sof_io_write,
503	.read		= sof_io_read,
504	.write64	= sof_io_write64,
505	.read64		= sof_io_read64,
506
507	/* ipc */
508	.send_msg		= mt8186_send_msg,
509	.get_mailbox_offset	= mt8186_get_mailbox_offset,
510	.get_window_offset	= mt8186_get_window_offset,
511	.ipc_msg_data		= sof_ipc_msg_data,
512	.set_stream_data_offset = sof_set_stream_data_offset,
513
514	/* misc */
515	.get_bar_index	= mt8186_get_bar_index,
516
517	/* stream callbacks */
518	.pcm_open	= sof_stream_pcm_open,
519	.pcm_hw_params	= mt8186_pcm_hw_params,
520	.pcm_pointer	= mt8186_pcm_pointer,
521	.pcm_close	= sof_stream_pcm_close,
522
523	/* firmware loading */
524	.load_firmware	= snd_sof_load_firmware_memcpy,
525
526	/* Firmware ops */
527	.dsp_arch_ops = &sof_xtensa_arch_ops,
528
529	/* DAI drivers */
530	.drv		= mt8186_dai,
531	.num_drv	= ARRAY_SIZE(mt8186_dai),
532
533	/* Debug information */
534	.dbg_dump = mt8186_adsp_dump,
535	.debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
536
537	/* PM */
538	.suspend	= mt8186_dsp_suspend,
539	.resume		= mt8186_dsp_resume,
540
541	/* ALSA HW info flags */
542	.hw_info =	SNDRV_PCM_INFO_MMAP |
543			SNDRV_PCM_INFO_MMAP_VALID |
544			SNDRV_PCM_INFO_INTERLEAVED |
545			SNDRV_PCM_INFO_PAUSE |
546			SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
547};
548
549static struct snd_sof_of_mach sof_mt8186_machs[] = {
550	{
551		.compatible = "mediatek,mt8186",
552		.sof_tplg_filename = "sof-mt8186.tplg",
553	},
554	{}
555};
556
557static const struct sof_dev_desc sof_of_mt8186_desc = {
558	.of_machines = sof_mt8186_machs,
559	.ipc_supported_mask	= BIT(SOF_IPC_TYPE_3),
560	.ipc_default		= SOF_IPC_TYPE_3,
561	.default_fw_path = {
562		[SOF_IPC_TYPE_3] = "mediatek/sof",
563	},
564	.default_tplg_path = {
565		[SOF_IPC_TYPE_3] = "mediatek/sof-tplg",
566	},
567	.default_fw_filename = {
568		[SOF_IPC_TYPE_3] = "sof-mt8186.ri",
569	},
570	.nocodec_tplg_filename = "sof-mt8186-nocodec.tplg",
571	.ops = &sof_mt8186_ops,
572};
573
574/*
575 * DL2, DL3, UL4, UL5 are registered as SOF FE, so creating the corresponding
576 * SOF BE to complete the pipeline.
577 */
578static struct snd_soc_dai_driver mt8188_dai[] = {
579{
580	.name = "SOF_DL2",
581	.playback = {
582		.channels_min = 1,
583		.channels_max = 2,
584	},
585},
586{
587	.name = "SOF_DL3",
588	.playback = {
589		.channels_min = 1,
590		.channels_max = 2,
591	},
592},
593{
594	.name = "SOF_UL4",
595	.capture = {
596		.channels_min = 1,
597		.channels_max = 2,
598	},
599},
600{
601	.name = "SOF_UL5",
602	.capture = {
603		.channels_min = 1,
604		.channels_max = 2,
605	},
606},
607};
608
609/* mt8188 ops */
610static struct snd_sof_dsp_ops sof_mt8188_ops;
611
612static int sof_mt8188_ops_init(struct snd_sof_dev *sdev)
613{
614	/* common defaults */
615	memcpy(&sof_mt8188_ops, &sof_mt8186_ops, sizeof(sof_mt8188_ops));
616
617	sof_mt8188_ops.drv = mt8188_dai;
618	sof_mt8188_ops.num_drv = ARRAY_SIZE(mt8188_dai);
619
620	return 0;
621}
622
623static struct snd_sof_of_mach sof_mt8188_machs[] = {
624	{
625		.compatible = "mediatek,mt8188",
626		.sof_tplg_filename = "sof-mt8188.tplg",
627	},
628	{}
629};
630
631static const struct sof_dev_desc sof_of_mt8188_desc = {
632	.of_machines = sof_mt8188_machs,
633	.ipc_supported_mask	= BIT(SOF_IPC_TYPE_3),
634	.ipc_default		= SOF_IPC_TYPE_3,
635	.default_fw_path = {
636		[SOF_IPC_TYPE_3] = "mediatek/sof",
637	},
638	.default_tplg_path = {
639		[SOF_IPC_TYPE_3] = "mediatek/sof-tplg",
640	},
641	.default_fw_filename = {
642		[SOF_IPC_TYPE_3] = "sof-mt8188.ri",
643	},
644	.nocodec_tplg_filename = "sof-mt8188-nocodec.tplg",
645	.ops = &sof_mt8188_ops,
646	.ops_init = sof_mt8188_ops_init,
647};
648
649static const struct of_device_id sof_of_mt8186_ids[] = {
650	{ .compatible = "mediatek,mt8186-dsp", .data = &sof_of_mt8186_desc},
651	{ .compatible = "mediatek,mt8188-dsp", .data = &sof_of_mt8188_desc},
652	{ }
653};
654MODULE_DEVICE_TABLE(of, sof_of_mt8186_ids);
655
656/* DT driver definition */
657static struct platform_driver snd_sof_of_mt8186_driver = {
658	.probe = sof_of_probe,
659	.remove_new = sof_of_remove,
660	.shutdown = sof_of_shutdown,
661	.driver = {
662	.name = "sof-audio-of-mt8186",
663		.pm = &sof_of_pm,
664		.of_match_table = sof_of_mt8186_ids,
665	},
666};
667module_platform_driver(snd_sof_of_mt8186_driver);
668
669MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
670MODULE_IMPORT_NS(SND_SOC_SOF_MTK_COMMON);
671MODULE_LICENSE("Dual BSD/GPL");
672