1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Keyboard class input driver for the NVIDIA Tegra SoC internal matrix 4 * keyboard controller 5 * 6 * Copyright (c) 2009-2011, NVIDIA Corporation. 7 */ 8 9#include <linux/kernel.h> 10#include <linux/module.h> 11#include <linux/input.h> 12#include <linux/platform_device.h> 13#include <linux/delay.h> 14#include <linux/io.h> 15#include <linux/interrupt.h> 16#include <linux/of.h> 17#include <linux/property.h> 18#include <linux/clk.h> 19#include <linux/slab.h> 20#include <linux/input/matrix_keypad.h> 21#include <linux/reset.h> 22#include <linux/err.h> 23 24#define KBC_MAX_KPENT 8 25 26/* Maximum row/column supported by Tegra KBC yet is 16x8 */ 27#define KBC_MAX_GPIO 24 28/* Maximum keys supported by Tegra KBC yet is 16 x 8*/ 29#define KBC_MAX_KEY (16 * 8) 30 31#define KBC_MAX_DEBOUNCE_CNT 0x3ffu 32 33/* KBC row scan time and delay for beginning the row scan. */ 34#define KBC_ROW_SCAN_TIME 16 35#define KBC_ROW_SCAN_DLY 5 36 37/* KBC uses a 32KHz clock so a cycle = 1/32Khz */ 38#define KBC_CYCLE_MS 32 39 40/* KBC Registers */ 41 42/* KBC Control Register */ 43#define KBC_CONTROL_0 0x0 44#define KBC_FIFO_TH_CNT_SHIFT(cnt) (cnt << 14) 45#define KBC_DEBOUNCE_CNT_SHIFT(cnt) (cnt << 4) 46#define KBC_CONTROL_FIFO_CNT_INT_EN (1 << 3) 47#define KBC_CONTROL_KEYPRESS_INT_EN (1 << 1) 48#define KBC_CONTROL_KBC_EN (1 << 0) 49 50/* KBC Interrupt Register */ 51#define KBC_INT_0 0x4 52#define KBC_INT_FIFO_CNT_INT_STATUS (1 << 2) 53#define KBC_INT_KEYPRESS_INT_STATUS (1 << 0) 54 55#define KBC_ROW_CFG0_0 0x8 56#define KBC_COL_CFG0_0 0x18 57#define KBC_TO_CNT_0 0x24 58#define KBC_INIT_DLY_0 0x28 59#define KBC_RPT_DLY_0 0x2c 60#define KBC_KP_ENT0_0 0x30 61#define KBC_KP_ENT1_0 0x34 62#define KBC_ROW0_MASK_0 0x38 63 64#define KBC_ROW_SHIFT 3 65 66enum tegra_pin_type { 67 PIN_CFG_IGNORE, 68 PIN_CFG_COL, 69 PIN_CFG_ROW, 70}; 71 72/* Tegra KBC hw support */ 73struct tegra_kbc_hw_support { 74 int max_rows; 75 int max_columns; 76}; 77 78struct tegra_kbc_pin_cfg { 79 enum tegra_pin_type type; 80 unsigned char num; 81}; 82 83struct tegra_kbc { 84 struct device *dev; 85 unsigned int debounce_cnt; 86 unsigned int repeat_cnt; 87 struct tegra_kbc_pin_cfg pin_cfg[KBC_MAX_GPIO]; 88 const struct matrix_keymap_data *keymap_data; 89 bool wakeup; 90 void __iomem *mmio; 91 struct input_dev *idev; 92 int irq; 93 spinlock_t lock; 94 unsigned int repoll_dly; 95 unsigned long cp_dly_jiffies; 96 unsigned int cp_to_wkup_dly; 97 bool use_fn_map; 98 bool use_ghost_filter; 99 bool keypress_caused_wake; 100 unsigned short keycode[KBC_MAX_KEY * 2]; 101 unsigned short current_keys[KBC_MAX_KPENT]; 102 unsigned int num_pressed_keys; 103 u32 wakeup_key; 104 struct timer_list timer; 105 struct clk *clk; 106 struct reset_control *rst; 107 const struct tegra_kbc_hw_support *hw_support; 108 int max_keys; 109 int num_rows_and_columns; 110}; 111 112static void tegra_kbc_report_released_keys(struct input_dev *input, 113 unsigned short old_keycodes[], 114 unsigned int old_num_keys, 115 unsigned short new_keycodes[], 116 unsigned int new_num_keys) 117{ 118 unsigned int i, j; 119 120 for (i = 0; i < old_num_keys; i++) { 121 for (j = 0; j < new_num_keys; j++) 122 if (old_keycodes[i] == new_keycodes[j]) 123 break; 124 125 if (j == new_num_keys) 126 input_report_key(input, old_keycodes[i], 0); 127 } 128} 129 130static void tegra_kbc_report_pressed_keys(struct input_dev *input, 131 unsigned char scancodes[], 132 unsigned short keycodes[], 133 unsigned int num_pressed_keys) 134{ 135 unsigned int i; 136 137 for (i = 0; i < num_pressed_keys; i++) { 138 input_event(input, EV_MSC, MSC_SCAN, scancodes[i]); 139 input_report_key(input, keycodes[i], 1); 140 } 141} 142 143static void tegra_kbc_report_keys(struct tegra_kbc *kbc) 144{ 145 unsigned char scancodes[KBC_MAX_KPENT]; 146 unsigned short keycodes[KBC_MAX_KPENT]; 147 u32 val = 0; 148 unsigned int i; 149 unsigned int num_down = 0; 150 bool fn_keypress = false; 151 bool key_in_same_row = false; 152 bool key_in_same_col = false; 153 154 for (i = 0; i < KBC_MAX_KPENT; i++) { 155 if ((i % 4) == 0) 156 val = readl(kbc->mmio + KBC_KP_ENT0_0 + i); 157 158 if (val & 0x80) { 159 unsigned int col = val & 0x07; 160 unsigned int row = (val >> 3) & 0x0f; 161 unsigned char scancode = 162 MATRIX_SCAN_CODE(row, col, KBC_ROW_SHIFT); 163 164 scancodes[num_down] = scancode; 165 keycodes[num_down] = kbc->keycode[scancode]; 166 /* If driver uses Fn map, do not report the Fn key. */ 167 if ((keycodes[num_down] == KEY_FN) && kbc->use_fn_map) 168 fn_keypress = true; 169 else 170 num_down++; 171 } 172 173 val >>= 8; 174 } 175 176 /* 177 * Matrix keyboard designs are prone to keyboard ghosting. 178 * Ghosting occurs if there are 3 keys such that - 179 * any 2 of the 3 keys share a row, and any 2 of them share a column. 180 * If so ignore the key presses for this iteration. 181 */ 182 if (kbc->use_ghost_filter && num_down >= 3) { 183 for (i = 0; i < num_down; i++) { 184 unsigned int j; 185 u8 curr_col = scancodes[i] & 0x07; 186 u8 curr_row = scancodes[i] >> KBC_ROW_SHIFT; 187 188 /* 189 * Find 2 keys such that one key is in the same row 190 * and the other is in the same column as the i-th key. 191 */ 192 for (j = i + 1; j < num_down; j++) { 193 u8 col = scancodes[j] & 0x07; 194 u8 row = scancodes[j] >> KBC_ROW_SHIFT; 195 196 if (col == curr_col) 197 key_in_same_col = true; 198 if (row == curr_row) 199 key_in_same_row = true; 200 } 201 } 202 } 203 204 /* 205 * If the platform uses Fn keymaps, translate keys on a Fn keypress. 206 * Function keycodes are max_keys apart from the plain keycodes. 207 */ 208 if (fn_keypress) { 209 for (i = 0; i < num_down; i++) { 210 scancodes[i] += kbc->max_keys; 211 keycodes[i] = kbc->keycode[scancodes[i]]; 212 } 213 } 214 215 /* Ignore the key presses for this iteration? */ 216 if (key_in_same_col && key_in_same_row) 217 return; 218 219 tegra_kbc_report_released_keys(kbc->idev, 220 kbc->current_keys, kbc->num_pressed_keys, 221 keycodes, num_down); 222 tegra_kbc_report_pressed_keys(kbc->idev, scancodes, keycodes, num_down); 223 input_sync(kbc->idev); 224 225 memcpy(kbc->current_keys, keycodes, sizeof(kbc->current_keys)); 226 kbc->num_pressed_keys = num_down; 227} 228 229static void tegra_kbc_set_fifo_interrupt(struct tegra_kbc *kbc, bool enable) 230{ 231 u32 val; 232 233 val = readl(kbc->mmio + KBC_CONTROL_0); 234 if (enable) 235 val |= KBC_CONTROL_FIFO_CNT_INT_EN; 236 else 237 val &= ~KBC_CONTROL_FIFO_CNT_INT_EN; 238 writel(val, kbc->mmio + KBC_CONTROL_0); 239} 240 241static void tegra_kbc_keypress_timer(struct timer_list *t) 242{ 243 struct tegra_kbc *kbc = from_timer(kbc, t, timer); 244 unsigned long flags; 245 u32 val; 246 unsigned int i; 247 248 spin_lock_irqsave(&kbc->lock, flags); 249 250 val = (readl(kbc->mmio + KBC_INT_0) >> 4) & 0xf; 251 if (val) { 252 unsigned long dly; 253 254 tegra_kbc_report_keys(kbc); 255 256 /* 257 * If more than one keys are pressed we need not wait 258 * for the repoll delay. 259 */ 260 dly = (val == 1) ? kbc->repoll_dly : 1; 261 mod_timer(&kbc->timer, jiffies + msecs_to_jiffies(dly)); 262 } else { 263 /* Release any pressed keys and exit the polling loop */ 264 for (i = 0; i < kbc->num_pressed_keys; i++) 265 input_report_key(kbc->idev, kbc->current_keys[i], 0); 266 input_sync(kbc->idev); 267 268 kbc->num_pressed_keys = 0; 269 270 /* All keys are released so enable the keypress interrupt */ 271 tegra_kbc_set_fifo_interrupt(kbc, true); 272 } 273 274 spin_unlock_irqrestore(&kbc->lock, flags); 275} 276 277static irqreturn_t tegra_kbc_isr(int irq, void *args) 278{ 279 struct tegra_kbc *kbc = args; 280 unsigned long flags; 281 u32 val; 282 283 spin_lock_irqsave(&kbc->lock, flags); 284 285 /* 286 * Quickly bail out & reenable interrupts if the fifo threshold 287 * count interrupt wasn't the interrupt source 288 */ 289 val = readl(kbc->mmio + KBC_INT_0); 290 writel(val, kbc->mmio + KBC_INT_0); 291 292 if (val & KBC_INT_FIFO_CNT_INT_STATUS) { 293 /* 294 * Until all keys are released, defer further processing to 295 * the polling loop in tegra_kbc_keypress_timer. 296 */ 297 tegra_kbc_set_fifo_interrupt(kbc, false); 298 mod_timer(&kbc->timer, jiffies + kbc->cp_dly_jiffies); 299 } else if (val & KBC_INT_KEYPRESS_INT_STATUS) { 300 /* We can be here only through system resume path */ 301 kbc->keypress_caused_wake = true; 302 } 303 304 spin_unlock_irqrestore(&kbc->lock, flags); 305 306 return IRQ_HANDLED; 307} 308 309static void tegra_kbc_setup_wakekeys(struct tegra_kbc *kbc, bool filter) 310{ 311 int i; 312 unsigned int rst_val; 313 314 /* Either mask all keys or none. */ 315 rst_val = (filter && !kbc->wakeup) ? ~0 : 0; 316 317 for (i = 0; i < kbc->hw_support->max_rows; i++) 318 writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4); 319} 320 321static void tegra_kbc_config_pins(struct tegra_kbc *kbc) 322{ 323 int i; 324 325 for (i = 0; i < KBC_MAX_GPIO; i++) { 326 u32 r_shft = 5 * (i % 6); 327 u32 c_shft = 4 * (i % 8); 328 u32 r_mask = 0x1f << r_shft; 329 u32 c_mask = 0x0f << c_shft; 330 u32 r_offs = (i / 6) * 4 + KBC_ROW_CFG0_0; 331 u32 c_offs = (i / 8) * 4 + KBC_COL_CFG0_0; 332 u32 row_cfg = readl(kbc->mmio + r_offs); 333 u32 col_cfg = readl(kbc->mmio + c_offs); 334 335 row_cfg &= ~r_mask; 336 col_cfg &= ~c_mask; 337 338 switch (kbc->pin_cfg[i].type) { 339 case PIN_CFG_ROW: 340 row_cfg |= ((kbc->pin_cfg[i].num << 1) | 1) << r_shft; 341 break; 342 343 case PIN_CFG_COL: 344 col_cfg |= ((kbc->pin_cfg[i].num << 1) | 1) << c_shft; 345 break; 346 347 case PIN_CFG_IGNORE: 348 break; 349 } 350 351 writel(row_cfg, kbc->mmio + r_offs); 352 writel(col_cfg, kbc->mmio + c_offs); 353 } 354} 355 356static int tegra_kbc_start(struct tegra_kbc *kbc) 357{ 358 unsigned int debounce_cnt; 359 u32 val = 0; 360 int ret; 361 362 ret = clk_prepare_enable(kbc->clk); 363 if (ret) 364 return ret; 365 366 /* Reset the KBC controller to clear all previous status.*/ 367 reset_control_assert(kbc->rst); 368 udelay(100); 369 reset_control_deassert(kbc->rst); 370 udelay(100); 371 372 tegra_kbc_config_pins(kbc); 373 tegra_kbc_setup_wakekeys(kbc, false); 374 375 writel(kbc->repeat_cnt, kbc->mmio + KBC_RPT_DLY_0); 376 377 /* Keyboard debounce count is maximum of 12 bits. */ 378 debounce_cnt = min(kbc->debounce_cnt, KBC_MAX_DEBOUNCE_CNT); 379 val = KBC_DEBOUNCE_CNT_SHIFT(debounce_cnt); 380 val |= KBC_FIFO_TH_CNT_SHIFT(1); /* set fifo interrupt threshold to 1 */ 381 val |= KBC_CONTROL_FIFO_CNT_INT_EN; /* interrupt on FIFO threshold */ 382 val |= KBC_CONTROL_KBC_EN; /* enable */ 383 writel(val, kbc->mmio + KBC_CONTROL_0); 384 385 /* 386 * Compute the delay(ns) from interrupt mode to continuous polling 387 * mode so the timer routine is scheduled appropriately. 388 */ 389 val = readl(kbc->mmio + KBC_INIT_DLY_0); 390 kbc->cp_dly_jiffies = usecs_to_jiffies((val & 0xfffff) * 32); 391 392 kbc->num_pressed_keys = 0; 393 394 /* 395 * Atomically clear out any remaining entries in the key FIFO 396 * and enable keyboard interrupts. 397 */ 398 while (1) { 399 val = readl(kbc->mmio + KBC_INT_0); 400 val >>= 4; 401 if (!val) 402 break; 403 404 val = readl(kbc->mmio + KBC_KP_ENT0_0); 405 val = readl(kbc->mmio + KBC_KP_ENT1_0); 406 } 407 writel(0x7, kbc->mmio + KBC_INT_0); 408 409 enable_irq(kbc->irq); 410 411 return 0; 412} 413 414static void tegra_kbc_stop(struct tegra_kbc *kbc) 415{ 416 unsigned long flags; 417 u32 val; 418 419 spin_lock_irqsave(&kbc->lock, flags); 420 val = readl(kbc->mmio + KBC_CONTROL_0); 421 val &= ~1; 422 writel(val, kbc->mmio + KBC_CONTROL_0); 423 spin_unlock_irqrestore(&kbc->lock, flags); 424 425 disable_irq(kbc->irq); 426 del_timer_sync(&kbc->timer); 427 428 clk_disable_unprepare(kbc->clk); 429} 430 431static int tegra_kbc_open(struct input_dev *dev) 432{ 433 struct tegra_kbc *kbc = input_get_drvdata(dev); 434 435 return tegra_kbc_start(kbc); 436} 437 438static void tegra_kbc_close(struct input_dev *dev) 439{ 440 struct tegra_kbc *kbc = input_get_drvdata(dev); 441 442 return tegra_kbc_stop(kbc); 443} 444 445static bool tegra_kbc_check_pin_cfg(const struct tegra_kbc *kbc, 446 unsigned int *num_rows) 447{ 448 int i; 449 450 *num_rows = 0; 451 452 for (i = 0; i < KBC_MAX_GPIO; i++) { 453 const struct tegra_kbc_pin_cfg *pin_cfg = &kbc->pin_cfg[i]; 454 455 switch (pin_cfg->type) { 456 case PIN_CFG_ROW: 457 if (pin_cfg->num >= kbc->hw_support->max_rows) { 458 dev_err(kbc->dev, 459 "pin_cfg[%d]: invalid row number %d\n", 460 i, pin_cfg->num); 461 return false; 462 } 463 (*num_rows)++; 464 break; 465 466 case PIN_CFG_COL: 467 if (pin_cfg->num >= kbc->hw_support->max_columns) { 468 dev_err(kbc->dev, 469 "pin_cfg[%d]: invalid column number %d\n", 470 i, pin_cfg->num); 471 return false; 472 } 473 break; 474 475 case PIN_CFG_IGNORE: 476 break; 477 478 default: 479 dev_err(kbc->dev, 480 "pin_cfg[%d]: invalid entry type %d\n", 481 pin_cfg->type, pin_cfg->num); 482 return false; 483 } 484 } 485 486 return true; 487} 488 489static int tegra_kbc_parse_dt(struct tegra_kbc *kbc) 490{ 491 struct device_node *np = kbc->dev->of_node; 492 u32 prop; 493 int i; 494 u32 num_rows = 0; 495 u32 num_cols = 0; 496 u32 cols_cfg[KBC_MAX_GPIO]; 497 u32 rows_cfg[KBC_MAX_GPIO]; 498 int proplen; 499 int ret; 500 501 if (!of_property_read_u32(np, "nvidia,debounce-delay-ms", &prop)) 502 kbc->debounce_cnt = prop; 503 504 if (!of_property_read_u32(np, "nvidia,repeat-delay-ms", &prop)) 505 kbc->repeat_cnt = prop; 506 507 kbc->use_ghost_filter = of_property_present(np, "nvidia,needs-ghost-filter"); 508 509 if (of_property_read_bool(np, "wakeup-source") || 510 of_property_read_bool(np, "nvidia,wakeup-source")) /* legacy */ 511 kbc->wakeup = true; 512 513 if (!of_get_property(np, "nvidia,kbc-row-pins", &proplen)) { 514 dev_err(kbc->dev, "property nvidia,kbc-row-pins not found\n"); 515 return -ENOENT; 516 } 517 num_rows = proplen / sizeof(u32); 518 519 if (!of_get_property(np, "nvidia,kbc-col-pins", &proplen)) { 520 dev_err(kbc->dev, "property nvidia,kbc-col-pins not found\n"); 521 return -ENOENT; 522 } 523 num_cols = proplen / sizeof(u32); 524 525 if (num_rows > kbc->hw_support->max_rows) { 526 dev_err(kbc->dev, 527 "Number of rows is more than supported by hardware\n"); 528 return -EINVAL; 529 } 530 531 if (num_cols > kbc->hw_support->max_columns) { 532 dev_err(kbc->dev, 533 "Number of cols is more than supported by hardware\n"); 534 return -EINVAL; 535 } 536 537 if (!of_get_property(np, "linux,keymap", &proplen)) { 538 dev_err(kbc->dev, "property linux,keymap not found\n"); 539 return -ENOENT; 540 } 541 542 if (!num_rows || !num_cols || ((num_rows + num_cols) > KBC_MAX_GPIO)) { 543 dev_err(kbc->dev, 544 "keypad rows/columns not properly specified\n"); 545 return -EINVAL; 546 } 547 548 /* Set all pins as non-configured */ 549 for (i = 0; i < kbc->num_rows_and_columns; i++) 550 kbc->pin_cfg[i].type = PIN_CFG_IGNORE; 551 552 ret = of_property_read_u32_array(np, "nvidia,kbc-row-pins", 553 rows_cfg, num_rows); 554 if (ret < 0) { 555 dev_err(kbc->dev, "Rows configurations are not proper\n"); 556 return -EINVAL; 557 } 558 559 ret = of_property_read_u32_array(np, "nvidia,kbc-col-pins", 560 cols_cfg, num_cols); 561 if (ret < 0) { 562 dev_err(kbc->dev, "Cols configurations are not proper\n"); 563 return -EINVAL; 564 } 565 566 for (i = 0; i < num_rows; i++) { 567 kbc->pin_cfg[rows_cfg[i]].type = PIN_CFG_ROW; 568 kbc->pin_cfg[rows_cfg[i]].num = i; 569 } 570 571 for (i = 0; i < num_cols; i++) { 572 kbc->pin_cfg[cols_cfg[i]].type = PIN_CFG_COL; 573 kbc->pin_cfg[cols_cfg[i]].num = i; 574 } 575 576 return 0; 577} 578 579static const struct tegra_kbc_hw_support tegra20_kbc_hw_support = { 580 .max_rows = 16, 581 .max_columns = 8, 582}; 583 584static const struct tegra_kbc_hw_support tegra11_kbc_hw_support = { 585 .max_rows = 11, 586 .max_columns = 8, 587}; 588 589static const struct of_device_id tegra_kbc_of_match[] = { 590 { .compatible = "nvidia,tegra114-kbc", .data = &tegra11_kbc_hw_support}, 591 { .compatible = "nvidia,tegra30-kbc", .data = &tegra20_kbc_hw_support}, 592 { .compatible = "nvidia,tegra20-kbc", .data = &tegra20_kbc_hw_support}, 593 { }, 594}; 595MODULE_DEVICE_TABLE(of, tegra_kbc_of_match); 596 597static int tegra_kbc_probe(struct platform_device *pdev) 598{ 599 struct tegra_kbc *kbc; 600 int err; 601 int num_rows = 0; 602 unsigned int debounce_cnt; 603 unsigned int scan_time_rows; 604 unsigned int keymap_rows; 605 606 kbc = devm_kzalloc(&pdev->dev, sizeof(*kbc), GFP_KERNEL); 607 if (!kbc) { 608 dev_err(&pdev->dev, "failed to alloc memory for kbc\n"); 609 return -ENOMEM; 610 } 611 612 kbc->dev = &pdev->dev; 613 kbc->hw_support = device_get_match_data(&pdev->dev); 614 kbc->max_keys = kbc->hw_support->max_rows * 615 kbc->hw_support->max_columns; 616 kbc->num_rows_and_columns = kbc->hw_support->max_rows + 617 kbc->hw_support->max_columns; 618 keymap_rows = kbc->max_keys; 619 spin_lock_init(&kbc->lock); 620 621 err = tegra_kbc_parse_dt(kbc); 622 if (err) 623 return err; 624 625 if (!tegra_kbc_check_pin_cfg(kbc, &num_rows)) 626 return -EINVAL; 627 628 kbc->irq = platform_get_irq(pdev, 0); 629 if (kbc->irq < 0) 630 return -ENXIO; 631 632 kbc->idev = devm_input_allocate_device(&pdev->dev); 633 if (!kbc->idev) { 634 dev_err(&pdev->dev, "failed to allocate input device\n"); 635 return -ENOMEM; 636 } 637 638 timer_setup(&kbc->timer, tegra_kbc_keypress_timer, 0); 639 640 kbc->mmio = devm_platform_ioremap_resource(pdev, 0); 641 if (IS_ERR(kbc->mmio)) 642 return PTR_ERR(kbc->mmio); 643 644 kbc->clk = devm_clk_get(&pdev->dev, NULL); 645 if (IS_ERR(kbc->clk)) { 646 dev_err(&pdev->dev, "failed to get keyboard clock\n"); 647 return PTR_ERR(kbc->clk); 648 } 649 650 kbc->rst = devm_reset_control_get(&pdev->dev, "kbc"); 651 if (IS_ERR(kbc->rst)) { 652 dev_err(&pdev->dev, "failed to get keyboard reset\n"); 653 return PTR_ERR(kbc->rst); 654 } 655 656 /* 657 * The time delay between two consecutive reads of the FIFO is 658 * the sum of the repeat time and the time taken for scanning 659 * the rows. There is an additional delay before the row scanning 660 * starts. The repoll delay is computed in milliseconds. 661 */ 662 debounce_cnt = min(kbc->debounce_cnt, KBC_MAX_DEBOUNCE_CNT); 663 scan_time_rows = (KBC_ROW_SCAN_TIME + debounce_cnt) * num_rows; 664 kbc->repoll_dly = KBC_ROW_SCAN_DLY + scan_time_rows + kbc->repeat_cnt; 665 kbc->repoll_dly = DIV_ROUND_UP(kbc->repoll_dly, KBC_CYCLE_MS); 666 667 kbc->idev->name = pdev->name; 668 kbc->idev->id.bustype = BUS_HOST; 669 kbc->idev->dev.parent = &pdev->dev; 670 kbc->idev->open = tegra_kbc_open; 671 kbc->idev->close = tegra_kbc_close; 672 673 if (kbc->keymap_data && kbc->use_fn_map) 674 keymap_rows *= 2; 675 676 err = matrix_keypad_build_keymap(kbc->keymap_data, NULL, 677 keymap_rows, 678 kbc->hw_support->max_columns, 679 kbc->keycode, kbc->idev); 680 if (err) { 681 dev_err(&pdev->dev, "failed to setup keymap\n"); 682 return err; 683 } 684 685 __set_bit(EV_REP, kbc->idev->evbit); 686 input_set_capability(kbc->idev, EV_MSC, MSC_SCAN); 687 688 input_set_drvdata(kbc->idev, kbc); 689 690 err = devm_request_irq(&pdev->dev, kbc->irq, tegra_kbc_isr, 691 IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN, 692 pdev->name, kbc); 693 if (err) { 694 dev_err(&pdev->dev, "failed to request keyboard IRQ\n"); 695 return err; 696 } 697 698 err = input_register_device(kbc->idev); 699 if (err) { 700 dev_err(&pdev->dev, "failed to register input device\n"); 701 return err; 702 } 703 704 platform_set_drvdata(pdev, kbc); 705 device_init_wakeup(&pdev->dev, kbc->wakeup); 706 707 return 0; 708} 709 710static void tegra_kbc_set_keypress_interrupt(struct tegra_kbc *kbc, bool enable) 711{ 712 u32 val; 713 714 val = readl(kbc->mmio + KBC_CONTROL_0); 715 if (enable) 716 val |= KBC_CONTROL_KEYPRESS_INT_EN; 717 else 718 val &= ~KBC_CONTROL_KEYPRESS_INT_EN; 719 writel(val, kbc->mmio + KBC_CONTROL_0); 720} 721 722static int tegra_kbc_suspend(struct device *dev) 723{ 724 struct platform_device *pdev = to_platform_device(dev); 725 struct tegra_kbc *kbc = platform_get_drvdata(pdev); 726 727 mutex_lock(&kbc->idev->mutex); 728 if (device_may_wakeup(&pdev->dev)) { 729 disable_irq(kbc->irq); 730 del_timer_sync(&kbc->timer); 731 tegra_kbc_set_fifo_interrupt(kbc, false); 732 733 /* Forcefully clear the interrupt status */ 734 writel(0x7, kbc->mmio + KBC_INT_0); 735 /* 736 * Store the previous resident time of continuous polling mode. 737 * Force the keyboard into interrupt mode. 738 */ 739 kbc->cp_to_wkup_dly = readl(kbc->mmio + KBC_TO_CNT_0); 740 writel(0, kbc->mmio + KBC_TO_CNT_0); 741 742 tegra_kbc_setup_wakekeys(kbc, true); 743 msleep(30); 744 745 kbc->keypress_caused_wake = false; 746 /* Enable keypress interrupt before going into suspend. */ 747 tegra_kbc_set_keypress_interrupt(kbc, true); 748 enable_irq(kbc->irq); 749 enable_irq_wake(kbc->irq); 750 } else { 751 if (input_device_enabled(kbc->idev)) 752 tegra_kbc_stop(kbc); 753 } 754 mutex_unlock(&kbc->idev->mutex); 755 756 return 0; 757} 758 759static int tegra_kbc_resume(struct device *dev) 760{ 761 struct platform_device *pdev = to_platform_device(dev); 762 struct tegra_kbc *kbc = platform_get_drvdata(pdev); 763 int err = 0; 764 765 mutex_lock(&kbc->idev->mutex); 766 if (device_may_wakeup(&pdev->dev)) { 767 disable_irq_wake(kbc->irq); 768 tegra_kbc_setup_wakekeys(kbc, false); 769 /* We will use fifo interrupts for key detection. */ 770 tegra_kbc_set_keypress_interrupt(kbc, false); 771 772 /* Restore the resident time of continuous polling mode. */ 773 writel(kbc->cp_to_wkup_dly, kbc->mmio + KBC_TO_CNT_0); 774 775 tegra_kbc_set_fifo_interrupt(kbc, true); 776 777 if (kbc->keypress_caused_wake && kbc->wakeup_key) { 778 /* 779 * We can't report events directly from the ISR 780 * because timekeeping is stopped when processing 781 * wakeup request and we get a nasty warning when 782 * we try to call do_gettimeofday() in evdev 783 * handler. 784 */ 785 input_report_key(kbc->idev, kbc->wakeup_key, 1); 786 input_sync(kbc->idev); 787 input_report_key(kbc->idev, kbc->wakeup_key, 0); 788 input_sync(kbc->idev); 789 } 790 } else { 791 if (input_device_enabled(kbc->idev)) 792 err = tegra_kbc_start(kbc); 793 } 794 mutex_unlock(&kbc->idev->mutex); 795 796 return err; 797} 798 799static DEFINE_SIMPLE_DEV_PM_OPS(tegra_kbc_pm_ops, 800 tegra_kbc_suspend, tegra_kbc_resume); 801 802static struct platform_driver tegra_kbc_driver = { 803 .probe = tegra_kbc_probe, 804 .driver = { 805 .name = "tegra-kbc", 806 .pm = pm_sleep_ptr(&tegra_kbc_pm_ops), 807 .of_match_table = tegra_kbc_of_match, 808 }, 809}; 810module_platform_driver(tegra_kbc_driver); 811 812MODULE_LICENSE("GPL"); 813MODULE_AUTHOR("Rakesh Iyer <riyer@nvidia.com>"); 814MODULE_DESCRIPTION("Tegra matrix keyboard controller driver"); 815MODULE_ALIAS("platform:tegra-kbc"); 816