Searched refs:clk_rate (Results 101 - 125 of 155) sorted by relevance

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/linux-master/drivers/i2c/busses/
H A Di2c-digicolor.c259 unsigned long clk_rate = clk_get_rate(i2c->clk); local
267 clocktime = DIV_ROUND_UP(clk_rate, 64 * i2c->frequency);
H A Di2c-imx-lpi2c.c210 unsigned int clk_rate, clk_cycle, clkhi, clklo; local
216 clk_rate = lpi2c_imx->rate_per;
224 clk_cycle = clk_rate / ((1 << prescale) * lpi2c_imx->bitrate)
H A Di2c-stm32f4.c761 u32 irq_event, irq_error, clk_rate; local
802 ret = of_property_read_u32(np, "clock-frequency", &clk_rate);
803 if (!ret && clk_rate >= I2C_MAX_FAST_MODE_FREQ)
H A Di2c-microchip-corei2c.c187 u32 clk_rate = clk_get_rate(idev->i2c_clk); local
188 u32 divisor = clk_rate / idev->bus_clk_rate;
/linux-master/drivers/gpio/
H A Dgpio-mvebu.c100 unsigned long clk_rate; member in struct:mvebu_pwm
680 mvpwm->clk_rate);
688 state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, mvpwm->clk_rate);
713 val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle;
728 val = (unsigned long long) mvpwm->clk_rate * state->period;
867 mvpwm->clk_rate = clk_get_rate(mvchip->clk);
868 if (!mvpwm->clk_rate) {
/linux-master/drivers/counter/
H A Dti-ecap-capture.c479 unsigned long clk_rate; local
502 clk_rate = clk_get_rate(ecap_dev->clk);
503 if (!clk_rate) {
/linux-master/drivers/gpu/drm/arm/display/komeda/
H A Dkomeda_crtc.c465 unsigned long clk_rate; local
477 clk_rate = adjusted_mode->crtc_clock * 1000;
480 clk_rate) / 1000;
/linux-master/drivers/mmc/host/
H A Dowl-mmc.c391 unsigned long clk_rate; local
421 clk_rate = clk_round_rate(owl_host->clk, rate << 1);
422 ret = clk_set_rate(owl_host->clk, clk_rate);
H A Drenesas_sdhi_sys_dmac.c51 .clk_rate = 156000000,
55 .clk_rate = 0,
/linux-master/sound/soc/rockchip/
H A Drockchip_pdm.c201 unsigned int clk_rate, clk_div, samplerate; local
211 clk_rate = get_pdm_clk(pdm, samplerate, &clk_src, &clk_out);
212 if (!clk_rate)
/linux-master/drivers/spi/
H A Dspi-sunplus-sp7021.c287 u32 clk_rate, clk_sel, div; local
289 clk_rate = clk_get_rate(pspim->spi_clk);
290 div = max(2U, clk_rate / xfer->speed_hz);
H A Datmel-quadspi.c517 unsigned long clk_rate; local
526 clk_rate = clk_get_rate(aq->pclk);
527 if (!clk_rate)
530 cs_setup = DIV_ROUND_UP((delay * DIV_ROUND_UP(clk_rate, 1000000)),
H A Dspi-uniphier.c648 unsigned long clk_rate; local
695 clk_rate = clk_get_rate(priv->clk);
697 host->max_speed_hz = DIV_ROUND_UP(clk_rate, SSI_MIN_CLK_DIVIDER);
698 host->min_speed_hz = DIV_ROUND_UP(clk_rate, SSI_MAX_CLK_DIVIDER);
H A Dspi-stm32-qspi.c108 u32 clk_rate; member in struct:stm32_qspi
669 presc = DIV_ROUND_UP(qspi->clk_rate, spi->max_speed_hz) - 1;
819 qspi->clk_rate = clk_get_rate(qspi->clk);
820 if (!qspi->clk_rate)
H A Dspi-stm32.c304 * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
333 u32 clk_rate; member in struct:stm32_spi
542 /* Ensure spi->clk_rate is even */
543 div = DIV_ROUND_CLOSEST(spi->clk_rate & ~0x1, speed_hz);
561 spi->cur_speed = spi->clk_rate / (1 << mbrdiv);
2121 spi->clk_rate = clk_get_rate(spi->clk);
2122 if (!spi->clk_rate) {
2173 ctrl->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min;
2174 ctrl->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max;
/linux-master/drivers/regulator/
H A Dti-abb-regulator.c412 u32 clk_rate, sr2_wt_cnt_val, cycle_rate; local
473 clk_rate = DIV_ROUND_CLOSEST(clk_get_rate(abb->clk), 1000000);
476 cycle_rate = DIV_ROUND_CLOSEST(clock_cycles * 10, clk_rate);
/linux-master/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_trace.h161 "crtc=%d bw_ctl=%llu clk_rate=%u stop_req=%d u_bus=%d u_clk=%d",
941 TP_PROTO(struct drm_device *dev, bool stop_req, u64 clk_rate),
942 TP_ARGS(dev, stop_req, clk_rate),
946 __field( u64, clk_rate )
951 __entry->clk_rate = clk_rate;
953 TP_printk("dev:%s stop_req:%s clk_rate:%llu", __get_str(dev_name),
954 __entry->stop_req ? "true" : "false", __entry->clk_rate)
/linux-master/drivers/mtd/nand/raw/
H A Dmeson_nand.c122 unsigned long clk_rate; member in struct:meson_nfc_nand_chip
170 unsigned long clk_rate; member in struct:meson_nfc
273 if (nfc->clk_rate != meson_chip->clk_rate) {
274 ret = clk_set_rate(nfc->nand_clk, meson_chip->clk_rate);
279 nfc->clk_rate = meson_chip->clk_rate;
1271 meson_chip->clk_rate = 1000000000 / meson_chip->level1_divider;
H A Ddenali_dt.c180 denali->clk_rate = clk_get_rate(dt->clk);
H A Dsunxi_nand.c186 * @clk_rate: clk_rate required for this NAND chip
196 unsigned long clk_rate; member in struct:sunxi_nand_chip
233 * @clk_rate: NAND controller current clock rate
248 unsigned long clk_rate; member in struct:sunxi_nfc
436 if (nfc->clk_rate != sunxi_nand->clk_rate) {
437 clk_set_rate(nfc->mod_clk, sunxi_nand->clk_rate);
438 nfc->clk_rate = sunxi_nand->clk_rate;
[all...]
/linux-master/drivers/media/platform/allegro-dvt/
H A Dallegro-mail.h43 s32 clk_rate; member in struct:mcu_msg_init_request
/linux-master/drivers/media/i2c/
H A Dimx296.c1011 unsigned long clk_rate; local
1050 clk_rate = clk_get_rate(sensor->clk);
1052 if (clk_rate == imx296_clk_params[i].freq) {
1059 dev_err(sensor->dev, "unsupported clock rate %lu\n", clk_rate);
/linux-master/sound/soc/fsl/
H A Dfsl_sai.c407 unsigned long clk_rate; local
428 clk_rate = clk_get_rate(sai->mclk_clk[id]);
429 if (!clk_rate)
432 ratio = DIV_ROUND_CLOSEST(clk_rate, freq);
440 diff = abs((long)clk_rate - ratio * freq);
446 if (diff != 0 && clk_rate / diff < 1000)
451 ratio, freq, clk_rate);
/linux-master/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_main.c169 u32 clk_rate = clk_get_rate(priv->sxgbe_clk); local
174 if (clk_rate < SXGBE_CSR_F_150M)
176 else if (clk_rate <= SXGBE_CSR_F_250M)
178 else if (clk_rate <= SXGBE_CSR_F_300M)
180 else if (clk_rate <= SXGBE_CSR_F_350M)
182 else if (clk_rate <= SXGBE_CSR_F_400M)
184 else if (clk_rate <= SXGBE_CSR_F_500M)
/linux-master/drivers/accel/habanalabs/common/
H A Dhabanalabs_ioctl.c285 struct hl_info_clk_rate clk_rate = {0}; local
293 rc = hl_fw_get_clk_rate(hdev, &clk_rate.cur_clk_rate_mhz, &clk_rate.max_clk_rate_mhz);
297 return copy_to_user(out, &clk_rate, min_t(size_t, max_size, sizeof(clk_rate)))

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