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ca8c1fd3 |
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08-Feb-2024 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: split _dpu_encoder_resource_control_helper() Follow the _dpu_encoder_irq_control() change and split the _dpu_encoder_resource_control_helper() into enable and disable parts. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/577525/ Link: https://lore.kernel.org/r/20240208-fd_remove_phys_ops_atomic_mode_set-v4-2-caf5dcd125c0@linaro.org
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#
c6f60037 |
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08-Feb-2024 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: split irq_control into irq_enable and _disable The single helper for both enable and disable cases is too complicated, especially if we start adding more code to these helpers. Split it into irq_enable and irq_disable cases. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/577526/ Link: https://lore.kernel.org/r/20240208-fd_remove_phys_ops_atomic_mode_set-v4-1-caf5dcd125c0@linaro.org
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#
6be6ece9 |
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02-Aug-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: stop using raw IRQ indices in the kernel traces In preparation to reworking IRQ indcies, stop using raw indices in kernel traces. Instead use a pair of register index and bit. This corresponds closer to the values in HW catalog. Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/550935/ Link: https://lore.kernel.org/r/20230802100426.4184892-8-dmitry.baryshkov@linaro.org
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#
fdcb8fe0 |
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02-Aug-2023 |
Jessica Zhang <quic_jesszhan@quicinc.com> |
drm/msm/dpu: Drop encoder vsync_event Drop vsync_event and vsync_event_work handlers as they are unnecessary. In addition drop the dpu_enc_ktime_template event class as it will be unused after the vsync_event handlers are dropped. Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/550983/ Link: https://lore.kernel.org/r/20230802-encoder-cleanup-v2-1-5bfdec0ce765@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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#
e955a3f0 |
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26-Apr-2023 |
Marijn Suijten <marijn.suijten@somainline.org> |
drm/msm/dpu: Implement tearcheck support on INTF block Since DPU 5.0.0 the TEARCHECK registers and interrupts moved out of the PINGPONG block and into the INTF. Implement the necessary callbacks in the INTF block, and use these callbacks together with the INTF_TEAR interrupts. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/534234/ Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-21-27ce1a5ab5c6@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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#
74fd7fda |
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16-Mar-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: use dpu_sw_pipe for dpu_hw_sspp callbacks Where feasible, use dpu_sw_pipe rather than a combo of dpu_hw_sspp and multirect_index/_mode arguments. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Tested-by: Abhinav Kumar <quic_abhinavk@quicinc.com> # sc7280 Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/527333/ Link: https://lore.kernel.org/r/20230316161653.4106395-9-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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#
3cfcd130 |
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16-Mar-2023 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: introduce struct dpu_sw_pipe Wrap SSPP and multirect index/mode into a single structure that represents software view on the pipe used. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Tested-by: Abhinav Kumar <quic_abhinavk@quicinc.com> # sc7280 Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/527326/ Link: https://lore.kernel.org/r/20230316161653.4106395-8-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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#
da10e280 |
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26-Apr-2022 |
Abhinav Kumar <quic_abhinavk@quicinc.com> |
drm/msm/dpu: add wb_idx to DRM traces in dpu_encoder Change the DRM traces to include both the intf_mode and wb_idx similar to the DRM prints in the previous change. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/483528/ Link: https://lore.kernel.org/r/1650984096-9964-20-git-send-email-quic_abhinavk@quicinc.com [DB: fixed indentation and added wb_idx to the dpu_enc_trigger_flush's TP_ARGS] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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#
1e7ac595 |
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16-Feb-2022 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: pass irq to dpu_encoder_helper_wait_for_irq() Pass IRQ number directly rather than passing an index in the dpu_encoder's irq table. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/474703/ Link: https://lore.kernel.org/r/20220217043148.480898-7-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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6ee11c41 |
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16-Feb-2022 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: get rid of dpu_encoder_helper_(un)register_irq Get rid of dpu_encoder_helper_register_irq/unregister_irq helpers, call dpu_core_register/unregister_callback directly, without surrounding them with helpers. Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/474698/ Link: https://lore.kernel.org/r/20220217043148.480898-5-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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#
c929ac60 |
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16-Feb-2022 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: allow just single IRQ callback DPU interrupts code allows multiple callbacks per interrut. In reality none of the interrupts is shared between blocks (and will probably never be). Drop support for registering multiple callbacks per interrupt to simplify interrupt handling code. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/474701/ Link: https://lore.kernel.org/r/20220217043148.480898-4-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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#
88e2d5b1 |
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04-Nov-2021 |
Sean Paul <seanpaul@chromium.org> |
drm/msm/dpu: Remove encoder->enable() hack encoder->commit() was being misused because there were some global resources which needed to be tweaked in encoder->enable() which were not accessible in dpu_encoder.c. That is no longer true and the redirect serves no purpose any longer. So remove the indirection. Tested-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20210913175747.47456-11-sean@poorly.run #v1 Link: https://patchwork.freedesktop.org/patch/msgid/20210915203834.1439-11-sean@poorly.run #v2 Link: https://patchwork.freedesktop.org/patch/msgid/20211001151145.55916-11-sean@poorly.run #v3 Changes in v2: -None Changes in v3: -None Changes in v4: -None Link: https://lore.kernel.org/r/20211105030434.2828845-11-sean@poorly.run Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
d94fc8f3 |
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16-May-2021 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: simplify IRQ enabling/disabling Merge dpu_core_irq_enable() into dpu_core_irq_register_callback() and dpu_core_irq_disable() into dpu_core_irq_unregister_callback(), because they are called in pairs. There is no need to have separate enable/disable pair, we can enable hardware IRQ when first callback is registered and when the last callback is unregistered. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/20210516202910.2141079-7-dmitry.baryshkov@linaro.org [fixup tracepoint compile warns] Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
667e9985 |
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16-May-2021 |
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
drm/msm/dpu: replace IRQ lookup with the data in hw catalog The IRQ table in the dpu_hw_interrupts.h is big, ugly, and hard to maintain. There are only few interrupts used from that table. Newer generations use different IRQ locations. Move this data to hw catalog. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/20210516202910.2141079-5-dmitry.baryshkov@linaro.org [fixup tracepoint compile warns/err] Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
5dce0c0b |
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28-Apr-2020 |
Ville Syrjälä <ville.syrjala@linux.intel.com> |
drm/msm/dpu: Stop copying around mode->private_flags The driver never sets mode->private_flags so copying it back and forth is entirely pointless. Stop doing it. Also drop private_flags from the tracepoint. Cc: Rob Clark <robdclark@gmail.com> Cc: Sean Paul <sean@poorly.run> Cc: linux-arm-msm@vger.kernel.org Cc: freedreno@lists.freedesktop.org Reviewed-by: Emil Velikov <emil.velikov@collabora.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200428171940.19552-5-ville.syrjala@linux.intel.com
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#
b721ea48 |
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27-Aug-2019 |
Rob Clark <robdclark@chromium.org> |
drm/msm/dpu: remove stray "\n" The extra line-break in traces was annoying me. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Sean Paul <sean@poorly.run> Signed-off-by: Rob Clark <robdclark@chromium.org>
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#
cb88482e |
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18-Jun-2019 |
Jayant Shekhar <jshekhar@codeaurora.org> |
drm/msm/dpu: clean up references of DPU custom bus scaling Since the upstream interconnect bus framework has landed upstream, the existing references of custom bus scaling needs to be cleaned up. Changes in v2: - Fixed build error due to partial clean up Changes in v3: - Condense multiple lines into a single line (Sean Paul) Changes in v4-v7: - None Signed-off-by: Sravanthi Kollukuduru <skolluku@codeaurora.org> Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Sean Paul <sean@poorly.run>
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#
97fb5e8d |
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29-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 284 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 and only version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 294 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.825281744@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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1a5e1778 |
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07-Dec-2018 |
Jeykumar Sankaran <jsanka@codeaurora.org> |
drm/msm/dpu: clean up redundant hw type struct dpu_hw_blk has hw block type info. Remove duplicate type tracking in struct dpu_rm_hw_blk. changes in v2: - remove redundant type in trace api's (Sean Paul) Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org>
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#
3e46c5df |
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16-Nov-2018 |
Sean Paul <seanpaul@chromium.org> |
drm/msm: dpu: Remove vblank_requested flag from dpu_crtc It's just for debugfs output, we don't need it Changes in v2: - None Cc: Jeykumar Sankaran <jsanka@codeaurora.org> Reviewed-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
3cf63cd5 |
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16-Nov-2018 |
Sean Paul <seanpaul@chromium.org> |
drm/msm: dpu: Handle crtc pm_runtime_resume() directly Instead of registering through dpu_power_handle just to get a call on runtime_resume, call the crtc function directly. Changes in v2: - None Reviewed-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
d05994df |
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16-Nov-2018 |
Sean Paul <seanpaul@chromium.org> |
drm/msm: dpu: Remove unused trace_dpu_perf_update_bus() Changes in v2: - None Reviewed-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
7a007a12 |
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05-Oct-2018 |
Bruce Wang <bzwang@chromium.org> |
drm/msm/dpu: Remove suspend state tracking from crtc Since drm core's modeset locks serialize atomic commits, we don't need to track whether or not we're in a suspended state from inside the crtc for dpu_crtc_enable/disable. This patch removes the suspend logic from the crtc and removes the relevant tracing from dpu_trace. Since we removed all calls to dpu_kms_is_suspend_state, we can remove that function and the suspend_state field of dpu_kms as well. v2: added patch to patchset v3: reworded commit body and moved deletion of dpu_kms_is_suspend_state and suspend_state to this patch Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Bruce Wang <bzwang@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
812eeeb6 |
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03-Oct-2018 |
Sean Paul <seanpaul@chromium.org> |
drm/msm: dpu: Add tracing around CTL_FLUSH I found these tracepoints useful for debugging cursor/ctl, someone else might find them useful too Reviewed-by: Jeykumar Sankaran <jsanka@codeaurora.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
f65f035f |
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19-Sep-2018 |
Sean Paul <seanpaul@chromium.org> |
drm/msm: dpu: Don't store/deref pointers in trace ringbuffer TP_printk is not synchronous, so storing pointers and then later dereferencing them is a Bad Idea. This patch stores everything locally to avoid display stomped memory. Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> [seanpaul fixed up commit msg typo on apply] Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
1bb4e701 |
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19-Sep-2018 |
Sean Paul <seanpaul@chromium.org> |
drm/msm: dpu: Add extra_flush_bits to trigger_flush trace It's useful to know which bits of the flush come from extra_flush_bits Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
9816b226 |
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05-Sep-2018 |
Jeykumar Sankaran <jsanka@codeaurora.org> |
drm/msm/dpu: remove cdm block support from resource manager Support for CDM block is not present in DPU. Remove CDM handlers from resource manager. changes in v4: - Introduced in the series changes in v5: - Remove catalog references to CDM (Sean) Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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#
25fdd593 |
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27-Jun-2018 |
Jeykumar Sankaran <jsanka@codeaurora.org> |
drm/msm: Add SDM845 DPU support SDM845 SoC includes the Mobile Display Sub System (MDSS) which is a top level wrapper consisting of Display Processing Unit (DPU) and display peripheral modules such as Display Serial Interface (DSI) and DisplayPort (DP). MDSS functions essentially as a back-end composition engine. It blends video and graphic images stored in the frame buffers and scans out the composed image to a display sink (over DSI/DP). The following diagram represents hardware blocks for a simple pipeline (two planes are present on a given crtc which is connected to a DSI connector): MDSS +---------------------------------+ | +-----------------------------+ | | | DPU | | | | +--------+ +--------+ | | | | | SSPP | | SSPP | | | | | +----+---+ +----+---+ | | | | | | | | | | +----v-----------v---+ | | | | | Layer Mixer (LM) | | | | | +--------------------+ | | | | +--------------------+ | | | | | PingPong (PP) | | | | | +--------------------+ | | | | +--------------------+ | | | | | INTERFACE (VIDEO) | | | | | +---+----------------+ | | | +------|----------------------+ | | | | | +------|---------------------+ | | | | DISPLAY PERIPHERALS | | | | +---v-+ +-----+ | | | | | DSI | | DP | | | | | +-----+ +-----+ | | | +----------------------------+ | +---------------------------------+ The number of DPU sub-blocks (i.e. SSPPs, LMs, PP blocks and INTFs) depends on SoC capabilities. Overview of DPU sub-blocks: --------------------------- * Source Surface Processor (SSPP): Refers to any of hardware pipes like ViG, DMA etc. Only ViG pipes are capable of performing format conversion, scaling and quality improvement for source surfaces. * Layer Mixer (LM): Blend source surfaces together (in requested zorder) * PingPong (PP): This block controls frame done interrupt output, EOL and EOF generation, overflow/underflow control. * Display interface (INTF): Timing generator and interface connecting the display peripherals. DRM components mapping to DPU architecture: ------------------------------------------ PLANEs maps to SSPPs CRTC maps to LMs Encoder maps to PPs, INTFs Data flow setup: --------------- MDSS hardware can support various data flows (e.g.): - Dual pipe: Output from two LMs combined to single display. - Split display: Output from two LMs connected to two separate interfaces. The hardware capabilities determine the number of concurrent data paths possible. Any control path (i.e. pipeline w/i DPU) can be routed to any of the hardware data paths. A given control path can be triggered, flushed and controlled independently. Changes in v3: - Move msm_media_info.h from uapi to dpu/ subdir - Remove preclose callback dpu (it's handled in core) - Fix kbuild warnings with parent_ops - Remove unused functions from dpu_core_irq - Rename mdss_phys to mdss - Rename mdp_phys address space to mdp - Drop _phys from vbif and regdma binding names Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org> Signed-off-by: Sravanthi Kollukuduru <skolluku@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> [robclark minor rebase] Signed-off-by: Rob Clark <robdclark@gmail.com>
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