1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. 3 */ 4 5#if !defined(_DPU_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ) 6#define _DPU_TRACE_H_ 7 8#include <linux/stringify.h> 9#include <linux/types.h> 10#include <linux/tracepoint.h> 11 12#include <drm/drm_rect.h> 13#include "dpu_crtc.h" 14#include "dpu_encoder_phys.h" 15#include "dpu_hw_mdss.h" 16#include "dpu_hw_vbif.h" 17#include "dpu_plane.h" 18 19#undef TRACE_SYSTEM 20#define TRACE_SYSTEM dpu 21#undef TRACE_INCLUDE_FILE 22#define TRACE_INCLUDE_FILE dpu_trace 23 24TRACE_EVENT(dpu_perf_set_qos_luts, 25 TP_PROTO(u32 pnum, u32 fmt, bool rt, u32 fl, 26 u32 lut, u32 lut_usage), 27 TP_ARGS(pnum, fmt, rt, fl, lut, lut_usage), 28 TP_STRUCT__entry( 29 __field(u32, pnum) 30 __field(u32, fmt) 31 __field(bool, rt) 32 __field(u32, fl) 33 __field(u64, lut) 34 __field(u32, lut_usage) 35 ), 36 TP_fast_assign( 37 __entry->pnum = pnum; 38 __entry->fmt = fmt; 39 __entry->rt = rt; 40 __entry->fl = fl; 41 __entry->lut = lut; 42 __entry->lut_usage = lut_usage; 43 ), 44 TP_printk("pnum=%d fmt=%x rt=%d fl=%d lut=0x%llx lut_usage=%d", 45 __entry->pnum, __entry->fmt, 46 __entry->rt, __entry->fl, 47 __entry->lut, __entry->lut_usage) 48); 49 50TRACE_EVENT(dpu_perf_set_danger_luts, 51 TP_PROTO(u32 pnum, u32 fmt, u32 mode, u32 danger_lut, 52 u32 safe_lut), 53 TP_ARGS(pnum, fmt, mode, danger_lut, safe_lut), 54 TP_STRUCT__entry( 55 __field(u32, pnum) 56 __field(u32, fmt) 57 __field(u32, mode) 58 __field(u32, danger_lut) 59 __field(u32, safe_lut) 60 ), 61 TP_fast_assign( 62 __entry->pnum = pnum; 63 __entry->fmt = fmt; 64 __entry->mode = mode; 65 __entry->danger_lut = danger_lut; 66 __entry->safe_lut = safe_lut; 67 ), 68 TP_printk("pnum=%d fmt=%x mode=%d luts[0x%x, 0x%x]", 69 __entry->pnum, __entry->fmt, 70 __entry->mode, __entry->danger_lut, 71 __entry->safe_lut) 72); 73 74TRACE_EVENT(dpu_perf_set_ot, 75 TP_PROTO(u32 pnum, u32 xin_id, u32 rd_lim, u32 vbif_idx), 76 TP_ARGS(pnum, xin_id, rd_lim, vbif_idx), 77 TP_STRUCT__entry( 78 __field(u32, pnum) 79 __field(u32, xin_id) 80 __field(u32, rd_lim) 81 __field(u32, vbif_idx) 82 ), 83 TP_fast_assign( 84 __entry->pnum = pnum; 85 __entry->xin_id = xin_id; 86 __entry->rd_lim = rd_lim; 87 __entry->vbif_idx = vbif_idx; 88 ), 89 TP_printk("pnum:%d xin_id:%d ot:%d vbif:%d", 90 __entry->pnum, __entry->xin_id, __entry->rd_lim, 91 __entry->vbif_idx) 92) 93 94TRACE_EVENT(dpu_cmd_release_bw, 95 TP_PROTO(u32 crtc_id), 96 TP_ARGS(crtc_id), 97 TP_STRUCT__entry( 98 __field(u32, crtc_id) 99 ), 100 TP_fast_assign( 101 __entry->crtc_id = crtc_id; 102 ), 103 TP_printk("crtc:%d", __entry->crtc_id) 104); 105 106TRACE_EVENT(tracing_mark_write, 107 TP_PROTO(int pid, const char *name, bool trace_begin), 108 TP_ARGS(pid, name, trace_begin), 109 TP_STRUCT__entry( 110 __field(int, pid) 111 __string(trace_name, name) 112 __field(bool, trace_begin) 113 ), 114 TP_fast_assign( 115 __entry->pid = pid; 116 __assign_str(trace_name, name); 117 __entry->trace_begin = trace_begin; 118 ), 119 TP_printk("%s|%d|%s", __entry->trace_begin ? "B" : "E", 120 __entry->pid, __get_str(trace_name)) 121) 122 123TRACE_EVENT(dpu_trace_counter, 124 TP_PROTO(int pid, char *name, int value), 125 TP_ARGS(pid, name, value), 126 TP_STRUCT__entry( 127 __field(int, pid) 128 __string(counter_name, name) 129 __field(int, value) 130 ), 131 TP_fast_assign( 132 __entry->pid = current->tgid; 133 __assign_str(counter_name, name); 134 __entry->value = value; 135 ), 136 TP_printk("%d|%s|%d", __entry->pid, 137 __get_str(counter_name), __entry->value) 138) 139 140TRACE_EVENT(dpu_perf_crtc_update, 141 TP_PROTO(u32 crtc, u64 bw_ctl, u32 core_clk_rate, 142 bool stop_req, bool update_bus, bool update_clk), 143 TP_ARGS(crtc, bw_ctl, core_clk_rate, stop_req, update_bus, update_clk), 144 TP_STRUCT__entry( 145 __field(u32, crtc) 146 __field(u64, bw_ctl) 147 __field(u32, core_clk_rate) 148 __field(bool, stop_req) 149 __field(u32, update_bus) 150 __field(u32, update_clk) 151 ), 152 TP_fast_assign( 153 __entry->crtc = crtc; 154 __entry->bw_ctl = bw_ctl; 155 __entry->core_clk_rate = core_clk_rate; 156 __entry->stop_req = stop_req; 157 __entry->update_bus = update_bus; 158 __entry->update_clk = update_clk; 159 ), 160 TP_printk( 161 "crtc=%d bw_ctl=%llu clk_rate=%u stop_req=%d u_bus=%d u_clk=%d", 162 __entry->crtc, 163 __entry->bw_ctl, 164 __entry->core_clk_rate, 165 __entry->stop_req, 166 __entry->update_bus, 167 __entry->update_clk) 168); 169 170DECLARE_EVENT_CLASS(dpu_irq_template, 171 TP_PROTO(unsigned int irq_reg, unsigned int irq_bit), 172 TP_ARGS(irq_reg, irq_bit), 173 TP_STRUCT__entry( 174 __field( unsigned int, irq_reg ) 175 __field( unsigned int, irq_bit ) 176 ), 177 TP_fast_assign( 178 __entry->irq_reg = irq_reg; 179 __entry->irq_bit = irq_bit; 180 ), 181 TP_printk("IRQ=[%d, %d]", __entry->irq_reg, __entry->irq_bit) 182); 183DEFINE_EVENT(dpu_irq_template, dpu_irq_register_success, 184 TP_PROTO(unsigned int irq_reg, unsigned int irq_bit), 185 TP_ARGS(irq_reg, irq_bit) 186); 187DEFINE_EVENT(dpu_irq_template, dpu_irq_unregister_success, 188 TP_PROTO(unsigned int irq_reg, unsigned int irq_bit), 189 TP_ARGS(irq_reg, irq_bit) 190); 191 192TRACE_EVENT(dpu_enc_irq_wait_success, 193 TP_PROTO(uint32_t drm_id, void *func, 194 unsigned int irq_reg, unsigned int irq_bit, enum dpu_pingpong pp_idx, int atomic_cnt), 195 TP_ARGS(drm_id, func, irq_reg, irq_bit, pp_idx, atomic_cnt), 196 TP_STRUCT__entry( 197 __field( uint32_t, drm_id ) 198 __field( void *, func ) 199 __field( unsigned int, irq_reg ) 200 __field( unsigned int, irq_bit ) 201 __field( enum dpu_pingpong, pp_idx ) 202 __field( int, atomic_cnt ) 203 ), 204 TP_fast_assign( 205 __entry->drm_id = drm_id; 206 __entry->func = func; 207 __entry->irq_reg = irq_reg; 208 __entry->irq_bit = irq_bit; 209 __entry->pp_idx = pp_idx; 210 __entry->atomic_cnt = atomic_cnt; 211 ), 212 TP_printk("id=%u, callback=%ps, IRQ=[%d, %d], pp=%d, atomic_cnt=%d", 213 __entry->drm_id, __entry->func, 214 __entry->irq_reg, __entry->irq_bit, __entry->pp_idx, __entry->atomic_cnt) 215); 216 217DECLARE_EVENT_CLASS(dpu_drm_obj_template, 218 TP_PROTO(uint32_t drm_id), 219 TP_ARGS(drm_id), 220 TP_STRUCT__entry( 221 __field( uint32_t, drm_id ) 222 ), 223 TP_fast_assign( 224 __entry->drm_id = drm_id; 225 ), 226 TP_printk("id=%u", __entry->drm_id) 227); 228DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_atomic_check, 229 TP_PROTO(uint32_t drm_id), 230 TP_ARGS(drm_id) 231); 232DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_mode_set, 233 TP_PROTO(uint32_t drm_id), 234 TP_ARGS(drm_id) 235); 236DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_disable, 237 TP_PROTO(uint32_t drm_id), 238 TP_ARGS(drm_id) 239); 240DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_kickoff, 241 TP_PROTO(uint32_t drm_id), 242 TP_ARGS(drm_id) 243); 244DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_prepare_kickoff, 245 TP_PROTO(uint32_t drm_id), 246 TP_ARGS(drm_id) 247); 248DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_prepare_kickoff_reset, 249 TP_PROTO(uint32_t drm_id), 250 TP_ARGS(drm_id) 251); 252DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_complete_flip, 253 TP_PROTO(uint32_t drm_id), 254 TP_ARGS(drm_id) 255); 256DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_vblank_cb, 257 TP_PROTO(uint32_t drm_id), 258 TP_ARGS(drm_id) 259); 260DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_complete_commit, 261 TP_PROTO(uint32_t drm_id), 262 TP_ARGS(drm_id) 263); 264DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_commit, 265 TP_PROTO(uint32_t drm_id), 266 TP_ARGS(drm_id) 267); 268DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_wait_for_commit_done, 269 TP_PROTO(uint32_t drm_id), 270 TP_ARGS(drm_id) 271); 272DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_runtime_resume, 273 TP_PROTO(uint32_t drm_id), 274 TP_ARGS(drm_id) 275); 276DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_rc_enable, 277 TP_PROTO(uint32_t drm_id), 278 TP_ARGS(drm_id) 279); 280DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_rc_disable, 281 TP_PROTO(uint32_t drm_id), 282 TP_ARGS(drm_id) 283); 284 285TRACE_EVENT(dpu_enc_enable, 286 TP_PROTO(uint32_t drm_id, int hdisplay, int vdisplay), 287 TP_ARGS(drm_id, hdisplay, vdisplay), 288 TP_STRUCT__entry( 289 __field( uint32_t, drm_id ) 290 __field( int, hdisplay ) 291 __field( int, vdisplay ) 292 ), 293 TP_fast_assign( 294 __entry->drm_id = drm_id; 295 __entry->hdisplay = hdisplay; 296 __entry->vdisplay = vdisplay; 297 ), 298 TP_printk("id=%u, mode=%dx%d", 299 __entry->drm_id, __entry->hdisplay, __entry->vdisplay) 300); 301 302DECLARE_EVENT_CLASS(dpu_enc_keyval_template, 303 TP_PROTO(uint32_t drm_id, int val), 304 TP_ARGS(drm_id, val), 305 TP_STRUCT__entry( 306 __field( uint32_t, drm_id ) 307 __field( int, val ) 308 ), 309 TP_fast_assign( 310 __entry->drm_id = drm_id; 311 __entry->val = val; 312 ), 313 TP_printk("id=%u, val=%d", __entry->drm_id, __entry->val) 314); 315DEFINE_EVENT(dpu_enc_keyval_template, dpu_enc_underrun_cb, 316 TP_PROTO(uint32_t drm_id, int count), 317 TP_ARGS(drm_id, count) 318); 319DEFINE_EVENT(dpu_enc_keyval_template, dpu_enc_trigger_start, 320 TP_PROTO(uint32_t drm_id, int ctl_idx), 321 TP_ARGS(drm_id, ctl_idx) 322); 323 324TRACE_EVENT(dpu_enc_atomic_check_flags, 325 TP_PROTO(uint32_t drm_id, unsigned int flags), 326 TP_ARGS(drm_id, flags), 327 TP_STRUCT__entry( 328 __field( uint32_t, drm_id ) 329 __field( unsigned int, flags ) 330 ), 331 TP_fast_assign( 332 __entry->drm_id = drm_id; 333 __entry->flags = flags; 334 ), 335 TP_printk("id=%u, flags=%u", 336 __entry->drm_id, __entry->flags) 337); 338 339DECLARE_EVENT_CLASS(dpu_enc_id_enable_template, 340 TP_PROTO(uint32_t drm_id, bool enable), 341 TP_ARGS(drm_id, enable), 342 TP_STRUCT__entry( 343 __field( uint32_t, drm_id ) 344 __field( bool, enable ) 345 ), 346 TP_fast_assign( 347 __entry->drm_id = drm_id; 348 __entry->enable = enable; 349 ), 350 TP_printk("id=%u, enable=%s", 351 __entry->drm_id, __entry->enable ? "true" : "false") 352); 353DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_vblank_cb, 354 TP_PROTO(uint32_t drm_id, bool enable), 355 TP_ARGS(drm_id, enable) 356); 357DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_frame_event_cb, 358 TP_PROTO(uint32_t drm_id, bool enable), 359 TP_ARGS(drm_id, enable) 360); 361DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_phys_cmd_connect_te, 362 TP_PROTO(uint32_t drm_id, bool enable), 363 TP_ARGS(drm_id, enable) 364); 365 366TRACE_EVENT(dpu_enc_rc, 367 TP_PROTO(uint32_t drm_id, u32 sw_event, bool idle_pc_supported, 368 int rc_state, const char *stage), 369 TP_ARGS(drm_id, sw_event, idle_pc_supported, rc_state, stage), 370 TP_STRUCT__entry( 371 __field( uint32_t, drm_id ) 372 __field( u32, sw_event ) 373 __field( bool, idle_pc_supported ) 374 __field( int, rc_state ) 375 __string( stage_str, stage ) 376 ), 377 TP_fast_assign( 378 __entry->drm_id = drm_id; 379 __entry->sw_event = sw_event; 380 __entry->idle_pc_supported = idle_pc_supported; 381 __entry->rc_state = rc_state; 382 __assign_str(stage_str, stage); 383 ), 384 TP_printk("%s: id:%u, sw_event:%d, idle_pc_supported:%s, rc_state:%d", 385 __get_str(stage_str), __entry->drm_id, __entry->sw_event, 386 __entry->idle_pc_supported ? "true" : "false", 387 __entry->rc_state) 388); 389 390TRACE_EVENT(dpu_enc_frame_done_cb_not_busy, 391 TP_PROTO(uint32_t drm_id, u32 event, char *intf_mode, enum dpu_intf intf_idx, 392 enum dpu_wb wb_idx), 393 TP_ARGS(drm_id, event, intf_mode, intf_idx, wb_idx), 394 TP_STRUCT__entry( 395 __field( uint32_t, drm_id ) 396 __field( u32, event ) 397 __string( intf_mode_str, intf_mode ) 398 __field( enum dpu_intf, intf_idx ) 399 __field( enum dpu_wb, wb_idx ) 400 ), 401 TP_fast_assign( 402 __entry->drm_id = drm_id; 403 __entry->event = event; 404 __assign_str(intf_mode_str, intf_mode); 405 __entry->intf_idx = intf_idx; 406 __entry->wb_idx = wb_idx; 407 ), 408 TP_printk("id=%u, event=%u, intf_mode=%s intf=%d wb=%d", __entry->drm_id, 409 __entry->event, __get_str(intf_mode_str), 410 __entry->intf_idx, __entry->wb_idx) 411); 412 413TRACE_EVENT(dpu_enc_frame_done_cb, 414 TP_PROTO(uint32_t drm_id, unsigned int idx, 415 unsigned long frame_busy_mask), 416 TP_ARGS(drm_id, idx, frame_busy_mask), 417 TP_STRUCT__entry( 418 __field( uint32_t, drm_id ) 419 __field( unsigned int, idx ) 420 __field( unsigned long, frame_busy_mask ) 421 ), 422 TP_fast_assign( 423 __entry->drm_id = drm_id; 424 __entry->idx = idx; 425 __entry->frame_busy_mask = frame_busy_mask; 426 ), 427 TP_printk("id=%u, idx=%u, frame_busy_mask=%lx", __entry->drm_id, 428 __entry->idx, __entry->frame_busy_mask) 429); 430 431TRACE_EVENT(dpu_enc_trigger_flush, 432 TP_PROTO(uint32_t drm_id, char *intf_mode, enum dpu_intf intf_idx, enum dpu_wb wb_idx, 433 int pending_kickoff_cnt, int ctl_idx, u32 extra_flush_bits, 434 u32 pending_flush_ret), 435 TP_ARGS(drm_id, intf_mode, intf_idx, wb_idx, pending_kickoff_cnt, ctl_idx, 436 extra_flush_bits, pending_flush_ret), 437 TP_STRUCT__entry( 438 __field( uint32_t, drm_id ) 439 __string( intf_mode_str, intf_mode ) 440 __field( enum dpu_intf, intf_idx ) 441 __field( enum dpu_wb, wb_idx ) 442 __field( int, pending_kickoff_cnt ) 443 __field( int, ctl_idx ) 444 __field( u32, extra_flush_bits ) 445 __field( u32, pending_flush_ret ) 446 ), 447 TP_fast_assign( 448 __entry->drm_id = drm_id; 449 __assign_str(intf_mode_str, intf_mode); 450 __entry->intf_idx = intf_idx; 451 __entry->wb_idx = wb_idx; 452 __entry->pending_kickoff_cnt = pending_kickoff_cnt; 453 __entry->ctl_idx = ctl_idx; 454 __entry->extra_flush_bits = extra_flush_bits; 455 __entry->pending_flush_ret = pending_flush_ret; 456 ), 457 TP_printk("id=%u, intf_mode=%s, intf_idx=%d, wb_idx=%d, pending_kickoff_cnt=%d ctl_idx=%d " 458 "extra_flush_bits=0x%x pending_flush_ret=0x%x", 459 __entry->drm_id, __get_str(intf_mode_str), __entry->intf_idx, __entry->wb_idx, 460 __entry->pending_kickoff_cnt, __entry->ctl_idx, 461 __entry->extra_flush_bits, __entry->pending_flush_ret) 462); 463 464DECLARE_EVENT_CLASS(dpu_id_event_template, 465 TP_PROTO(uint32_t drm_id, u32 event), 466 TP_ARGS(drm_id, event), 467 TP_STRUCT__entry( 468 __field( uint32_t, drm_id ) 469 __field( u32, event ) 470 ), 471 TP_fast_assign( 472 __entry->drm_id = drm_id; 473 __entry->event = event; 474 ), 475 TP_printk("id=%u, event=%u", __entry->drm_id, __entry->event) 476); 477DEFINE_EVENT(dpu_id_event_template, dpu_enc_frame_done_timeout, 478 TP_PROTO(uint32_t drm_id, u32 event), 479 TP_ARGS(drm_id, event) 480); 481DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_cb, 482 TP_PROTO(uint32_t drm_id, u32 event), 483 TP_ARGS(drm_id, event) 484); 485DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_done, 486 TP_PROTO(uint32_t drm_id, u32 event), 487 TP_ARGS(drm_id, event) 488); 489DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_more_pending, 490 TP_PROTO(uint32_t drm_id, u32 event), 491 TP_ARGS(drm_id, event) 492); 493 494TRACE_EVENT(dpu_enc_wait_event_timeout, 495 TP_PROTO(uint32_t drm_id, unsigned int irq_reg, unsigned int irq_bit, int rc, s64 time, 496 s64 expected_time, int atomic_cnt), 497 TP_ARGS(drm_id, irq_reg, irq_bit, rc, time, expected_time, atomic_cnt), 498 TP_STRUCT__entry( 499 __field( uint32_t, drm_id ) 500 __field( unsigned int, irq_reg ) 501 __field( unsigned int, irq_bit ) 502 __field( int, rc ) 503 __field( s64, time ) 504 __field( s64, expected_time ) 505 __field( int, atomic_cnt ) 506 ), 507 TP_fast_assign( 508 __entry->drm_id = drm_id; 509 __entry->irq_reg = irq_reg; 510 __entry->irq_bit = irq_bit; 511 __entry->rc = rc; 512 __entry->time = time; 513 __entry->expected_time = expected_time; 514 __entry->atomic_cnt = atomic_cnt; 515 ), 516 TP_printk("id=%u, IRQ=[%d, %d], rc=%d, time=%lld, expected=%lld cnt=%d", 517 __entry->drm_id, __entry->irq_reg, __entry->irq_bit, __entry->rc, __entry->time, 518 __entry->expected_time, __entry->atomic_cnt) 519); 520 521TRACE_EVENT(dpu_enc_phys_cmd_irq_enable, 522 TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, 523 int refcnt), 524 TP_ARGS(drm_id, pp, refcnt), 525 TP_STRUCT__entry( 526 __field( uint32_t, drm_id ) 527 __field( enum dpu_pingpong, pp ) 528 __field( int, refcnt ) 529 ), 530 TP_fast_assign( 531 __entry->drm_id = drm_id; 532 __entry->pp = pp; 533 __entry->refcnt = refcnt; 534 ), 535 TP_printk("id=%u, pp=%d, refcnt=%d", __entry->drm_id, 536 __entry->pp, 537 __entry->refcnt) 538); 539 540TRACE_EVENT(dpu_enc_phys_cmd_irq_disable, 541 TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, 542 int refcnt), 543 TP_ARGS(drm_id, pp, refcnt), 544 TP_STRUCT__entry( 545 __field( uint32_t, drm_id ) 546 __field( enum dpu_pingpong, pp ) 547 __field( int, refcnt ) 548 ), 549 TP_fast_assign( 550 __entry->drm_id = drm_id; 551 __entry->pp = pp; 552 __entry->refcnt = refcnt; 553 ), 554 TP_printk("id=%u, pp=%d, refcnt=%d", __entry->drm_id, 555 __entry->pp, 556 __entry->refcnt) 557); 558 559TRACE_EVENT(dpu_enc_phys_cmd_pp_tx_done, 560 TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int new_count, 561 u32 event), 562 TP_ARGS(drm_id, pp, new_count, event), 563 TP_STRUCT__entry( 564 __field( uint32_t, drm_id ) 565 __field( enum dpu_pingpong, pp ) 566 __field( int, new_count ) 567 __field( u32, event ) 568 ), 569 TP_fast_assign( 570 __entry->drm_id = drm_id; 571 __entry->pp = pp; 572 __entry->new_count = new_count; 573 __entry->event = event; 574 ), 575 TP_printk("id=%u, pp=%d, new_count=%d, event=%u", __entry->drm_id, 576 __entry->pp, __entry->new_count, __entry->event) 577); 578 579TRACE_EVENT(dpu_enc_phys_cmd_pdone_timeout, 580 TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int timeout_count, 581 int kickoff_count, u32 event), 582 TP_ARGS(drm_id, pp, timeout_count, kickoff_count, event), 583 TP_STRUCT__entry( 584 __field( uint32_t, drm_id ) 585 __field( enum dpu_pingpong, pp ) 586 __field( int, timeout_count ) 587 __field( int, kickoff_count ) 588 __field( u32, event ) 589 ), 590 TP_fast_assign( 591 __entry->drm_id = drm_id; 592 __entry->pp = pp; 593 __entry->timeout_count = timeout_count; 594 __entry->kickoff_count = kickoff_count; 595 __entry->event = event; 596 ), 597 TP_printk("id=%u, pp=%d, timeout_count=%d, kickoff_count=%d, event=%u", 598 __entry->drm_id, __entry->pp, __entry->timeout_count, 599 __entry->kickoff_count, __entry->event) 600); 601 602TRACE_EVENT(dpu_enc_phys_vid_post_kickoff, 603 TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx), 604 TP_ARGS(drm_id, intf_idx), 605 TP_STRUCT__entry( 606 __field( uint32_t, drm_id ) 607 __field( enum dpu_intf, intf_idx ) 608 ), 609 TP_fast_assign( 610 __entry->drm_id = drm_id; 611 __entry->intf_idx = intf_idx; 612 ), 613 TP_printk("id=%u, intf_idx=%d", __entry->drm_id, __entry->intf_idx) 614); 615 616TRACE_EVENT(dpu_enc_phys_vid_irq_enable, 617 TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, 618 int refcnt), 619 TP_ARGS(drm_id, intf_idx, refcnt), 620 TP_STRUCT__entry( 621 __field( uint32_t, drm_id ) 622 __field( enum dpu_intf, intf_idx ) 623 __field( int, refcnt ) 624 ), 625 TP_fast_assign( 626 __entry->drm_id = drm_id; 627 __entry->intf_idx = intf_idx; 628 __entry->refcnt = refcnt; 629 ), 630 TP_printk("id=%u, intf_idx=%d refcnt=%d", __entry->drm_id, 631 __entry->intf_idx, 632 __entry->drm_id) 633); 634 635TRACE_EVENT(dpu_enc_phys_vid_irq_disable, 636 TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, 637 int refcnt), 638 TP_ARGS(drm_id, intf_idx, refcnt), 639 TP_STRUCT__entry( 640 __field( uint32_t, drm_id ) 641 __field( enum dpu_intf, intf_idx ) 642 __field( int, refcnt ) 643 ), 644 TP_fast_assign( 645 __entry->drm_id = drm_id; 646 __entry->intf_idx = intf_idx; 647 __entry->refcnt = refcnt; 648 ), 649 TP_printk("id=%u, intf_idx=%d refcnt=%d", __entry->drm_id, 650 __entry->intf_idx, 651 __entry->drm_id) 652); 653 654TRACE_EVENT(dpu_crtc_setup_mixer, 655 TP_PROTO(uint32_t crtc_id, uint32_t plane_id, 656 struct drm_plane_state *state, struct dpu_plane_state *pstate, 657 uint32_t stage_idx, uint32_t pixel_format, 658 uint64_t modifier), 659 TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx, 660 pixel_format, modifier), 661 TP_STRUCT__entry( 662 __field( uint32_t, crtc_id ) 663 __field( uint32_t, plane_id ) 664 __field( uint32_t, fb_id ) 665 __field_struct( struct drm_rect, src_rect ) 666 __field_struct( struct drm_rect, dst_rect ) 667 __field( uint32_t, stage_idx ) 668 __field( enum dpu_stage, stage ) 669 __field( enum dpu_sspp, sspp ) 670 __field( uint32_t, multirect_idx ) 671 __field( uint32_t, multirect_mode ) 672 __field( uint32_t, pixel_format ) 673 __field( uint64_t, modifier ) 674 ), 675 TP_fast_assign( 676 __entry->crtc_id = crtc_id; 677 __entry->plane_id = plane_id; 678 __entry->fb_id = state ? state->fb->base.id : 0; 679 __entry->src_rect = drm_plane_state_src(state); 680 __entry->dst_rect = drm_plane_state_dest(state); 681 __entry->stage_idx = stage_idx; 682 __entry->stage = pstate->stage; 683 __entry->sspp = pstate->pipe.sspp->idx; 684 __entry->multirect_idx = pstate->pipe.multirect_index; 685 __entry->multirect_mode = pstate->pipe.multirect_mode; 686 __entry->pixel_format = pixel_format; 687 __entry->modifier = modifier; 688 ), 689 TP_printk("crtc_id:%u plane_id:%u fb_id:%u src:" DRM_RECT_FP_FMT 690 " dst:" DRM_RECT_FMT " stage_idx:%u stage:%d, sspp:%d " 691 "multirect_index:%d multirect_mode:%u pix_format:%u " 692 "modifier:%llu", 693 __entry->crtc_id, __entry->plane_id, __entry->fb_id, 694 DRM_RECT_FP_ARG(&__entry->src_rect), 695 DRM_RECT_ARG(&__entry->dst_rect), 696 __entry->stage_idx, __entry->stage, __entry->sspp, 697 __entry->multirect_idx, __entry->multirect_mode, 698 __entry->pixel_format, __entry->modifier) 699); 700 701TRACE_EVENT(dpu_crtc_setup_lm_bounds, 702 TP_PROTO(uint32_t drm_id, int mixer, struct drm_rect *bounds), 703 TP_ARGS(drm_id, mixer, bounds), 704 TP_STRUCT__entry( 705 __field( uint32_t, drm_id ) 706 __field( int, mixer ) 707 __field_struct( struct drm_rect, bounds ) 708 ), 709 TP_fast_assign( 710 __entry->drm_id = drm_id; 711 __entry->mixer = mixer; 712 __entry->bounds = *bounds; 713 ), 714 TP_printk("id:%u mixer:%d bounds:" DRM_RECT_FMT, __entry->drm_id, 715 __entry->mixer, DRM_RECT_ARG(&__entry->bounds)) 716); 717 718TRACE_EVENT(dpu_crtc_vblank_enable, 719 TP_PROTO(uint32_t drm_id, uint32_t enc_id, bool enable, 720 struct dpu_crtc *crtc), 721 TP_ARGS(drm_id, enc_id, enable, crtc), 722 TP_STRUCT__entry( 723 __field( uint32_t, drm_id ) 724 __field( uint32_t, enc_id ) 725 __field( bool, enable ) 726 __field( bool, enabled ) 727 ), 728 TP_fast_assign( 729 __entry->drm_id = drm_id; 730 __entry->enc_id = enc_id; 731 __entry->enable = enable; 732 __entry->enabled = crtc->enabled; 733 ), 734 TP_printk("id:%u encoder:%u enable:%s state{enabled:%s}", 735 __entry->drm_id, __entry->enc_id, 736 __entry->enable ? "true" : "false", 737 __entry->enabled ? "true" : "false") 738); 739 740DECLARE_EVENT_CLASS(dpu_crtc_enable_template, 741 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc), 742 TP_ARGS(drm_id, enable, crtc), 743 TP_STRUCT__entry( 744 __field( uint32_t, drm_id ) 745 __field( bool, enable ) 746 __field( bool, enabled ) 747 ), 748 TP_fast_assign( 749 __entry->drm_id = drm_id; 750 __entry->enable = enable; 751 __entry->enabled = crtc->enabled; 752 ), 753 TP_printk("id:%u enable:%s state{enabled:%s}", 754 __entry->drm_id, __entry->enable ? "true" : "false", 755 __entry->enabled ? "true" : "false") 756); 757DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_enable, 758 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc), 759 TP_ARGS(drm_id, enable, crtc) 760); 761DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_disable, 762 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc), 763 TP_ARGS(drm_id, enable, crtc) 764); 765DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_vblank, 766 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc), 767 TP_ARGS(drm_id, enable, crtc) 768); 769 770TRACE_EVENT(dpu_crtc_disable_frame_pending, 771 TP_PROTO(uint32_t drm_id, int frame_pending), 772 TP_ARGS(drm_id, frame_pending), 773 TP_STRUCT__entry( 774 __field( uint32_t, drm_id ) 775 __field( int, frame_pending ) 776 ), 777 TP_fast_assign( 778 __entry->drm_id = drm_id; 779 __entry->frame_pending = frame_pending; 780 ), 781 TP_printk("id:%u frame_pending:%d", __entry->drm_id, 782 __entry->frame_pending) 783); 784 785TRACE_EVENT(dpu_plane_set_scanout, 786 TP_PROTO(struct dpu_sw_pipe *pipe, struct dpu_hw_fmt_layout *layout), 787 TP_ARGS(pipe, layout), 788 TP_STRUCT__entry( 789 __field( enum dpu_sspp, index ) 790 __field_struct( struct dpu_hw_fmt_layout, layout ) 791 __field( enum dpu_sspp_multirect_index, multirect_index) 792 ), 793 TP_fast_assign( 794 __entry->index = pipe->sspp->idx; 795 __entry->layout = *layout; 796 __entry->multirect_index = pipe->multirect_index; 797 ), 798 TP_printk("index:%d layout:{%ux%u @ [%u/%u, %u/%u, %u/%u, %u/%u]} " 799 "multirect_index:%d", __entry->index, __entry->layout.width, 800 __entry->layout.height, __entry->layout.plane_addr[0], 801 __entry->layout.plane_size[0], 802 __entry->layout.plane_addr[1], 803 __entry->layout.plane_size[1], 804 __entry->layout.plane_addr[2], 805 __entry->layout.plane_size[2], 806 __entry->layout.plane_addr[3], 807 __entry->layout.plane_size[3], __entry->multirect_index) 808); 809 810TRACE_EVENT(dpu_plane_disable, 811 TP_PROTO(uint32_t drm_id, bool is_virtual, uint32_t multirect_mode), 812 TP_ARGS(drm_id, is_virtual, multirect_mode), 813 TP_STRUCT__entry( 814 __field( uint32_t, drm_id ) 815 __field( bool, is_virtual ) 816 __field( uint32_t, multirect_mode ) 817 ), 818 TP_fast_assign( 819 __entry->drm_id = drm_id; 820 __entry->is_virtual = is_virtual; 821 __entry->multirect_mode = multirect_mode; 822 ), 823 TP_printk("id:%u is_virtual:%s multirect_mode:%u", __entry->drm_id, 824 __entry->is_virtual ? "true" : "false", 825 __entry->multirect_mode) 826); 827 828DECLARE_EVENT_CLASS(dpu_rm_iter_template, 829 TP_PROTO(uint32_t id, uint32_t enc_id), 830 TP_ARGS(id, enc_id), 831 TP_STRUCT__entry( 832 __field( uint32_t, id ) 833 __field( uint32_t, enc_id ) 834 ), 835 TP_fast_assign( 836 __entry->id = id; 837 __entry->enc_id = enc_id; 838 ), 839 TP_printk("id:%d enc_id:%u", __entry->id, __entry->enc_id) 840); 841DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_intf, 842 TP_PROTO(uint32_t id, uint32_t enc_id), 843 TP_ARGS(id, enc_id) 844); 845DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_ctls, 846 TP_PROTO(uint32_t id, uint32_t enc_id), 847 TP_ARGS(id, enc_id) 848); 849 850TRACE_EVENT(dpu_rm_reserve_lms, 851 TP_PROTO(uint32_t id, uint32_t enc_id, uint32_t pp_id), 852 TP_ARGS(id, enc_id, pp_id), 853 TP_STRUCT__entry( 854 __field( uint32_t, id ) 855 __field( uint32_t, enc_id ) 856 __field( uint32_t, pp_id ) 857 ), 858 TP_fast_assign( 859 __entry->id = id; 860 __entry->enc_id = enc_id; 861 __entry->pp_id = pp_id; 862 ), 863 TP_printk("id:%d enc_id:%u pp_id:%u", __entry->id, 864 __entry->enc_id, __entry->pp_id) 865); 866 867TRACE_EVENT(dpu_vbif_wait_xin_halt_fail, 868 TP_PROTO(enum dpu_vbif index, u32 xin_id), 869 TP_ARGS(index, xin_id), 870 TP_STRUCT__entry( 871 __field( enum dpu_vbif, index ) 872 __field( u32, xin_id ) 873 ), 874 TP_fast_assign( 875 __entry->index = index; 876 __entry->xin_id = xin_id; 877 ), 878 TP_printk("index:%d xin_id:%u", __entry->index, __entry->xin_id) 879); 880 881TRACE_EVENT(dpu_pp_connect_ext_te, 882 TP_PROTO(enum dpu_pingpong pp, u32 cfg), 883 TP_ARGS(pp, cfg), 884 TP_STRUCT__entry( 885 __field( enum dpu_pingpong, pp ) 886 __field( u32, cfg ) 887 ), 888 TP_fast_assign( 889 __entry->pp = pp; 890 __entry->cfg = cfg; 891 ), 892 TP_printk("pp:%d cfg:%u", __entry->pp, __entry->cfg) 893); 894 895TRACE_EVENT(dpu_intf_connect_ext_te, 896 TP_PROTO(enum dpu_intf intf, u32 cfg), 897 TP_ARGS(intf, cfg), 898 TP_STRUCT__entry( 899 __field( enum dpu_intf, intf ) 900 __field( u32, cfg ) 901 ), 902 TP_fast_assign( 903 __entry->intf = intf; 904 __entry->cfg = cfg; 905 ), 906 TP_printk("intf:%d cfg:%u", __entry->intf, __entry->cfg) 907); 908 909TRACE_EVENT(dpu_core_irq_register_callback, 910 TP_PROTO(unsigned int irq_reg, unsigned int irq_bit, void *callback), 911 TP_ARGS(irq_reg, irq_bit, callback), 912 TP_STRUCT__entry( 913 __field( unsigned int, irq_reg ) 914 __field( unsigned int, irq_bit ) 915 __field( void *, callback) 916 ), 917 TP_fast_assign( 918 __entry->irq_reg = irq_reg; 919 __entry->irq_bit = irq_bit; 920 __entry->callback = callback; 921 ), 922 TP_printk("IRQ=[%d, %d] callback:%ps", __entry->irq_reg, __entry->irq_bit, 923 __entry->callback) 924); 925 926TRACE_EVENT(dpu_core_irq_unregister_callback, 927 TP_PROTO(unsigned int irq_reg, unsigned int irq_bit), 928 TP_ARGS(irq_reg, irq_bit), 929 TP_STRUCT__entry( 930 __field( unsigned int, irq_reg ) 931 __field( unsigned int, irq_bit ) 932 ), 933 TP_fast_assign( 934 __entry->irq_reg = irq_reg; 935 __entry->irq_bit = irq_bit; 936 ), 937 TP_printk("IRQ=[%d, %d]", __entry->irq_reg, __entry->irq_bit) 938); 939 940TRACE_EVENT(dpu_core_perf_update_clk, 941 TP_PROTO(struct drm_device *dev, bool stop_req, u64 clk_rate), 942 TP_ARGS(dev, stop_req, clk_rate), 943 TP_STRUCT__entry( 944 __string( dev_name, dev->unique ) 945 __field( bool, stop_req ) 946 __field( u64, clk_rate ) 947 ), 948 TP_fast_assign( 949 __assign_str(dev_name, dev->unique); 950 __entry->stop_req = stop_req; 951 __entry->clk_rate = clk_rate; 952 ), 953 TP_printk("dev:%s stop_req:%s clk_rate:%llu", __get_str(dev_name), 954 __entry->stop_req ? "true" : "false", __entry->clk_rate) 955); 956 957TRACE_EVENT(dpu_hw_ctl_update_pending_flush, 958 TP_PROTO(u32 new_bits, u32 pending_mask), 959 TP_ARGS(new_bits, pending_mask), 960 TP_STRUCT__entry( 961 __field( u32, new_bits ) 962 __field( u32, pending_mask ) 963 ), 964 TP_fast_assign( 965 __entry->new_bits = new_bits; 966 __entry->pending_mask = pending_mask; 967 ), 968 TP_printk("new=%x existing=%x", __entry->new_bits, 969 __entry->pending_mask) 970); 971 972DECLARE_EVENT_CLASS(dpu_hw_ctl_pending_flush_template, 973 TP_PROTO(u32 pending_mask, u32 ctl_flush), 974 TP_ARGS(pending_mask, ctl_flush), 975 TP_STRUCT__entry( 976 __field( u32, pending_mask ) 977 __field( u32, ctl_flush ) 978 ), 979 TP_fast_assign( 980 __entry->pending_mask = pending_mask; 981 __entry->ctl_flush = ctl_flush; 982 ), 983 TP_printk("pending_mask=%x CTL_FLUSH=%x", __entry->pending_mask, 984 __entry->ctl_flush) 985); 986DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_clear_pending_flush, 987 TP_PROTO(u32 pending_mask, u32 ctl_flush), 988 TP_ARGS(pending_mask, ctl_flush) 989); 990DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, 991 dpu_hw_ctl_trigger_pending_flush, 992 TP_PROTO(u32 pending_mask, u32 ctl_flush), 993 TP_ARGS(pending_mask, ctl_flush) 994); 995DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_trigger_prepare, 996 TP_PROTO(u32 pending_mask, u32 ctl_flush), 997 TP_ARGS(pending_mask, ctl_flush) 998); 999DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_trigger_start, 1000 TP_PROTO(u32 pending_mask, u32 ctl_flush), 1001 TP_ARGS(pending_mask, ctl_flush) 1002); 1003 1004#define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0) 1005#define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1) 1006#define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__) 1007 1008#define DPU_ATRACE_INT(name, value) \ 1009 trace_dpu_trace_counter(current->tgid, name, value) 1010 1011#endif /* _DPU_TRACE_H_ */ 1012 1013/* This part must be outside protection */ 1014#undef TRACE_INCLUDE_PATH 1015#define TRACE_INCLUDE_PATH . 1016#include <trace/define_trace.h> 1017