Searched refs:divider (Results 101 - 125 of 147) sorted by path

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/linux-master/drivers/iio/imu/inv_mpu6050/
H A Dinv_mpu_core.c111 .divider = INV_MPU6050_FIFO_RATE_TO_DIVIDER(50),
128 .divider = INV_MPU6050_FIFO_RATE_TO_DIVIDER(50),
538 d = st->chip_config.divider;
556 NSEC_PER_SEC / INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
604 freq_hz = INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
955 /* compute the chip sample rate divider */
962 if (d == st->chip_config.divider) {
981 st->chip_config.divider = d;
1014 fifo_rate = INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
H A Dinv_mpu_iio.h111 * @divider: chip sample rate divider (sample rate divider - 1)
126 u8 divider; member in struct:inv_mpu6050_chip_config
378 /* return the frequency divider (chip sample rate divider + 1) */
380 ((st)->chip_config.divider + 1)
381 /* chip sample rate divider to fifo rate */
384 #define INV_MPU6050_DIVIDER_TO_FIFO_RATE(divider) \
385 (INV_MPU6050_INTERNAL_FREQ_HZ / ((divider)
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H A Dinv_mpu_ring.c115 fifo_period = NSEC_PER_SEC / INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
/linux-master/drivers/media/dvb-frontends/
H A Dstv6110.c226 u32 nbsteps, divider, psd2, freq; local
231 divider = (priv->regs[RSTV6110_TUNING2] & 0x0f) << 8;
232 divider += priv->regs[RSTV6110_TUNING1];
239 freq = divider * (priv->mclk / 1000);
252 u32 divider, ref, p, presc, i, result_freq, vco_freq; local
300 divider = (((frequency * 1000) + (ref >> 1)) / ref);
306 /* NDIV_MSB = MSB(divider) */
308 priv->regs[RSTV6110_TUNING2] |= (((divider) >> 8) & 0x0f);
310 /* NDIV_LSB, LSB(divider) */
311 priv->regs[RSTV6110_TUNING1] = (divider
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H A Dstv6110x.c111 u32 rDiv, divider; local
144 divider = (frequency * R_DIV(rDivOpt) * pVal) / REFCLOCK_kHz;
145 divider = (divider + 5) / 10;
148 STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG1], TNG1_N_DIV_11_8, MSB(divider));
149 STV6110x_SETFIELD(stv6110x->regs[STV6110x_TNG0], TNG0_N_DIV_7_0, LSB(divider));
235 /* setup divider */
/linux-master/drivers/media/i2c/cx25840/
H A Dcx25840-ir.c124 * Note the largest clock divider value of 0xffff corresponds to:
145 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) argument
147 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, (divider + 1) * 16);
150 static inline unsigned int clock_divider_to_freq(unsigned int divider, argument
154 (divider + 1) * rollovers);
195 static u32 clock_divider_to_resolution(u16 divider) argument
202 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000,
206 static u64 pulse_width_count_to_ns(u16 count, u16 divider) argument
215 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
224 static u16 ns_to_pulse_width_count(u32 ns, u16 divider)
248 pulse_width_count_to_us(u16 count, u16 divider) argument
391 txclk_tx_s_carrier(struct i2c_client *c, unsigned int freq, u16 *divider) argument
400 rxclk_rx_s_carrier(struct i2c_client *c, unsigned int freq, u16 *divider) argument
409 txclk_tx_s_max_pulse_width(struct i2c_client *c, u32 ns, u16 *divider) argument
422 rxclk_rx_s_max_pulse_width(struct i2c_client *c, u32 ns, u16 *divider) argument
633 u16 divider; local
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/linux-master/drivers/media/i2c/
H A Dmt9t112.c409 priv->info->divider.m, priv->info->divider.n,
410 priv->info->divider.p1, priv->info->divider.p2,
411 priv->info->divider.p3, priv->info->divider.p4,
412 priv->info->divider.p5, priv->info->divider.p6,
413 priv->info->divider.p7);
H A Dov4689.c148 u32 divider; member in struct:ov4689_gain_range
293 .divider = 1,
301 .divider = 2,
309 .divider = 4,
317 .divider = 8,
628 *result = clamp(range->offset + (logical_gain) / range->divider,
/linux-master/drivers/media/pci/cx23885/
H A Dcx23888-ir.c163 * Note the largest clock divider value of 0xffff corresponds to:
184 static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) argument
186 return DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ, (divider + 1) * 16);
189 static inline unsigned int clock_divider_to_freq(unsigned int divider, argument
193 (divider + 1) * rollovers);
234 static u32 clock_divider_to_resolution(u16 divider) argument
241 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000,
245 static u64 pulse_width_count_to_ns(u16 count, u16 divider) argument
254 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
261 static unsigned int pulse_width_count_to_us(u16 count, u16 divider) argument
411 txclk_tx_s_carrier(struct cx23885_dev *dev, unsigned int freq, u16 *divider) argument
420 rxclk_rx_s_carrier(struct cx23885_dev *dev, unsigned int freq, u16 *divider) argument
429 txclk_tx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns, u16 *divider) argument
442 rxclk_rx_s_max_pulse_width(struct cx23885_dev *dev, u32 ns, u16 *divider) argument
634 u16 divider = (u16) atomic_read(&state->rxclk_divider); local
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/linux-master/drivers/media/platform/ti/omap3isp/
H A Disp.c159 static void isp_xclk_update(struct isp_xclk *xclk, u32 divider) argument
165 divider << ISPTCTRL_CTRL_DIVA_SHIFT);
170 divider << ISPTCTRL_CTRL_DIVB_SHIFT);
197 isp_xclk_update(xclk, xclk->divider);
220 return parent_rate / xclk->divider;
225 u32 divider; local
235 divider = DIV_ROUND_CLOSEST(parent_rate, *rate);
236 if (divider >= ISPTCTRL_CTRL_DIV_BYPASS)
237 divider = ISPTCTRL_CTRL_DIV_BYPASS - 1;
239 *rate = parent_rate / divider;
255 u32 divider; local
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H A Disp.h131 spinlock_t lock; /* Protects enabled and divider */
133 unsigned int divider; member in struct:isp_xclk
/linux-master/drivers/media/rc/
H A Dir-xmp-decoder.c75 int divider, i; local
89 * the 4th nibble should be 15 so base the divider on this
91 * the divider to compensate for fluctuations in the signal
93 divider = (n[3] - XMP_NIBBLE_PREFIX) / 15 - 2000;
94 if (divider < 50) {
95 dev_dbg(&dev->dev, "divider to small %d.\n",
96 divider);
103 n[i] = (n[i] - XMP_NIBBLE_PREFIX) / divider;
/linux-master/drivers/media/usb/dvb-usb/
H A Ddib0700_core.c433 u16 divider; local
445 divider = (u16) (30000 / scl_kHz);
447 st->buf[2] = (u8) (divider >> 8);
448 st->buf[3] = (u8) (divider & 0xff);
449 divider = (u16) (72000 / scl_kHz);
450 st->buf[4] = (u8) (divider >> 8);
451 st->buf[5] = (u8) (divider & 0xff);
452 divider = (u16) (72000 / scl_kHz); /* clock: 72MHz */
453 st->buf[6] = (u8) (divider >> 8);
454 st->buf[7] = (u8) (divider
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/linux-master/drivers/mfd/
H A Dsm501.c392 int divider; member in struct:sm501_clock
411 int divider; local
416 try divider 5 for panel only.*/
418 for (divider = 1; divider <= max_div; divider += 2) {
422 diff = DIV_ROUND_CLOSEST(mclk, divider << shift) - freq;
431 clock->divider = divider;
476 return clock->mclk / (clock->divider << cloc
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/linux-master/drivers/mmc/host/
H A Dmxcmmc.c788 unsigned int divider; local
793 for (divider = 1; divider <= 0xF; divider++) {
796 x = (clk_in / (divider + 1));
804 if (divider < 0x10)
813 mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE);
815 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
816 prescaler, divider, clk_in, clk_ios);
/linux-master/drivers/net/can/sja1000/
H A Dsja1000_platform.c183 u32 divider = priv->can.clock.freq * 2 / prop; local
185 if (divider > 1)
186 priv->cdr |= divider / 2 - 1;
/linux-master/drivers/net/ethernet/mediatek/
H A Dmtk_eth_soc.c819 unsigned int max_clk = 2500000, divider; local
859 divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63);
866 val = FIELD_PREP(PPSC_MDC_CFG, divider);
871 dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider);
/linux-master/drivers/net/ethernet/mellanox/mlx5/core/esw/
H A Dqos.c14 #define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \
15 min_t(u32, max_t(u32, DIV_ROUND_UP(rate, divider), MLX5_MIN_BW_SHARE), limit)
119 /* If vports min rate divider is 0 but their group has bw_share configured, then
127 static u32 esw_qos_calc_bw_share(u32 min_rate, u32 divider, u32 fw_max) argument
129 if (divider)
130 return MLX5_RATE_TO_BW_SHARE(min_rate, divider, fw_max);
140 u32 divider = esw_qos_calculate_min_rate_divider(esw, group, false); local
149 bw_share = esw_qos_calc_bw_share(evport->qos.min_rate, divider, fw_max_bw_share);
164 static int esw_qos_normalize_groups_min_rate(struct mlx5_eswitch *esw, u32 divider, argument
173 bw_share = esw_qos_calc_bw_share(group->min_rate, divider, fw_max_bw_shar
255 u32 previous_min_rate, divider; local
424 u32 divider; local
494 u32 divider; local
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/linux-master/drivers/power/supply/
H A Dcpcap-battery.c239 * @divider: conversion divider
256 s16 offset, u32 divider)
260 if (!divider)
267 acc = div_s64(acc, divider);
254 cpcap_battery_cc_raw_div(struct cpcap_battery_ddata *ddata, s32 sample, s32 accumulator, s16 offset, u32 divider) argument
/linux-master/drivers/soc/qcom/
H A Dqcom-geni-se.c626 unsigned int divider; local
637 divider = DIV_ROUND_UP(tbl[i], req_freq);
638 new_delta = req_freq - tbl[i] / divider;
/linux-master/drivers/soundwire/
H A Dcadence_master.c1330 int divider; local
1332 /* Set clock divider */
1333 divider = (prop->mclk_freq / prop->max_clk_freq) - 1;
1336 CDNS_MCP_CLK_MCLKD_MASK, divider);
1338 CDNS_MCP_CLK_MCLKD_MASK, divider);
1418 int divider; local
1425 divider = prop->mclk_freq * SDW_DOUBLE_RATE_FACTOR /
1427 divider--; /* divider is 1/(N+1) */
1434 cdns_updatel(cdns, mcp_clkctrl_off, CDNS_MCP_CLK_MCLKD_MASK, divider);
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/linux-master/drivers/spi/
H A Dspi-meson-spicc.c575 * The pow2 divider is tied to the controller HW state, and the
576 * divider is only valid when the controller is initialized.
585 struct clk_divider *divider = to_clk_divider(hw); local
586 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
597 struct clk_divider *divider = to_clk_divider(hw); local
598 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
609 struct clk_divider *divider = to_clk_divider(hw); local
610 struct meson_spicc_device *spicc = pow2_clk_to_spicc(divider);
H A Dspi-orion.c160 /* best integer divider: */
161 unsigned divider = DIV_ROUND_UP(tclk_hz, speed); local
164 if (divider < 16) {
165 /* This is the easy case, divider is less than 16 */
166 spr = divider;
172 * Find the highest bit set in divider. This and the
177 sppr = fls(divider) - 4;
180 * As SPR only has 4 bits, we have to round divider up
184 divider = (divider
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H A Dspi-xcomm.c79 unsigned int divider; local
81 divider = DIV_ROUND_UP(SPI_XCOMM_CLOCK, t->speed_hz);
82 if (divider >= 64)
84 else if (divider >= 16)
/linux-master/drivers/staging/media/ipu3/
H A Dipu3-css-params.c29 unsigned int divider)
31 int i = fls(divider) - fls(counter);
36 if (divider >> i < counter)
28 imgu_css_scaler_get_exp(unsigned int counter, unsigned int divider) argument

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