Searched refs:nand (Results 151 - 162 of 162) sorted by relevance

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/u-boot/arch/arm/mach-imx/
H A Dcmd_nandbcb.c2 * i.MX nand boot control block(bcb).
4 * Based on the common/imx-bbu-nand-fcb.c from barebox and imx kobs-ng
18 #include <nand.h>
33 #include <nand.h>
189 printf("failed to get nand_curr_device, run nand device\n");
523 /* switch nand BCH to FCB compatible settings */
626 /* switch nand BCH to FCB compatible settings */
984 * - nand timings
/u-boot/drivers/mtd/nand/raw/
H A Drockchip_nfc.c22 #include <linux/mtd/nand.h>
26 #include <nand.h>
933 ret = ofnode_read_u32(node, "nand-ecc-strength", &tmp);
936 ret = ofnode_read_u32(node, "nand-ecc-step-size", &tmp);
H A Dpxa3xx_nand.c3 * drivers/mtd/nand/raw/pxa3xx_nand.c
12 #include <nand.h>
298 * http://www.linux-mtd.infradead.org/nand-data/nanddata.html
385 /* convert nano-seconds to nand flash controller clock cycles */
390 .compatible = "marvell,armada370-nand-controller",
394 .compatible = "marvell,armada-8k-nand-controller",
398 .compatible = "marvell,mvebu-ac5-pxa3xx-nand",
1767 if (dev_read_bool(dev, "marvell,nand-enable-arbiter"))
1770 if (dev_read_bool(dev, "marvell,nand-keep-config"))
1779 pdata->ecc_strength = dev_read_u32_default(dev, "nand
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/u-boot/drivers/pinctrl/meson/
H A Dpinctrl-meson-gxl.c642 FUNCTION(nand),
H A Dpinctrl-meson-axg.c33 /* nand */
856 FUNCTION(nand),
H A Dpinctrl-meson-g12a.c33 /* nand */
1150 FUNCTION(nand),
/u-boot/cmd/mvebu/
H A Dbubt.c21 #include <nand.h>
71 { 0x5350491a, "nand" },
149 { 0x8B, "nand" },
702 {"nand", NULL, nand_burn_image, is_nand_active},
1177 #define DEFAULT_BUBT_DST "nand"
1259 "\t-destination Flash to burn to [spi, nand, mmc, sata]. Default = " DEFAULT_BUBT_DST "\n"
1263 "\tbubt flash-image-new.bin nand - Burn flash-image-new.bin from tftp to NAND flash\n"
/u-boot/drivers/block/
H A Drkmtd.c18 #include <nand.h>
/u-boot/cmd/
H A Dmtdparts.c40 * <dev-id> := 'nand'|'nor'|'onenand'|'spi-nand'<dev-num>
68 * mtdids=nor0=edb7312-nor,nand0=edb7312-nand
69 * mtdparts=[mtdparts=]edb7312-nor:256k(ARMboot)ro,-(root);edb7312-nand:-(home)
87 #include <nand.h>
322 * is located. Alignment with the granularity of nand erasesize is verified.
1033 * Parse device id string <dev-id> := 'nand'|'nor'|'onenand'|'spi-nand'<dev-num>,
1048 if (strncmp(p, "nand", 4) == 0) {
1057 } else if (strncmp(p, "spi-nand",
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/u-boot/
H A DMakefile1566 u-boot-nand.imx: u-boot.imx FORCE
1569 u-boot-with-spl.imx u-boot-with-nand-spl.imx: SPL $(if $(CONFIG_OF_SEPARATE),u-boot.img,u-boot.uim) FORCE
1623 u-boot-with-nand-spl.sfp: u-boot-spl-padx4.sfp u-boot.img FORCE
/u-boot/fs/jffs2/
H A Djffs2_1pass.c153 #include <nand.h>
216 printf("read_nand_cached: error reading nand off %#x size %d bytes\n",
323 printf("read_onenand_cached: error reading nand off %#x size %d bytes\n",
/u-boot/drivers/mtd/nand/raw/brcmnand/
H A Dbrcmnand.c18 #include <nand.h>
673 else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp"))
675 else if (dev_read_bool(ctrl->dev, "brcm,nand-has-wp"))
1244 dev_err(host->pdev, "nand #WP expected %s\n",
2288 "brcm,nand-oob-sector-size",
2292 "brcm,nand-oob-sector-size",
2703 ctrl->clk = devm_clk_get(dev, "nand");
2719 * Most chips have this cache at a fixed offset within 'nand' block.
2723 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache");
2735 if (!dev_read_resource_byname(pdev, "nand
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