#
d678a59d |
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18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
c45973bc |
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01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
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0cf207ec |
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27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
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41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
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38c1c6f8 |
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02-Oct-2020 |
Neil Armstrong <neil.armstrong@linaro.org> |
pinctrl: meson-axg: add missing GPIOA_18 Add the missing GPIOA_18 from the missing EE gpio list. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |
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2c4e3cf2 |
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08-Apr-2019 |
Guillaume La Roque <glaroque@baylibre.com> |
pinctrl: meson: axg: Fix PIN and BANK offsets Periphs bank offset must be applied on all pins and PMX bank to prevent issue in meson_pinconf_set call. Without offset on pins when a call to pinconf is done meson_gpio_calc_reg_and_bit return wrong offset. To avoid breaking pmx function offset is needed in pmx bank structure too. Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |
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139ebe9e |
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06-Dec-2018 |
Carlo Caione <ccaione@baylibre.com> |
pinctrl: meson: axg: Fix GPIO pin offsets The pin number (first and last) in the bank definition is missing the pin base offset shifting. This is causing a miscalculation when retrieving the register and pin offsets in the GPIO driver causing the 'gpio' command to drive the wrong pins / GPIOs in the second GPIO chip (the AO bank is driven correctly because the shifting is already 0). Signed-off-by: Carlo Caione <ccaione@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |
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8587839f |
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05-Oct-2018 |
Jerome Brunet <jbrunet@baylibre.com> |
pinctrl: meson: add axg support This adds support for the Amlogic AXG SoC pinctrl and GPIO controller using a specific set of pinctrl functions which differs from the GX SoCs. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |
#
c45973bc |
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01-May-2024 |
Tom Rini <trini@konsulko.com> |
pinctrl: Remove <common.h> and add needed includes Remove <common.h> from this driver directory and when needed add missing include files directly. Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
0cf207ec |
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27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
41575d8e |
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03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
38c1c6f8 |
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02-Oct-2020 |
Neil Armstrong <neil.armstrong@linaro.org> |
pinctrl: meson-axg: add missing GPIOA_18 Add the missing GPIOA_18 from the missing EE gpio list. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |
#
2c4e3cf2 |
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08-Apr-2019 |
Guillaume La Roque <glaroque@baylibre.com> |
pinctrl: meson: axg: Fix PIN and BANK offsets Periphs bank offset must be applied on all pins and PMX bank to prevent issue in meson_pinconf_set call. Without offset on pins when a call to pinconf is done meson_gpio_calc_reg_and_bit return wrong offset. To avoid breaking pmx function offset is needed in pmx bank structure too. Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |
#
139ebe9e |
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06-Dec-2018 |
Carlo Caione <ccaione@baylibre.com> |
pinctrl: meson: axg: Fix GPIO pin offsets The pin number (first and last) in the bank definition is missing the pin base offset shifting. This is causing a miscalculation when retrieving the register and pin offsets in the GPIO driver causing the 'gpio' command to drive the wrong pins / GPIOs in the second GPIO chip (the AO bank is driven correctly because the shifting is already 0). Signed-off-by: Carlo Caione <ccaione@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |
#
8587839f |
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05-Oct-2018 |
Jerome Brunet <jbrunet@baylibre.com> |
pinctrl: meson: add axg support This adds support for the Amlogic AXG SoC pinctrl and GPIO controller using a specific set of pinctrl functions which differs from the GX SoCs. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |
#
0cf207ec |
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27-Sep-2021 |
Wolfgang Denk <wd@denx.de> |
WS cleanup: remove SPACE(s) followed by TAB Signed-off-by: Wolfgang Denk <wd@denx.de> |
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
38c1c6f8 |
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02-Oct-2020 |
Neil Armstrong <narmstrong@baylibre.com> |
pinctrl: meson-axg: add missing GPIOA_18 Add the missing GPIOA_18 from the missing EE gpio list. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |
#
2c4e3cf2 |
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08-Apr-2019 |
Guillaume La Roque <glaroque@baylibre.com> |
pinctrl: meson: axg: Fix PIN and BANK offsets Periphs bank offset must be applied on all pins and PMX bank to prevent issue in meson_pinconf_set call. Without offset on pins when a call to pinconf is done meson_gpio_calc_reg_and_bit return wrong offset. To avoid breaking pmx function offset is needed in pmx bank structure too. Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |
#
139ebe9e |
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06-Dec-2018 |
Carlo Caione <ccaione@baylibre.com> |
pinctrl: meson: axg: Fix GPIO pin offsets The pin number (first and last) in the bank definition is missing the pin base offset shifting. This is causing a miscalculation when retrieving the register and pin offsets in the GPIO driver causing the 'gpio' command to drive the wrong pins / GPIOs in the second GPIO chip (the AO bank is driven correctly because the shifting is already 0). Signed-off-by: Carlo Caione <ccaione@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |
#
8587839f |
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05-Oct-2018 |
Jerome Brunet <jbrunet@baylibre.com> |
pinctrl: meson: add axg support This adds support for the Amlogic AXG SoC pinctrl and GPIO controller using a specific set of pinctrl functions which differs from the GX SoCs. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |
#
41575d8e |
|
03-Dec-2020 |
Simon Glass <sjg@chromium.org> |
dm: treewide: Rename auto_alloc_size members to be shorter This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
38c1c6f8 |
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02-Oct-2020 |
Neil Armstrong <narmstrong@baylibre.com> |
pinctrl: meson-axg: add missing GPIOA_18 Add the missing GPIOA_18 from the missing EE gpio list. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |
#
2c4e3cf2 |
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08-Apr-2019 |
Guillaume La Roque <glaroque@baylibre.com> |
pinctrl: meson: axg: Fix PIN and BANK offsets Periphs bank offset must be applied on all pins and PMX bank to prevent issue in meson_pinconf_set call. Without offset on pins when a call to pinconf is done meson_gpio_calc_reg_and_bit return wrong offset. To avoid breaking pmx function offset is needed in pmx bank structure too. Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |
#
139ebe9e |
|
06-Dec-2018 |
Carlo Caione <ccaione@baylibre.com> |
pinctrl: meson: axg: Fix GPIO pin offsets The pin number (first and last) in the bank definition is missing the pin base offset shifting. This is causing a miscalculation when retrieving the register and pin offsets in the GPIO driver causing the 'gpio' command to drive the wrong pins / GPIOs in the second GPIO chip (the AO bank is driven correctly because the shifting is already 0). Signed-off-by: Carlo Caione <ccaione@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |
#
8587839f |
|
05-Oct-2018 |
Jerome Brunet <jbrunet@baylibre.com> |
pinctrl: meson: add axg support This adds support for the Amlogic AXG SoC pinctrl and GPIO controller using a specific set of pinctrl functions which differs from the GX SoCs. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |
#
38c1c6f8 |
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02-Oct-2020 |
Neil Armstrong <narmstrong@baylibre.com> |
pinctrl: meson-axg: add missing GPIOA_18 Add the missing GPIOA_18 from the missing EE gpio list. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |
#
2c4e3cf2 |
|
08-Apr-2019 |
Guillaume La Roque <glaroque@baylibre.com> |
pinctrl: meson: axg: Fix PIN and BANK offsets Periphs bank offset must be applied on all pins and PMX bank to prevent issue in meson_pinconf_set call. Without offset on pins when a call to pinconf is done meson_gpio_calc_reg_and_bit return wrong offset. To avoid breaking pmx function offset is needed in pmx bank structure too. Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |
#
139ebe9e |
|
06-Dec-2018 |
Carlo Caione <ccaione@baylibre.com> |
pinctrl: meson: axg: Fix GPIO pin offsets The pin number (first and last) in the bank definition is missing the pin base offset shifting. This is causing a miscalculation when retrieving the register and pin offsets in the GPIO driver causing the 'gpio' command to drive the wrong pins / GPIOs in the second GPIO chip (the AO bank is driven correctly because the shifting is already 0). Signed-off-by: Carlo Caione <ccaione@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |
#
8587839f |
|
05-Oct-2018 |
Jerome Brunet <jbrunet@baylibre.com> |
pinctrl: meson: add axg support This adds support for the Amlogic AXG SoC pinctrl and GPIO controller using a specific set of pinctrl functions which differs from the GX SoCs. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |
#
2c4e3cf2 |
|
08-Apr-2019 |
Guillaume La Roque <glaroque@baylibre.com> |
pinctrl: meson: axg: Fix PIN and BANK offsets Periphs bank offset must be applied on all pins and PMX bank to prevent issue in meson_pinconf_set call. Without offset on pins when a call to pinconf is done meson_gpio_calc_reg_and_bit return wrong offset. To avoid breaking pmx function offset is needed in pmx bank structure too. Signed-off-by: Guillaume La Roque <glaroque@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |
#
139ebe9e |
|
06-Dec-2018 |
Carlo Caione <ccaione@baylibre.com> |
pinctrl: meson: axg: Fix GPIO pin offsets The pin number (first and last) in the bank definition is missing the pin base offset shifting. This is causing a miscalculation when retrieving the register and pin offsets in the GPIO driver causing the 'gpio' command to drive the wrong pins / GPIOs in the second GPIO chip (the AO bank is driven correctly because the shifting is already 0). Signed-off-by: Carlo Caione <ccaione@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |
#
8587839f |
|
05-Oct-2018 |
Jerome Brunet <jbrunet@baylibre.com> |
pinctrl: meson: add axg support This adds support for the Amlogic AXG SoC pinctrl and GPIO controller using a specific set of pinctrl functions which differs from the GX SoCs. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> |