1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright �� 2010-2015 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15#include <common.h> 16#include <asm/io.h> 17#include <memalign.h> 18#include <nand.h> 19#include <clk.h> 20#include <dm/device_compat.h> 21#include <dm/devres.h> 22#include <linux/bitops.h> 23#include <linux/bug.h> 24#include <linux/err.h> 25#include <linux/ioport.h> 26#include <linux/completion.h> 27#include <linux/errno.h> 28#include <linux/log2.h> 29#include <linux/mtd/rawnand.h> 30#include <asm/processor.h> 31#include <dm.h> 32 33#include "brcmnand.h" 34#include "brcmnand_compat.h" 35 36/* 37 * This flag controls if WP stays on between erase/write commands to mitigate 38 * flash corruption due to power glitches. Values: 39 * 0: NAND_WP is not used or not available 40 * 1: NAND_WP is set by default, cleared for erase/write operations 41 * 2: NAND_WP is always cleared 42 */ 43static int wp_on = 1; 44module_param(wp_on, int, 0444); 45 46/*********************************************************************** 47 * Definitions 48 ***********************************************************************/ 49 50#define DRV_NAME "brcmnand" 51 52#define CMD_NULL 0x00 53#define CMD_PAGE_READ 0x01 54#define CMD_SPARE_AREA_READ 0x02 55#define CMD_STATUS_READ 0x03 56#define CMD_PROGRAM_PAGE 0x04 57#define CMD_PROGRAM_SPARE_AREA 0x05 58#define CMD_COPY_BACK 0x06 59#define CMD_DEVICE_ID_READ 0x07 60#define CMD_BLOCK_ERASE 0x08 61#define CMD_FLASH_RESET 0x09 62#define CMD_BLOCKS_LOCK 0x0a 63#define CMD_BLOCKS_LOCK_DOWN 0x0b 64#define CMD_BLOCKS_UNLOCK 0x0c 65#define CMD_READ_BLOCKS_LOCK_STATUS 0x0d 66#define CMD_PARAMETER_READ 0x0e 67#define CMD_PARAMETER_CHANGE_COL 0x0f 68#define CMD_LOW_LEVEL_OP 0x10 69 70struct brcm_nand_dma_desc { 71 u32 next_desc; 72 u32 next_desc_ext; 73 u32 cmd_irq; 74 u32 dram_addr; 75 u32 dram_addr_ext; 76 u32 tfr_len; 77 u32 total_len; 78 u32 flash_addr; 79 u32 flash_addr_ext; 80 u32 cs; 81 u32 pad2[5]; 82 u32 status_valid; 83} __packed; 84 85/* Bitfields for brcm_nand_dma_desc::status_valid */ 86#define FLASH_DMA_ECC_ERROR (1 << 8) 87#define FLASH_DMA_CORR_ERROR (1 << 9) 88 89/* Bitfields for DMA_MODE */ 90#define FLASH_DMA_MODE_STOP_ON_ERROR BIT(1) /* stop in Uncorr ECC error */ 91#define FLASH_DMA_MODE_MODE BIT(0) /* link list */ 92#define FLASH_DMA_MODE_MASK (FLASH_DMA_MODE_STOP_ON_ERROR | \ 93 FLASH_DMA_MODE_MODE) 94 95/* 512B flash cache in the NAND controller HW */ 96#define FC_SHIFT 9U 97#define FC_BYTES 512U 98#define FC_WORDS (FC_BYTES >> 2) 99 100#define BRCMNAND_MIN_PAGESIZE 512 101#define BRCMNAND_MIN_BLOCKSIZE (8 * 1024) 102#define BRCMNAND_MIN_DEVSIZE (4ULL * 1024 * 1024) 103 104#define NAND_CTRL_RDY (INTFC_CTLR_READY | INTFC_FLASH_READY) 105#define NAND_POLL_STATUS_TIMEOUT_MS 100 106 107/* flash_dma registers */ 108enum flash_dma_reg { 109 FLASH_DMA_REVISION = 0, 110 FLASH_DMA_FIRST_DESC, 111 FLASH_DMA_FIRST_DESC_EXT, 112 FLASH_DMA_CTRL, 113 FLASH_DMA_MODE, 114 FLASH_DMA_STATUS, 115 FLASH_DMA_INTERRUPT_DESC, 116 FLASH_DMA_INTERRUPT_DESC_EXT, 117 FLASH_DMA_ERROR_STATUS, 118 FLASH_DMA_CURRENT_DESC, 119 FLASH_DMA_CURRENT_DESC_EXT, 120}; 121 122#ifndef __UBOOT__ 123/* flash_dma registers v0*/ 124static const u16 flash_dma_regs_v0[] = { 125 [FLASH_DMA_REVISION] = 0x00, 126 [FLASH_DMA_FIRST_DESC] = 0x04, 127 [FLASH_DMA_CTRL] = 0x08, 128 [FLASH_DMA_MODE] = 0x0c, 129 [FLASH_DMA_STATUS] = 0x10, 130 [FLASH_DMA_INTERRUPT_DESC] = 0x14, 131 [FLASH_DMA_ERROR_STATUS] = 0x18, 132 [FLASH_DMA_CURRENT_DESC] = 0x1c, 133}; 134 135/* flash_dma registers v1*/ 136static const u16 flash_dma_regs_v1[] = { 137 [FLASH_DMA_REVISION] = 0x00, 138 [FLASH_DMA_FIRST_DESC] = 0x04, 139 [FLASH_DMA_FIRST_DESC_EXT] = 0x08, 140 [FLASH_DMA_CTRL] = 0x0c, 141 [FLASH_DMA_MODE] = 0x10, 142 [FLASH_DMA_STATUS] = 0x14, 143 [FLASH_DMA_INTERRUPT_DESC] = 0x18, 144 [FLASH_DMA_INTERRUPT_DESC_EXT] = 0x1c, 145 [FLASH_DMA_ERROR_STATUS] = 0x20, 146 [FLASH_DMA_CURRENT_DESC] = 0x24, 147 [FLASH_DMA_CURRENT_DESC_EXT] = 0x28, 148}; 149 150/* flash_dma registers v4 */ 151static const u16 flash_dma_regs_v4[] = { 152 [FLASH_DMA_REVISION] = 0x00, 153 [FLASH_DMA_FIRST_DESC] = 0x08, 154 [FLASH_DMA_FIRST_DESC_EXT] = 0x0c, 155 [FLASH_DMA_CTRL] = 0x10, 156 [FLASH_DMA_MODE] = 0x14, 157 [FLASH_DMA_STATUS] = 0x18, 158 [FLASH_DMA_INTERRUPT_DESC] = 0x20, 159 [FLASH_DMA_INTERRUPT_DESC_EXT] = 0x24, 160 [FLASH_DMA_ERROR_STATUS] = 0x28, 161 [FLASH_DMA_CURRENT_DESC] = 0x30, 162 [FLASH_DMA_CURRENT_DESC_EXT] = 0x34, 163}; 164#endif /* __UBOOT__ */ 165 166/* Controller feature flags */ 167enum { 168 BRCMNAND_HAS_1K_SECTORS = BIT(0), 169 BRCMNAND_HAS_PREFETCH = BIT(1), 170 BRCMNAND_HAS_CACHE_MODE = BIT(2), 171 BRCMNAND_HAS_WP = BIT(3), 172}; 173 174struct brcmnand_controller { 175#ifndef __UBOOT__ 176 struct device *dev; 177#else 178 struct udevice *dev; 179#endif /* __UBOOT__ */ 180 struct nand_hw_control controller; 181 void __iomem *nand_base; 182 void __iomem *nand_fc; /* flash cache */ 183 void __iomem *flash_dma_base; 184 unsigned int irq; 185 unsigned int dma_irq; 186 int nand_version; 187 int parameter_page_big_endian; 188 189 /* Some SoCs provide custom interrupt status register(s) */ 190 struct brcmnand_soc *soc; 191 192 /* Some SoCs have a gateable clock for the controller */ 193 struct clk *clk; 194 195 int cmd_pending; 196 bool dma_pending; 197 struct completion done; 198 struct completion dma_done; 199 200 /* List of NAND hosts (one for each chip-select) */ 201 struct list_head host_list; 202 203 /* flash_dma reg */ 204 const u16 *flash_dma_offsets; 205 struct brcm_nand_dma_desc *dma_desc; 206 dma_addr_t dma_pa; 207 208 /* in-memory cache of the FLASH_CACHE, used only for some commands */ 209 u8 flash_cache[FC_BYTES]; 210 211 /* Controller revision details */ 212 const u16 *reg_offsets; 213 unsigned int reg_spacing; /* between CS1, CS2, ... regs */ 214 const u8 *cs_offsets; /* within each chip-select */ 215 const u8 *cs0_offsets; /* within CS0, if different */ 216 unsigned int max_block_size; 217 const unsigned int *block_sizes; 218 unsigned int max_page_size; 219 const unsigned int *page_sizes; 220 unsigned int page_size_shift; 221 unsigned int max_oob; 222 u32 features; 223 224 /* for low-power standby/resume only */ 225 u32 nand_cs_nand_select; 226 u32 nand_cs_nand_xor; 227 u32 corr_stat_threshold; 228 u32 flash_dma_mode; 229}; 230 231struct brcmnand_cfg { 232 u64 device_size; 233 unsigned int block_size; 234 unsigned int page_size; 235 unsigned int spare_area_size; 236 unsigned int device_width; 237 unsigned int col_adr_bytes; 238 unsigned int blk_adr_bytes; 239 unsigned int ful_adr_bytes; 240 unsigned int sector_size_1k; 241 unsigned int ecc_level; 242 /* use for low-power standby/resume only */ 243 u32 acc_control; 244 u32 config; 245 u32 config_ext; 246 u32 timing_1; 247 u32 timing_2; 248}; 249 250struct brcmnand_host { 251 struct list_head node; 252 253 struct nand_chip chip; 254#ifndef __UBOOT__ 255 struct platform_device *pdev; 256#else 257 struct udevice *pdev; 258#endif /* __UBOOT__ */ 259 int cs; 260 261 unsigned int last_cmd; 262 unsigned int last_byte; 263 u64 last_addr; 264 struct brcmnand_cfg hwcfg; 265 struct brcmnand_controller *ctrl; 266}; 267 268enum brcmnand_reg { 269 BRCMNAND_CMD_START = 0, 270 BRCMNAND_CMD_EXT_ADDRESS, 271 BRCMNAND_CMD_ADDRESS, 272 BRCMNAND_INTFC_STATUS, 273 BRCMNAND_CS_SELECT, 274 BRCMNAND_CS_XOR, 275 BRCMNAND_LL_OP, 276 BRCMNAND_CS0_BASE, 277 BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */ 278 BRCMNAND_CORR_THRESHOLD, 279 BRCMNAND_CORR_THRESHOLD_EXT, 280 BRCMNAND_UNCORR_COUNT, 281 BRCMNAND_CORR_COUNT, 282 BRCMNAND_CORR_EXT_ADDR, 283 BRCMNAND_CORR_ADDR, 284 BRCMNAND_UNCORR_EXT_ADDR, 285 BRCMNAND_UNCORR_ADDR, 286 BRCMNAND_SEMAPHORE, 287 BRCMNAND_ID, 288 BRCMNAND_ID_EXT, 289 BRCMNAND_LL_RDATA, 290 BRCMNAND_OOB_READ_BASE, 291 BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */ 292 BRCMNAND_OOB_WRITE_BASE, 293 BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */ 294 BRCMNAND_FC_BASE, 295}; 296 297/* BRCMNAND v2.1-v2.2 */ 298static const u16 brcmnand_regs_v21[] = { 299 [BRCMNAND_CMD_START] = 0x04, 300 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 301 [BRCMNAND_CMD_ADDRESS] = 0x0c, 302 [BRCMNAND_INTFC_STATUS] = 0x5c, 303 [BRCMNAND_CS_SELECT] = 0x14, 304 [BRCMNAND_CS_XOR] = 0x18, 305 [BRCMNAND_LL_OP] = 0, 306 [BRCMNAND_CS0_BASE] = 0x40, 307 [BRCMNAND_CS1_BASE] = 0, 308 [BRCMNAND_CORR_THRESHOLD] = 0, 309 [BRCMNAND_CORR_THRESHOLD_EXT] = 0, 310 [BRCMNAND_UNCORR_COUNT] = 0, 311 [BRCMNAND_CORR_COUNT] = 0, 312 [BRCMNAND_CORR_EXT_ADDR] = 0x60, 313 [BRCMNAND_CORR_ADDR] = 0x64, 314 [BRCMNAND_UNCORR_EXT_ADDR] = 0x68, 315 [BRCMNAND_UNCORR_ADDR] = 0x6c, 316 [BRCMNAND_SEMAPHORE] = 0x50, 317 [BRCMNAND_ID] = 0x54, 318 [BRCMNAND_ID_EXT] = 0, 319 [BRCMNAND_LL_RDATA] = 0, 320 [BRCMNAND_OOB_READ_BASE] = 0x20, 321 [BRCMNAND_OOB_READ_10_BASE] = 0, 322 [BRCMNAND_OOB_WRITE_BASE] = 0x30, 323 [BRCMNAND_OOB_WRITE_10_BASE] = 0, 324 [BRCMNAND_FC_BASE] = 0x200, 325}; 326 327/* BRCMNAND v3.3-v4.0 */ 328static const u16 brcmnand_regs_v33[] = { 329 [BRCMNAND_CMD_START] = 0x04, 330 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 331 [BRCMNAND_CMD_ADDRESS] = 0x0c, 332 [BRCMNAND_INTFC_STATUS] = 0x6c, 333 [BRCMNAND_CS_SELECT] = 0x14, 334 [BRCMNAND_CS_XOR] = 0x18, 335 [BRCMNAND_LL_OP] = 0x178, 336 [BRCMNAND_CS0_BASE] = 0x40, 337 [BRCMNAND_CS1_BASE] = 0xd0, 338 [BRCMNAND_CORR_THRESHOLD] = 0x84, 339 [BRCMNAND_CORR_THRESHOLD_EXT] = 0, 340 [BRCMNAND_UNCORR_COUNT] = 0, 341 [BRCMNAND_CORR_COUNT] = 0, 342 [BRCMNAND_CORR_EXT_ADDR] = 0x70, 343 [BRCMNAND_CORR_ADDR] = 0x74, 344 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78, 345 [BRCMNAND_UNCORR_ADDR] = 0x7c, 346 [BRCMNAND_SEMAPHORE] = 0x58, 347 [BRCMNAND_ID] = 0x60, 348 [BRCMNAND_ID_EXT] = 0x64, 349 [BRCMNAND_LL_RDATA] = 0x17c, 350 [BRCMNAND_OOB_READ_BASE] = 0x20, 351 [BRCMNAND_OOB_READ_10_BASE] = 0x130, 352 [BRCMNAND_OOB_WRITE_BASE] = 0x30, 353 [BRCMNAND_OOB_WRITE_10_BASE] = 0, 354 [BRCMNAND_FC_BASE] = 0x200, 355}; 356 357/* BRCMNAND v5.0 */ 358static const u16 brcmnand_regs_v50[] = { 359 [BRCMNAND_CMD_START] = 0x04, 360 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 361 [BRCMNAND_CMD_ADDRESS] = 0x0c, 362 [BRCMNAND_INTFC_STATUS] = 0x6c, 363 [BRCMNAND_CS_SELECT] = 0x14, 364 [BRCMNAND_CS_XOR] = 0x18, 365 [BRCMNAND_LL_OP] = 0x178, 366 [BRCMNAND_CS0_BASE] = 0x40, 367 [BRCMNAND_CS1_BASE] = 0xd0, 368 [BRCMNAND_CORR_THRESHOLD] = 0x84, 369 [BRCMNAND_CORR_THRESHOLD_EXT] = 0, 370 [BRCMNAND_UNCORR_COUNT] = 0, 371 [BRCMNAND_CORR_COUNT] = 0, 372 [BRCMNAND_CORR_EXT_ADDR] = 0x70, 373 [BRCMNAND_CORR_ADDR] = 0x74, 374 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78, 375 [BRCMNAND_UNCORR_ADDR] = 0x7c, 376 [BRCMNAND_SEMAPHORE] = 0x58, 377 [BRCMNAND_ID] = 0x60, 378 [BRCMNAND_ID_EXT] = 0x64, 379 [BRCMNAND_LL_RDATA] = 0x17c, 380 [BRCMNAND_OOB_READ_BASE] = 0x20, 381 [BRCMNAND_OOB_READ_10_BASE] = 0x130, 382 [BRCMNAND_OOB_WRITE_BASE] = 0x30, 383 [BRCMNAND_OOB_WRITE_10_BASE] = 0x140, 384 [BRCMNAND_FC_BASE] = 0x200, 385}; 386 387/* BRCMNAND v6.0 - v7.1 */ 388static const u16 brcmnand_regs_v60[] = { 389 [BRCMNAND_CMD_START] = 0x04, 390 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 391 [BRCMNAND_CMD_ADDRESS] = 0x0c, 392 [BRCMNAND_INTFC_STATUS] = 0x14, 393 [BRCMNAND_CS_SELECT] = 0x18, 394 [BRCMNAND_CS_XOR] = 0x1c, 395 [BRCMNAND_LL_OP] = 0x20, 396 [BRCMNAND_CS0_BASE] = 0x50, 397 [BRCMNAND_CS1_BASE] = 0, 398 [BRCMNAND_CORR_THRESHOLD] = 0xc0, 399 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xc4, 400 [BRCMNAND_UNCORR_COUNT] = 0xfc, 401 [BRCMNAND_CORR_COUNT] = 0x100, 402 [BRCMNAND_CORR_EXT_ADDR] = 0x10c, 403 [BRCMNAND_CORR_ADDR] = 0x110, 404 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114, 405 [BRCMNAND_UNCORR_ADDR] = 0x118, 406 [BRCMNAND_SEMAPHORE] = 0x150, 407 [BRCMNAND_ID] = 0x194, 408 [BRCMNAND_ID_EXT] = 0x198, 409 [BRCMNAND_LL_RDATA] = 0x19c, 410 [BRCMNAND_OOB_READ_BASE] = 0x200, 411 [BRCMNAND_OOB_READ_10_BASE] = 0, 412 [BRCMNAND_OOB_WRITE_BASE] = 0x280, 413 [BRCMNAND_OOB_WRITE_10_BASE] = 0, 414 [BRCMNAND_FC_BASE] = 0x400, 415}; 416 417/* BRCMNAND v7.1 */ 418static const u16 brcmnand_regs_v71[] = { 419 [BRCMNAND_CMD_START] = 0x04, 420 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 421 [BRCMNAND_CMD_ADDRESS] = 0x0c, 422 [BRCMNAND_INTFC_STATUS] = 0x14, 423 [BRCMNAND_CS_SELECT] = 0x18, 424 [BRCMNAND_CS_XOR] = 0x1c, 425 [BRCMNAND_LL_OP] = 0x20, 426 [BRCMNAND_CS0_BASE] = 0x50, 427 [BRCMNAND_CS1_BASE] = 0, 428 [BRCMNAND_CORR_THRESHOLD] = 0xdc, 429 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0, 430 [BRCMNAND_UNCORR_COUNT] = 0xfc, 431 [BRCMNAND_CORR_COUNT] = 0x100, 432 [BRCMNAND_CORR_EXT_ADDR] = 0x10c, 433 [BRCMNAND_CORR_ADDR] = 0x110, 434 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114, 435 [BRCMNAND_UNCORR_ADDR] = 0x118, 436 [BRCMNAND_SEMAPHORE] = 0x150, 437 [BRCMNAND_ID] = 0x194, 438 [BRCMNAND_ID_EXT] = 0x198, 439 [BRCMNAND_LL_RDATA] = 0x19c, 440 [BRCMNAND_OOB_READ_BASE] = 0x200, 441 [BRCMNAND_OOB_READ_10_BASE] = 0, 442 [BRCMNAND_OOB_WRITE_BASE] = 0x280, 443 [BRCMNAND_OOB_WRITE_10_BASE] = 0, 444 [BRCMNAND_FC_BASE] = 0x400, 445}; 446 447/* BRCMNAND v7.2 */ 448static const u16 brcmnand_regs_v72[] = { 449 [BRCMNAND_CMD_START] = 0x04, 450 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08, 451 [BRCMNAND_CMD_ADDRESS] = 0x0c, 452 [BRCMNAND_INTFC_STATUS] = 0x14, 453 [BRCMNAND_CS_SELECT] = 0x18, 454 [BRCMNAND_CS_XOR] = 0x1c, 455 [BRCMNAND_LL_OP] = 0x20, 456 [BRCMNAND_CS0_BASE] = 0x50, 457 [BRCMNAND_CS1_BASE] = 0, 458 [BRCMNAND_CORR_THRESHOLD] = 0xdc, 459 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0, 460 [BRCMNAND_UNCORR_COUNT] = 0xfc, 461 [BRCMNAND_CORR_COUNT] = 0x100, 462 [BRCMNAND_CORR_EXT_ADDR] = 0x10c, 463 [BRCMNAND_CORR_ADDR] = 0x110, 464 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114, 465 [BRCMNAND_UNCORR_ADDR] = 0x118, 466 [BRCMNAND_SEMAPHORE] = 0x150, 467 [BRCMNAND_ID] = 0x194, 468 [BRCMNAND_ID_EXT] = 0x198, 469 [BRCMNAND_LL_RDATA] = 0x19c, 470 [BRCMNAND_OOB_READ_BASE] = 0x200, 471 [BRCMNAND_OOB_READ_10_BASE] = 0, 472 [BRCMNAND_OOB_WRITE_BASE] = 0x400, 473 [BRCMNAND_OOB_WRITE_10_BASE] = 0, 474 [BRCMNAND_FC_BASE] = 0x600, 475}; 476 477enum brcmnand_cs_reg { 478 BRCMNAND_CS_CFG_EXT = 0, 479 BRCMNAND_CS_CFG, 480 BRCMNAND_CS_ACC_CONTROL, 481 BRCMNAND_CS_TIMING1, 482 BRCMNAND_CS_TIMING2, 483}; 484 485/* Per chip-select offsets for v7.1 */ 486static const u8 brcmnand_cs_offsets_v71[] = { 487 [BRCMNAND_CS_ACC_CONTROL] = 0x00, 488 [BRCMNAND_CS_CFG_EXT] = 0x04, 489 [BRCMNAND_CS_CFG] = 0x08, 490 [BRCMNAND_CS_TIMING1] = 0x0c, 491 [BRCMNAND_CS_TIMING2] = 0x10, 492}; 493 494/* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */ 495static const u8 brcmnand_cs_offsets[] = { 496 [BRCMNAND_CS_ACC_CONTROL] = 0x00, 497 [BRCMNAND_CS_CFG_EXT] = 0x04, 498 [BRCMNAND_CS_CFG] = 0x04, 499 [BRCMNAND_CS_TIMING1] = 0x08, 500 [BRCMNAND_CS_TIMING2] = 0x0c, 501}; 502 503/* Per chip-select offset for <= v5.0 on CS0 only */ 504static const u8 brcmnand_cs_offsets_cs0[] = { 505 [BRCMNAND_CS_ACC_CONTROL] = 0x00, 506 [BRCMNAND_CS_CFG_EXT] = 0x08, 507 [BRCMNAND_CS_CFG] = 0x08, 508 [BRCMNAND_CS_TIMING1] = 0x10, 509 [BRCMNAND_CS_TIMING2] = 0x14, 510}; 511 512/* 513 * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had 514 * one config register, but once the bitfields overflowed, newer controllers 515 * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around. 516 */ 517enum { 518 CFG_BLK_ADR_BYTES_SHIFT = 8, 519 CFG_COL_ADR_BYTES_SHIFT = 12, 520 CFG_FUL_ADR_BYTES_SHIFT = 16, 521 CFG_BUS_WIDTH_SHIFT = 23, 522 CFG_BUS_WIDTH = BIT(CFG_BUS_WIDTH_SHIFT), 523 CFG_DEVICE_SIZE_SHIFT = 24, 524 525 /* Only for v2.1 */ 526 CFG_PAGE_SIZE_SHIFT_v2_1 = 30, 527 528 /* Only for pre-v7.1 (with no CFG_EXT register) */ 529 CFG_PAGE_SIZE_SHIFT = 20, 530 CFG_BLK_SIZE_SHIFT = 28, 531 532 /* Only for v7.1+ (with CFG_EXT register) */ 533 CFG_EXT_PAGE_SIZE_SHIFT = 0, 534 CFG_EXT_BLK_SIZE_SHIFT = 4, 535}; 536 537/* BRCMNAND_INTFC_STATUS */ 538enum { 539 INTFC_FLASH_STATUS = GENMASK(7, 0), 540 541 INTFC_ERASED = BIT(27), 542 INTFC_OOB_VALID = BIT(28), 543 INTFC_CACHE_VALID = BIT(29), 544 INTFC_FLASH_READY = BIT(30), 545 INTFC_CTLR_READY = BIT(31), 546}; 547 548static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs) 549{ 550 return brcmnand_readl(ctrl->nand_base + offs); 551} 552 553static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs, 554 u32 val) 555{ 556 brcmnand_writel(val, ctrl->nand_base + offs); 557} 558 559static int brcmnand_revision_init(struct brcmnand_controller *ctrl) 560{ 561 static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 }; 562 static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 }; 563 static const unsigned int block_sizes_v2_2[] = { 16, 128, 8, 512, 256, 0 }; 564 static const unsigned int block_sizes_v2_1[] = { 16, 128, 8, 512, 0 }; 565 static const unsigned int page_sizes_v3_4[] = { 512, 2048, 4096, 8192, 0 }; 566 static const unsigned int page_sizes_v2_2[] = { 512, 2048, 4096, 0 }; 567 static const unsigned int page_sizes_v2_1[] = { 512, 2048, 0 }; 568 569 ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff; 570 571 /* Only support v2.1+ */ 572 if (ctrl->nand_version < 0x0201) { 573 dev_err(ctrl->dev, "version %#x not supported\n", 574 ctrl->nand_version); 575 return -ENODEV; 576 } 577 578 /* Register offsets */ 579 if (ctrl->nand_version >= 0x0702) 580 ctrl->reg_offsets = brcmnand_regs_v72; 581 else if (ctrl->nand_version == 0x0701) 582 ctrl->reg_offsets = brcmnand_regs_v71; 583 else if (ctrl->nand_version >= 0x0600) 584 ctrl->reg_offsets = brcmnand_regs_v60; 585 else if (ctrl->nand_version >= 0x0500) 586 ctrl->reg_offsets = brcmnand_regs_v50; 587 else if (ctrl->nand_version >= 0x0303) 588 ctrl->reg_offsets = brcmnand_regs_v33; 589 else if (ctrl->nand_version >= 0x0201) 590 ctrl->reg_offsets = brcmnand_regs_v21; 591 592 /* Chip-select stride */ 593 if (ctrl->nand_version >= 0x0701) 594 ctrl->reg_spacing = 0x14; 595 else 596 ctrl->reg_spacing = 0x10; 597 598 /* Per chip-select registers */ 599 if (ctrl->nand_version >= 0x0701) { 600 ctrl->cs_offsets = brcmnand_cs_offsets_v71; 601 } else { 602 ctrl->cs_offsets = brcmnand_cs_offsets; 603 604 /* v3.3-5.0 have a different CS0 offset layout */ 605 if (ctrl->nand_version >= 0x0303 && 606 ctrl->nand_version <= 0x0500) 607 ctrl->cs0_offsets = brcmnand_cs_offsets_cs0; 608 } 609 610 /* Page / block sizes */ 611 if (ctrl->nand_version >= 0x0701) { 612 /* >= v7.1 use nice power-of-2 values! */ 613 ctrl->max_page_size = 16 * 1024; 614 ctrl->max_block_size = 2 * 1024 * 1024; 615 } else { 616 if (ctrl->nand_version >= 0x0304) 617 ctrl->page_sizes = page_sizes_v3_4; 618 else if (ctrl->nand_version >= 0x0202) 619 ctrl->page_sizes = page_sizes_v2_2; 620 else 621 ctrl->page_sizes = page_sizes_v2_1; 622 623 if (ctrl->nand_version >= 0x0202) 624 ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT; 625 else 626 ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT_v2_1; 627 628 if (ctrl->nand_version >= 0x0600) 629 ctrl->block_sizes = block_sizes_v6; 630 else if (ctrl->nand_version >= 0x0400) 631 ctrl->block_sizes = block_sizes_v4; 632 else if (ctrl->nand_version >= 0x0202) 633 ctrl->block_sizes = block_sizes_v2_2; 634 else 635 ctrl->block_sizes = block_sizes_v2_1; 636 637 if (ctrl->nand_version < 0x0400) { 638 if (ctrl->nand_version < 0x0202) 639 ctrl->max_page_size = 2048; 640 else 641 ctrl->max_page_size = 4096; 642 ctrl->max_block_size = 512 * 1024; 643 } 644 } 645 646 /* Maximum spare area sector size (per 512B) */ 647 if (ctrl->nand_version == 0x0702) 648 ctrl->max_oob = 128; 649 else if (ctrl->nand_version >= 0x0600) 650 ctrl->max_oob = 64; 651 else if (ctrl->nand_version >= 0x0500) 652 ctrl->max_oob = 32; 653 else 654 ctrl->max_oob = 16; 655 656 /* v6.0 and newer (except v6.1) have prefetch support */ 657 if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601) 658 ctrl->features |= BRCMNAND_HAS_PREFETCH; 659 660 /* 661 * v6.x has cache mode, but it's implemented differently. Ignore it for 662 * now. 663 */ 664 if (ctrl->nand_version >= 0x0700) 665 ctrl->features |= BRCMNAND_HAS_CACHE_MODE; 666 667 if (ctrl->nand_version >= 0x0500) 668 ctrl->features |= BRCMNAND_HAS_1K_SECTORS; 669 670 if (ctrl->nand_version >= 0x0700) 671 ctrl->features |= BRCMNAND_HAS_WP; 672#ifndef __UBOOT__ 673 else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp")) 674#else 675 else if (dev_read_bool(ctrl->dev, "brcm,nand-has-wp")) 676#endif /* __UBOOT__ */ 677 ctrl->features |= BRCMNAND_HAS_WP; 678 679 return 0; 680} 681 682#ifndef __UBOOT__ 683static void brcmnand_flash_dma_revision_init(struct brcmnand_controller *ctrl) 684{ 685 /* flash_dma register offsets */ 686 if (ctrl->nand_version >= 0x0703) 687 ctrl->flash_dma_offsets = flash_dma_regs_v4; 688 else if (ctrl->nand_version == 0x0602) 689 ctrl->flash_dma_offsets = flash_dma_regs_v0; 690 else 691 ctrl->flash_dma_offsets = flash_dma_regs_v1; 692} 693#endif /* __UBOOT__ */ 694 695static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl, 696 enum brcmnand_reg reg) 697{ 698 u16 offs = ctrl->reg_offsets[reg]; 699 700 if (offs) 701 return nand_readreg(ctrl, offs); 702 else 703 return 0; 704} 705 706static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl, 707 enum brcmnand_reg reg, u32 val) 708{ 709 u16 offs = ctrl->reg_offsets[reg]; 710 711 if (offs) 712 nand_writereg(ctrl, offs, val); 713} 714 715static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl, 716 enum brcmnand_reg reg, u32 mask, unsigned 717 int shift, u32 val) 718{ 719 u32 tmp = brcmnand_read_reg(ctrl, reg); 720 721 tmp &= ~mask; 722 tmp |= val << shift; 723 brcmnand_write_reg(ctrl, reg, tmp); 724} 725 726static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word) 727{ 728 return __raw_readl(ctrl->nand_fc + word * 4); 729} 730 731static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl, 732 int word, u32 val) 733{ 734 __raw_writel(val, ctrl->nand_fc + word * 4); 735} 736 737static void brcmnand_clear_ecc_addr(struct brcmnand_controller *ctrl) 738{ 739 740 /* Clear error addresses */ 741 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0); 742 brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0); 743 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0); 744 brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0); 745} 746 747static u64 brcmnand_get_uncorrecc_addr(struct brcmnand_controller *ctrl) 748{ 749 u64 err_addr; 750 751 err_addr = brcmnand_read_reg(ctrl, BRCMNAND_UNCORR_ADDR); 752 err_addr |= ((u64)(brcmnand_read_reg(ctrl, 753 BRCMNAND_UNCORR_EXT_ADDR) 754 & 0xffff) << 32); 755 756 return err_addr; 757} 758 759static u64 brcmnand_get_correcc_addr(struct brcmnand_controller *ctrl) 760{ 761 u64 err_addr; 762 763 err_addr = brcmnand_read_reg(ctrl, BRCMNAND_CORR_ADDR); 764 err_addr |= ((u64)(brcmnand_read_reg(ctrl, 765 BRCMNAND_CORR_EXT_ADDR) 766 & 0xffff) << 32); 767 768 return err_addr; 769} 770 771static void brcmnand_set_cmd_addr(struct mtd_info *mtd, u64 addr) 772{ 773 struct nand_chip *chip = mtd_to_nand(mtd); 774 struct brcmnand_host *host = nand_get_controller_data(chip); 775 struct brcmnand_controller *ctrl = host->ctrl; 776 777 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS, 778 (host->cs << 16) | ((addr >> 32) & 0xffff)); 779 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS); 780 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, 781 lower_32_bits(addr)); 782 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); 783} 784 785static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs, 786 enum brcmnand_cs_reg reg) 787{ 788 u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE]; 789 u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE]; 790 u8 cs_offs; 791 792 if (cs == 0 && ctrl->cs0_offsets) 793 cs_offs = ctrl->cs0_offsets[reg]; 794 else 795 cs_offs = ctrl->cs_offsets[reg]; 796 797 if (cs && offs_cs1) 798 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs; 799 800 return offs_cs0 + cs * ctrl->reg_spacing + cs_offs; 801} 802 803static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl) 804{ 805 if (ctrl->nand_version < 0x0600) 806 return 1; 807 return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT); 808} 809 810static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val) 811{ 812 struct brcmnand_controller *ctrl = host->ctrl; 813 unsigned int shift = 0, bits; 814 enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD; 815 int cs = host->cs; 816 817 if (!ctrl->reg_offsets[reg]) 818 return; 819 820 if (ctrl->nand_version == 0x0702) 821 bits = 7; 822 else if (ctrl->nand_version >= 0x0600) 823 bits = 6; 824 else if (ctrl->nand_version >= 0x0500) 825 bits = 5; 826 else 827 bits = 4; 828 829 if (ctrl->nand_version >= 0x0702) { 830 if (cs >= 4) 831 reg = BRCMNAND_CORR_THRESHOLD_EXT; 832 shift = (cs % 4) * bits; 833 } else if (ctrl->nand_version >= 0x0600) { 834 if (cs >= 5) 835 reg = BRCMNAND_CORR_THRESHOLD_EXT; 836 shift = (cs % 5) * bits; 837 } 838 brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val); 839} 840 841static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl) 842{ 843 if (ctrl->nand_version < 0x0602) 844 return 24; 845 return 0; 846} 847 848/*********************************************************************** 849 * NAND ACC CONTROL bitfield 850 * 851 * Some bits have remained constant throughout hardware revision, while 852 * others have shifted around. 853 ***********************************************************************/ 854 855/* Constant for all versions (where supported) */ 856enum { 857 /* See BRCMNAND_HAS_CACHE_MODE */ 858 ACC_CONTROL_CACHE_MODE = BIT(22), 859 860 /* See BRCMNAND_HAS_PREFETCH */ 861 ACC_CONTROL_PREFETCH = BIT(23), 862 863 ACC_CONTROL_PAGE_HIT = BIT(24), 864 ACC_CONTROL_WR_PREEMPT = BIT(25), 865 ACC_CONTROL_PARTIAL_PAGE = BIT(26), 866 ACC_CONTROL_RD_ERASED = BIT(27), 867 ACC_CONTROL_FAST_PGM_RDIN = BIT(28), 868 ACC_CONTROL_WR_ECC = BIT(30), 869 ACC_CONTROL_RD_ECC = BIT(31), 870}; 871 872static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl) 873{ 874 if (ctrl->nand_version == 0x0702) 875 return GENMASK(7, 0); 876 else if (ctrl->nand_version >= 0x0600) 877 return GENMASK(6, 0); 878 else if (ctrl->nand_version >= 0x0303) 879 return GENMASK(5, 0); 880 else 881 return GENMASK(4, 0); 882} 883 884#define NAND_ACC_CONTROL_ECC_SHIFT 16 885#define NAND_ACC_CONTROL_ECC_EXT_SHIFT 13 886 887static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl) 888{ 889 u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f; 890 891 mask <<= NAND_ACC_CONTROL_ECC_SHIFT; 892 893 /* v7.2 includes additional ECC levels */ 894 if (ctrl->nand_version >= 0x0702) 895 mask |= 0x7 << NAND_ACC_CONTROL_ECC_EXT_SHIFT; 896 897 return mask; 898} 899 900static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en) 901{ 902 struct brcmnand_controller *ctrl = host->ctrl; 903 u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); 904 u32 acc_control = nand_readreg(ctrl, offs); 905 u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC; 906 907 if (en) { 908 acc_control |= ecc_flags; /* enable RD/WR ECC */ 909 acc_control |= host->hwcfg.ecc_level 910 << NAND_ACC_CONTROL_ECC_SHIFT; 911 } else { 912 acc_control &= ~ecc_flags; /* disable RD/WR ECC */ 913 acc_control &= ~brcmnand_ecc_level_mask(ctrl); 914 } 915 916 nand_writereg(ctrl, offs, acc_control); 917} 918 919static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl) 920{ 921 if (ctrl->nand_version >= 0x0702) 922 return 9; 923 else if (ctrl->nand_version >= 0x0600) 924 return 7; 925 else if (ctrl->nand_version >= 0x0500) 926 return 6; 927 else 928 return -1; 929} 930 931static int brcmnand_get_sector_size_1k(struct brcmnand_host *host) 932{ 933 struct brcmnand_controller *ctrl = host->ctrl; 934 int shift = brcmnand_sector_1k_shift(ctrl); 935 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, 936 BRCMNAND_CS_ACC_CONTROL); 937 938 if (shift < 0) 939 return 0; 940 941 return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1; 942} 943 944static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val) 945{ 946 struct brcmnand_controller *ctrl = host->ctrl; 947 int shift = brcmnand_sector_1k_shift(ctrl); 948 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, 949 BRCMNAND_CS_ACC_CONTROL); 950 u32 tmp; 951 952 if (shift < 0) 953 return; 954 955 tmp = nand_readreg(ctrl, acc_control_offs); 956 tmp &= ~(1 << shift); 957 tmp |= (!!val) << shift; 958 nand_writereg(ctrl, acc_control_offs, tmp); 959} 960 961/*********************************************************************** 962 * CS_NAND_SELECT 963 ***********************************************************************/ 964 965enum { 966 CS_SELECT_NAND_WP = BIT(29), 967 CS_SELECT_AUTO_DEVICE_ID_CFG = BIT(30), 968}; 969 970static int bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl, 971 u32 mask, u32 expected_val, 972 unsigned long timeout_ms) 973{ 974#ifndef __UBOOT__ 975 unsigned long limit; 976 u32 val; 977 978 if (!timeout_ms) 979 timeout_ms = NAND_POLL_STATUS_TIMEOUT_MS; 980 981 limit = jiffies + msecs_to_jiffies(timeout_ms); 982 do { 983 val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS); 984 if ((val & mask) == expected_val) 985 return 0; 986 987 cpu_relax(); 988 } while (time_after(limit, jiffies)); 989#else 990 unsigned long base, limit; 991 u32 val; 992 993 if (!timeout_ms) 994 timeout_ms = NAND_POLL_STATUS_TIMEOUT_MS; 995 996 base = get_timer(0); 997 limit = CONFIG_SYS_HZ * timeout_ms / 1000; 998 do { 999 val = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS); 1000 if ((val & mask) == expected_val) 1001 return 0; 1002 1003 cpu_relax(); 1004 } while (get_timer(base) < limit); 1005#endif /* __UBOOT__ */ 1006 1007 dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n", 1008 expected_val, val & mask); 1009 1010 return -ETIMEDOUT; 1011} 1012 1013static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en) 1014{ 1015 u32 val = en ? CS_SELECT_NAND_WP : 0; 1016 1017 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val); 1018} 1019 1020/*********************************************************************** 1021 * Flash DMA 1022 ***********************************************************************/ 1023 1024static inline bool has_flash_dma(struct brcmnand_controller *ctrl) 1025{ 1026 return ctrl->flash_dma_base; 1027} 1028 1029static inline bool flash_dma_buf_ok(const void *buf) 1030{ 1031#ifndef __UBOOT__ 1032 return buf && !is_vmalloc_addr(buf) && 1033 likely(IS_ALIGNED((uintptr_t)buf, 4)); 1034#else 1035 return buf && likely(IS_ALIGNED((uintptr_t)buf, 4)); 1036#endif /* __UBOOT__ */ 1037} 1038 1039static inline void flash_dma_writel(struct brcmnand_controller *ctrl, 1040 enum flash_dma_reg dma_reg, u32 val) 1041{ 1042 u16 offs = ctrl->flash_dma_offsets[dma_reg]; 1043 1044 brcmnand_writel(val, ctrl->flash_dma_base + offs); 1045} 1046 1047static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, 1048 enum flash_dma_reg dma_reg) 1049{ 1050 u16 offs = ctrl->flash_dma_offsets[dma_reg]; 1051 1052 return brcmnand_readl(ctrl->flash_dma_base + offs); 1053} 1054 1055/* Low-level operation types: command, address, write, or read */ 1056enum brcmnand_llop_type { 1057 LL_OP_CMD, 1058 LL_OP_ADDR, 1059 LL_OP_WR, 1060 LL_OP_RD, 1061}; 1062 1063/*********************************************************************** 1064 * Internal support functions 1065 ***********************************************************************/ 1066 1067static inline bool is_hamming_ecc(struct brcmnand_controller *ctrl, 1068 struct brcmnand_cfg *cfg) 1069{ 1070 if (ctrl->nand_version <= 0x0701) 1071 return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 && 1072 cfg->ecc_level == 15; 1073 else 1074 return cfg->sector_size_1k == 0 && ((cfg->spare_area_size == 16 && 1075 cfg->ecc_level == 15) || 1076 (cfg->spare_area_size == 28 && cfg->ecc_level == 16)); 1077} 1078 1079/* 1080 * Returns a nand_ecclayout strucutre for the given layout/configuration. 1081 * Returns NULL on failure. 1082 */ 1083static struct nand_ecclayout *brcmnand_create_layout(int ecc_level, 1084 struct brcmnand_host *host) 1085{ 1086 struct brcmnand_cfg *cfg = &host->hwcfg; 1087 int i, j; 1088 struct nand_ecclayout *layout; 1089 int req; 1090 int sectors; 1091 int sas; 1092 int idx1, idx2; 1093 1094#ifndef __UBOOT__ 1095 layout = devm_kzalloc(&host->pdev->dev, sizeof(*layout), GFP_KERNEL); 1096#else 1097 layout = devm_kzalloc(host->pdev, sizeof(*layout), GFP_KERNEL); 1098#endif 1099 if (!layout) 1100 return NULL; 1101 1102 sectors = cfg->page_size / (512 << cfg->sector_size_1k); 1103 sas = cfg->spare_area_size << cfg->sector_size_1k; 1104 1105 /* Hamming */ 1106 if (is_hamming_ecc(host->ctrl, cfg)) { 1107 for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) { 1108 /* First sector of each page may have BBI */ 1109 if (i == 0) { 1110 layout->oobfree[idx2].offset = i * sas + 1; 1111 /* Small-page NAND use byte 6 for BBI */ 1112 if (cfg->page_size == 512) 1113 layout->oobfree[idx2].offset--; 1114 layout->oobfree[idx2].length = 5; 1115 } else { 1116 layout->oobfree[idx2].offset = i * sas; 1117 layout->oobfree[idx2].length = 6; 1118 } 1119 idx2++; 1120 layout->eccpos[idx1++] = i * sas + 6; 1121 layout->eccpos[idx1++] = i * sas + 7; 1122 layout->eccpos[idx1++] = i * sas + 8; 1123 layout->oobfree[idx2].offset = i * sas + 9; 1124 layout->oobfree[idx2].length = 7; 1125 idx2++; 1126 /* Leave zero-terminated entry for OOBFREE */ 1127 if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE || 1128 idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1) 1129 break; 1130 } 1131 1132 return layout; 1133 } 1134 1135 /* 1136 * CONTROLLER_VERSION: 1137 * < v5.0: ECC_REQ = ceil(BCH_T * 13/8) 1138 * >= v5.0: ECC_REQ = ceil(BCH_T * 14/8) 1139 * But we will just be conservative. 1140 */ 1141 req = DIV_ROUND_UP(ecc_level * 14, 8); 1142 if (req >= sas) { 1143 dev_err(host->pdev, 1144 "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n", 1145 req, sas); 1146 return NULL; 1147 } 1148 1149 layout->eccbytes = req * sectors; 1150 for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) { 1151 for (j = sas - req; j < sas && idx1 < 1152 MTD_MAX_ECCPOS_ENTRIES_LARGE; j++, idx1++) 1153 layout->eccpos[idx1] = i * sas + j; 1154 1155 /* First sector of each page may have BBI */ 1156 if (i == 0) { 1157 if (cfg->page_size == 512 && (sas - req >= 6)) { 1158 /* Small-page NAND use byte 6 for BBI */ 1159 layout->oobfree[idx2].offset = 0; 1160 layout->oobfree[idx2].length = 5; 1161 idx2++; 1162 if (sas - req > 6) { 1163 layout->oobfree[idx2].offset = 6; 1164 layout->oobfree[idx2].length = 1165 sas - req - 6; 1166 idx2++; 1167 } 1168 } else if (sas > req + 1) { 1169 layout->oobfree[idx2].offset = i * sas + 1; 1170 layout->oobfree[idx2].length = sas - req - 1; 1171 idx2++; 1172 } 1173 } else if (sas > req) { 1174 layout->oobfree[idx2].offset = i * sas; 1175 layout->oobfree[idx2].length = sas - req; 1176 idx2++; 1177 } 1178 /* Leave zero-terminated entry for OOBFREE */ 1179 if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE || 1180 idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1) 1181 break; 1182 } 1183 1184 return layout; 1185} 1186 1187static struct nand_ecclayout *brcmstb_choose_ecc_layout( 1188 struct brcmnand_host *host) 1189{ 1190 struct nand_ecclayout *layout; 1191 struct brcmnand_cfg *p = &host->hwcfg; 1192 unsigned int ecc_level = p->ecc_level; 1193 1194 if (p->sector_size_1k) 1195 ecc_level <<= 1; 1196 1197 layout = brcmnand_create_layout(ecc_level, host); 1198 if (!layout) { 1199 dev_err(host->pdev, 1200 "no proper ecc_layout for this NAND cfg\n"); 1201 return NULL; 1202 } 1203 1204 return layout; 1205} 1206 1207static void brcmnand_wp(struct mtd_info *mtd, int wp) 1208{ 1209 struct nand_chip *chip = mtd_to_nand(mtd); 1210 struct brcmnand_host *host = nand_get_controller_data(chip); 1211 struct brcmnand_controller *ctrl = host->ctrl; 1212 1213 if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) { 1214 static int old_wp = -1; 1215 int ret; 1216 1217 if (old_wp != wp) { 1218 dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off"); 1219 old_wp = wp; 1220 } 1221 1222 /* 1223 * make sure ctrl/flash ready before and after 1224 * changing state of #WP pin 1225 */ 1226 ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY | 1227 NAND_STATUS_READY, 1228 NAND_CTRL_RDY | 1229 NAND_STATUS_READY, 0); 1230 if (ret) 1231 return; 1232 1233 brcmnand_set_wp(ctrl, wp); 1234 nand_status_op(chip, NULL); 1235 /* NAND_STATUS_WP 0x00 = protected, 0x80 = not protected */ 1236 ret = bcmnand_ctrl_poll_status(ctrl, 1237 NAND_CTRL_RDY | 1238 NAND_STATUS_READY | 1239 NAND_STATUS_WP, 1240 NAND_CTRL_RDY | 1241 NAND_STATUS_READY | 1242 (wp ? 0 : NAND_STATUS_WP), 0); 1243 if (ret) 1244 dev_err(host->pdev, "nand #WP expected %s\n", 1245 wp ? "on" : "off"); 1246 } 1247} 1248 1249/* Helper functions for reading and writing OOB registers */ 1250static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs) 1251{ 1252 u16 offset0, offset10, reg_offs; 1253 1254 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE]; 1255 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE]; 1256 1257 if (offs >= ctrl->max_oob) 1258 return 0x77; 1259 1260 if (offs >= 16 && offset10) 1261 reg_offs = offset10 + ((offs - 0x10) & ~0x03); 1262 else 1263 reg_offs = offset0 + (offs & ~0x03); 1264 1265 return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3)); 1266} 1267 1268static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs, 1269 u32 data) 1270{ 1271 u16 offset0, offset10, reg_offs; 1272 1273 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE]; 1274 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE]; 1275 1276 if (offs >= ctrl->max_oob) 1277 return; 1278 1279 if (offs >= 16 && offset10) 1280 reg_offs = offset10 + ((offs - 0x10) & ~0x03); 1281 else 1282 reg_offs = offset0 + (offs & ~0x03); 1283 1284 nand_writereg(ctrl, reg_offs, data); 1285} 1286 1287/* 1288 * read_oob_from_regs - read data from OOB registers 1289 * @ctrl: NAND controller 1290 * @i: sub-page sector index 1291 * @oob: buffer to read to 1292 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE) 1293 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal 1294 */ 1295static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob, 1296 int sas, int sector_1k) 1297{ 1298 int tbytes = sas << sector_1k; 1299 int j; 1300 1301 /* Adjust OOB values for 1K sector size */ 1302 if (sector_1k && (i & 0x01)) 1303 tbytes = max(0, tbytes - (int)ctrl->max_oob); 1304 tbytes = min_t(int, tbytes, ctrl->max_oob); 1305 1306 for (j = 0; j < tbytes; j++) 1307 oob[j] = oob_reg_read(ctrl, j); 1308 return tbytes; 1309} 1310 1311/* 1312 * write_oob_to_regs - write data to OOB registers 1313 * @i: sub-page sector index 1314 * @oob: buffer to write from 1315 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE) 1316 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal 1317 */ 1318static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i, 1319 const u8 *oob, int sas, int sector_1k) 1320{ 1321 int tbytes = sas << sector_1k; 1322 int j; 1323 1324 /* Adjust OOB values for 1K sector size */ 1325 if (sector_1k && (i & 0x01)) 1326 tbytes = max(0, tbytes - (int)ctrl->max_oob); 1327 tbytes = min_t(int, tbytes, ctrl->max_oob); 1328 1329 for (j = 0; j < tbytes; j += 4) 1330 oob_reg_write(ctrl, j, 1331 (oob[j + 0] << 24) | 1332 (oob[j + 1] << 16) | 1333 (oob[j + 2] << 8) | 1334 (oob[j + 3] << 0)); 1335 return tbytes; 1336} 1337 1338#ifndef __UBOOT__ 1339static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data) 1340{ 1341 struct brcmnand_controller *ctrl = data; 1342 1343 /* Discard all NAND_CTLRDY interrupts during DMA */ 1344 if (ctrl->dma_pending) 1345 return IRQ_HANDLED; 1346 1347 complete(&ctrl->done); 1348 return IRQ_HANDLED; 1349} 1350 1351/* Handle SoC-specific interrupt hardware */ 1352static irqreturn_t brcmnand_irq(int irq, void *data) 1353{ 1354 struct brcmnand_controller *ctrl = data; 1355 1356 if (ctrl->soc->ctlrdy_ack(ctrl->soc)) 1357 return brcmnand_ctlrdy_irq(irq, data); 1358 1359 return IRQ_NONE; 1360} 1361 1362static irqreturn_t brcmnand_dma_irq(int irq, void *data) 1363{ 1364 struct brcmnand_controller *ctrl = data; 1365 1366 complete(&ctrl->dma_done); 1367 1368 return IRQ_HANDLED; 1369} 1370#endif /* __UBOOT__ */ 1371 1372static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd) 1373{ 1374 struct brcmnand_controller *ctrl = host->ctrl; 1375 int ret; 1376 u64 cmd_addr; 1377 1378 cmd_addr = brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS); 1379 1380 dev_dbg(ctrl->dev, "send native cmd %d addr 0x%llx\n", cmd, cmd_addr); 1381 1382 BUG_ON(ctrl->cmd_pending != 0); 1383 ctrl->cmd_pending = cmd; 1384 1385 ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, 0); 1386 WARN_ON(ret); 1387 1388 mb(); /* flush previous writes */ 1389 brcmnand_write_reg(ctrl, BRCMNAND_CMD_START, 1390 cmd << brcmnand_cmd_shift(ctrl)); 1391} 1392 1393/*********************************************************************** 1394 * NAND MTD API: read/program/erase 1395 ***********************************************************************/ 1396 1397static void brcmnand_cmd_ctrl(struct mtd_info *mtd, int dat, 1398 unsigned int ctrl) 1399{ 1400 /* intentionally left blank */ 1401} 1402 1403static int brcmnand_waitfunc(struct mtd_info *mtd, struct nand_chip *this) 1404{ 1405 struct nand_chip *chip = mtd_to_nand(mtd); 1406 struct brcmnand_host *host = nand_get_controller_data(chip); 1407 struct brcmnand_controller *ctrl = host->ctrl; 1408 1409#ifndef __UBOOT__ 1410 unsigned long timeo = msecs_to_jiffies(100); 1411 1412 dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending); 1413 if (ctrl->cmd_pending && 1414 wait_for_completion_timeout(&ctrl->done, timeo) <= 0) { 1415 u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START) 1416 >> brcmnand_cmd_shift(ctrl); 1417 1418 dev_err_ratelimited(ctrl->dev, 1419 "timeout waiting for command %#02x\n", cmd); 1420 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n", 1421 brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS)); 1422 } 1423#else 1424 unsigned long timeo = 100; /* 100 msec */ 1425 int ret; 1426 1427 dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending); 1428 1429 ret = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY, NAND_CTRL_RDY, timeo); 1430 WARN_ON(ret); 1431#endif /* __UBOOT__ */ 1432 1433 ctrl->cmd_pending = 0; 1434 return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & 1435 INTFC_FLASH_STATUS; 1436} 1437 1438enum { 1439 LLOP_RE = BIT(16), 1440 LLOP_WE = BIT(17), 1441 LLOP_ALE = BIT(18), 1442 LLOP_CLE = BIT(19), 1443 LLOP_RETURN_IDLE = BIT(31), 1444 1445 LLOP_DATA_MASK = GENMASK(15, 0), 1446}; 1447 1448static int brcmnand_low_level_op(struct brcmnand_host *host, 1449 enum brcmnand_llop_type type, u32 data, 1450 bool last_op) 1451{ 1452 struct mtd_info *mtd = nand_to_mtd(&host->chip); 1453 struct nand_chip *chip = &host->chip; 1454 struct brcmnand_controller *ctrl = host->ctrl; 1455 u32 tmp; 1456 1457 tmp = data & LLOP_DATA_MASK; 1458 switch (type) { 1459 case LL_OP_CMD: 1460 tmp |= LLOP_WE | LLOP_CLE; 1461 break; 1462 case LL_OP_ADDR: 1463 /* WE | ALE */ 1464 tmp |= LLOP_WE | LLOP_ALE; 1465 break; 1466 case LL_OP_WR: 1467 /* WE */ 1468 tmp |= LLOP_WE; 1469 break; 1470 case LL_OP_RD: 1471 /* RE */ 1472 tmp |= LLOP_RE; 1473 break; 1474 } 1475 if (last_op) 1476 /* RETURN_IDLE */ 1477 tmp |= LLOP_RETURN_IDLE; 1478 1479 dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp); 1480 1481 brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp); 1482 (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP); 1483 1484 brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP); 1485 return brcmnand_waitfunc(mtd, chip); 1486} 1487 1488static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command, 1489 int column, int page_addr) 1490{ 1491 struct nand_chip *chip = mtd_to_nand(mtd); 1492 struct brcmnand_host *host = nand_get_controller_data(chip); 1493 struct brcmnand_controller *ctrl = host->ctrl; 1494 u64 addr = (u64)page_addr << chip->page_shift; 1495 int native_cmd = 0; 1496 1497 if (command == NAND_CMD_READID || command == NAND_CMD_PARAM || 1498 command == NAND_CMD_RNDOUT) 1499 addr = (u64)column; 1500 /* Avoid propagating a negative, don't-care address */ 1501 else if (page_addr < 0) 1502 addr = 0; 1503 1504 dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command, 1505 (unsigned long long)addr); 1506 1507 host->last_cmd = command; 1508 host->last_byte = 0; 1509 host->last_addr = addr; 1510 1511 switch (command) { 1512 case NAND_CMD_RESET: 1513 native_cmd = CMD_FLASH_RESET; 1514 break; 1515 case NAND_CMD_STATUS: 1516 native_cmd = CMD_STATUS_READ; 1517 break; 1518 case NAND_CMD_READID: 1519 native_cmd = CMD_DEVICE_ID_READ; 1520 break; 1521 case NAND_CMD_READOOB: 1522 native_cmd = CMD_SPARE_AREA_READ; 1523 break; 1524 case NAND_CMD_ERASE1: 1525 native_cmd = CMD_BLOCK_ERASE; 1526 brcmnand_wp(mtd, 0); 1527 break; 1528 case NAND_CMD_PARAM: 1529 native_cmd = CMD_PARAMETER_READ; 1530 break; 1531 case NAND_CMD_SET_FEATURES: 1532 case NAND_CMD_GET_FEATURES: 1533 brcmnand_low_level_op(host, LL_OP_CMD, command, false); 1534 brcmnand_low_level_op(host, LL_OP_ADDR, column, false); 1535 break; 1536 case NAND_CMD_RNDOUT: 1537 native_cmd = CMD_PARAMETER_CHANGE_COL; 1538 addr &= ~((u64)(FC_BYTES - 1)); 1539 /* 1540 * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0 1541 * NB: hwcfg.sector_size_1k may not be initialized yet 1542 */ 1543 if (brcmnand_get_sector_size_1k(host)) { 1544 host->hwcfg.sector_size_1k = 1545 brcmnand_get_sector_size_1k(host); 1546 brcmnand_set_sector_size_1k(host, 0); 1547 } 1548 break; 1549 } 1550 1551 if (!native_cmd) 1552 return; 1553 1554 brcmnand_set_cmd_addr(mtd, addr); 1555 brcmnand_send_cmd(host, native_cmd); 1556 brcmnand_waitfunc(mtd, chip); 1557 1558 if (native_cmd == CMD_PARAMETER_READ || 1559 native_cmd == CMD_PARAMETER_CHANGE_COL) { 1560 /* Copy flash cache word-wise */ 1561 u32 *flash_cache = (u32 *)ctrl->flash_cache; 1562 int i; 1563 1564 brcmnand_soc_data_bus_prepare(ctrl->soc, true); 1565 1566 /* 1567 * Must cache the FLASH_CACHE now, since changes in 1568 * SECTOR_SIZE_1K may invalidate it 1569 */ 1570 for (i = 0; i < FC_WORDS; i++) { 1571 u32 fc; 1572 1573 fc = brcmnand_read_fc(ctrl, i); 1574 1575 /* 1576 * Flash cache is big endian for parameter pages, at 1577 * least on STB SoCs 1578 */ 1579 if (ctrl->parameter_page_big_endian) 1580 flash_cache[i] = be32_to_cpu(fc); 1581 else 1582 flash_cache[i] = le32_to_cpu(fc); 1583 } 1584 1585 brcmnand_soc_data_bus_unprepare(ctrl->soc, true); 1586 1587 /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */ 1588 if (host->hwcfg.sector_size_1k) 1589 brcmnand_set_sector_size_1k(host, 1590 host->hwcfg.sector_size_1k); 1591 } 1592 1593 /* Re-enable protection is necessary only after erase */ 1594 if (command == NAND_CMD_ERASE1) 1595 brcmnand_wp(mtd, 1); 1596} 1597 1598static uint8_t brcmnand_read_byte(struct mtd_info *mtd) 1599{ 1600 struct nand_chip *chip = mtd_to_nand(mtd); 1601 struct brcmnand_host *host = nand_get_controller_data(chip); 1602 struct brcmnand_controller *ctrl = host->ctrl; 1603 uint8_t ret = 0; 1604 int addr, offs; 1605 1606 switch (host->last_cmd) { 1607 case NAND_CMD_READID: 1608 if (host->last_byte < 4) 1609 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >> 1610 (24 - (host->last_byte << 3)); 1611 else if (host->last_byte < 8) 1612 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >> 1613 (56 - (host->last_byte << 3)); 1614 break; 1615 1616 case NAND_CMD_READOOB: 1617 ret = oob_reg_read(ctrl, host->last_byte); 1618 break; 1619 1620 case NAND_CMD_STATUS: 1621 ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) & 1622 INTFC_FLASH_STATUS; 1623 if (wp_on) /* hide WP status */ 1624 ret |= NAND_STATUS_WP; 1625 break; 1626 1627 case NAND_CMD_PARAM: 1628 case NAND_CMD_RNDOUT: 1629 addr = host->last_addr + host->last_byte; 1630 offs = addr & (FC_BYTES - 1); 1631 1632 /* At FC_BYTES boundary, switch to next column */ 1633 if (host->last_byte > 0 && offs == 0) 1634 nand_change_read_column_op(chip, addr, NULL, 0, false); 1635 1636 ret = ctrl->flash_cache[offs]; 1637 break; 1638 case NAND_CMD_GET_FEATURES: 1639 if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) { 1640 ret = 0; 1641 } else { 1642 bool last = host->last_byte == 1643 ONFI_SUBFEATURE_PARAM_LEN - 1; 1644 brcmnand_low_level_op(host, LL_OP_RD, 0, last); 1645 ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff; 1646 } 1647 } 1648 1649 dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret); 1650 host->last_byte++; 1651 1652 return ret; 1653} 1654 1655static void brcmnand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) 1656{ 1657 int i; 1658 1659 for (i = 0; i < len; i++, buf++) 1660 *buf = brcmnand_read_byte(mtd); 1661} 1662 1663static void brcmnand_write_buf(struct mtd_info *mtd, const uint8_t *buf, 1664 int len) 1665{ 1666 int i; 1667 struct nand_chip *chip = mtd_to_nand(mtd); 1668 struct brcmnand_host *host = nand_get_controller_data(chip); 1669 1670 switch (host->last_cmd) { 1671 case NAND_CMD_SET_FEATURES: 1672 for (i = 0; i < len; i++) 1673 brcmnand_low_level_op(host, LL_OP_WR, buf[i], 1674 (i + 1) == len); 1675 break; 1676 default: 1677 BUG(); 1678 break; 1679 } 1680} 1681 1682/** 1683 * Construct a FLASH_DMA descriptor as part of a linked list. You must know the 1684 * following ahead of time: 1685 * - Is this descriptor the beginning or end of a linked list? 1686 * - What is the (DMA) address of the next descriptor in the linked list? 1687 */ 1688#ifndef __UBOOT__ 1689static int brcmnand_fill_dma_desc(struct brcmnand_host *host, 1690 struct brcm_nand_dma_desc *desc, u64 addr, 1691 dma_addr_t buf, u32 len, u8 dma_cmd, 1692 bool begin, bool end, 1693 dma_addr_t next_desc) 1694{ 1695 memset(desc, 0, sizeof(*desc)); 1696 /* Descriptors are written in native byte order (wordwise) */ 1697 desc->next_desc = lower_32_bits(next_desc); 1698 desc->next_desc_ext = upper_32_bits(next_desc); 1699 desc->cmd_irq = (dma_cmd << 24) | 1700 (end ? (0x03 << 8) : 0) | /* IRQ | STOP */ 1701 (!!begin) | ((!!end) << 1); /* head, tail */ 1702#ifdef CONFIG_CPU_BIG_ENDIAN 1703 desc->cmd_irq |= 0x01 << 12; 1704#endif 1705 desc->dram_addr = lower_32_bits(buf); 1706 desc->dram_addr_ext = upper_32_bits(buf); 1707 desc->tfr_len = len; 1708 desc->total_len = len; 1709 desc->flash_addr = lower_32_bits(addr); 1710 desc->flash_addr_ext = upper_32_bits(addr); 1711 desc->cs = host->cs; 1712 desc->status_valid = 0x01; 1713 return 0; 1714} 1715 1716/** 1717 * Kick the FLASH_DMA engine, with a given DMA descriptor 1718 */ 1719static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc) 1720{ 1721 struct brcmnand_controller *ctrl = host->ctrl; 1722 unsigned long timeo = msecs_to_jiffies(100); 1723 1724 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc)); 1725 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC); 1726 if (ctrl->nand_version > 0x0602) { 1727 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, 1728 upper_32_bits(desc)); 1729 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT); 1730 } 1731 1732 /* Start FLASH_DMA engine */ 1733 ctrl->dma_pending = true; 1734 mb(); /* flush previous writes */ 1735 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */ 1736 1737 if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) { 1738 dev_err(ctrl->dev, 1739 "timeout waiting for DMA; status %#x, error status %#x\n", 1740 flash_dma_readl(ctrl, FLASH_DMA_STATUS), 1741 flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS)); 1742 } 1743 ctrl->dma_pending = false; 1744 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */ 1745} 1746 1747static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf, 1748 u32 len, u8 dma_cmd) 1749{ 1750 struct brcmnand_controller *ctrl = host->ctrl; 1751 dma_addr_t buf_pa; 1752 int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE; 1753 1754 buf_pa = dma_map_single(ctrl->dev, buf, len, dir); 1755 if (dma_mapping_error(ctrl->dev, buf_pa)) { 1756 dev_err(ctrl->dev, "unable to map buffer for DMA\n"); 1757 return -ENOMEM; 1758 } 1759 1760 brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len, 1761 dma_cmd, true, true, 0); 1762 1763 brcmnand_dma_run(host, ctrl->dma_pa); 1764 1765 dma_unmap_single(ctrl->dev, buf_pa, len, dir); 1766 1767 if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR) 1768 return -EBADMSG; 1769 else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR) 1770 return -EUCLEAN; 1771 1772 return 0; 1773} 1774#endif /* __UBOOT__ */ 1775 1776/* 1777 * Assumes proper CS is already set 1778 */ 1779static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip, 1780 u64 addr, unsigned int trans, u32 *buf, 1781 u8 *oob, u64 *err_addr) 1782{ 1783 struct brcmnand_host *host = nand_get_controller_data(chip); 1784 struct brcmnand_controller *ctrl = host->ctrl; 1785 int i, j, ret = 0; 1786 1787 brcmnand_clear_ecc_addr(ctrl); 1788 1789 for (i = 0; i < trans; i++, addr += FC_BYTES) { 1790 brcmnand_set_cmd_addr(mtd, addr); 1791 /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */ 1792 brcmnand_send_cmd(host, CMD_PAGE_READ); 1793 brcmnand_waitfunc(mtd, chip); 1794 1795 if (likely(buf)) { 1796 brcmnand_soc_data_bus_prepare(ctrl->soc, false); 1797 1798 for (j = 0; j < FC_WORDS; j++, buf++) 1799 *buf = brcmnand_read_fc(ctrl, j); 1800 1801 brcmnand_soc_data_bus_unprepare(ctrl->soc, false); 1802 } 1803 1804 if (oob) 1805 oob += read_oob_from_regs(ctrl, i, oob, 1806 mtd->oobsize / trans, 1807 host->hwcfg.sector_size_1k); 1808 1809 if (ret != -EBADMSG) { 1810 *err_addr = brcmnand_get_uncorrecc_addr(ctrl); 1811 1812 if (*err_addr) 1813 ret = -EBADMSG; 1814 } 1815 1816 if (!ret) { 1817 *err_addr = brcmnand_get_correcc_addr(ctrl); 1818 1819 if (*err_addr) 1820 ret = -EUCLEAN; 1821 } 1822 } 1823 1824 return ret; 1825} 1826 1827/* 1828 * Check a page to see if it is erased (w/ bitflips) after an uncorrectable ECC 1829 * error 1830 * 1831 * Because the HW ECC signals an ECC error if an erase paged has even a single 1832 * bitflip, we must check each ECC error to see if it is actually an erased 1833 * page with bitflips, not a truly corrupted page. 1834 * 1835 * On a real error, return a negative error code (-EBADMSG for ECC error), and 1836 * buf will contain raw data. 1837 * Otherwise, buf gets filled with 0xffs and return the maximum number of 1838 * bitflips-per-ECC-sector to the caller. 1839 * 1840 */ 1841static int brcmstb_nand_verify_erased_page(struct mtd_info *mtd, 1842 struct nand_chip *chip, void *buf, u64 addr) 1843{ 1844 struct mtd_oob_region ecc; 1845 int i; 1846 int bitflips = 0; 1847 int page = addr >> chip->page_shift; 1848 int ret; 1849 void *ecc_bytes; 1850 void *ecc_chunk; 1851 1852 if (!buf) { 1853#ifndef __UBOOT__ 1854 buf = chip->data_buf; 1855#else 1856 buf = chip->buffers->databuf; 1857#endif 1858 /* Invalidate page cache */ 1859 chip->pagebuf = -1; 1860 } 1861 1862 /* read without ecc for verification */ 1863 ret = chip->ecc.read_page_raw(mtd, chip, buf, true, page); 1864 if (ret) 1865 return ret; 1866 1867 for (i = 0; i < chip->ecc.steps; i++) { 1868 ecc_chunk = buf + chip->ecc.size * i; 1869 1870 mtd_ooblayout_ecc(mtd, i, &ecc); 1871 ecc_bytes = chip->oob_poi + ecc.offset; 1872 1873 ret = nand_check_erased_ecc_chunk(ecc_chunk, chip->ecc.size, 1874 ecc_bytes, ecc.length, 1875 NULL, 0, 1876 chip->ecc.strength); 1877 if (ret < 0) 1878 return ret; 1879 1880 bitflips = max(bitflips, ret); 1881 } 1882 1883 return bitflips; 1884} 1885 1886static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip, 1887 u64 addr, unsigned int trans, u32 *buf, u8 *oob) 1888{ 1889 struct brcmnand_host *host = nand_get_controller_data(chip); 1890 struct brcmnand_controller *ctrl = host->ctrl; 1891 u64 err_addr = 0; 1892 int err; 1893 bool retry = true; 1894 1895 dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf); 1896 1897try_dmaread: 1898 brcmnand_clear_ecc_addr(ctrl); 1899 1900#ifndef __UBOOT__ 1901 if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) { 1902 err = brcmnand_dma_trans(host, addr, buf, trans * FC_BYTES, 1903 CMD_PAGE_READ); 1904 if (err) { 1905 if (mtd_is_bitflip_or_eccerr(err)) 1906 err_addr = addr; 1907 else 1908 return -EIO; 1909 } 1910 } else { 1911 if (oob) 1912 memset(oob, 0x99, mtd->oobsize); 1913 1914 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf, 1915 oob, &err_addr); 1916 } 1917#else 1918 if (oob) 1919 memset(oob, 0x99, mtd->oobsize); 1920 1921 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf, 1922 oob, &err_addr); 1923#endif /* __UBOOT__ */ 1924 1925 if (mtd_is_eccerr(err)) { 1926 /* 1927 * On controller version and 7.0, 7.1 , DMA read after a 1928 * prior PIO read that reported uncorrectable error, 1929 * the DMA engine captures this error following DMA read 1930 * cleared only on subsequent DMA read, so just retry once 1931 * to clear a possible false error reported for current DMA 1932 * read 1933 */ 1934 if ((ctrl->nand_version == 0x0700) || 1935 (ctrl->nand_version == 0x0701)) { 1936 if (retry) { 1937 retry = false; 1938 goto try_dmaread; 1939 } 1940 } 1941 1942 /* 1943 * Controller version 7.2 has hw encoder to detect erased page 1944 * bitflips, apply sw verification for older controllers only 1945 */ 1946 if (ctrl->nand_version < 0x0702) { 1947 err = brcmstb_nand_verify_erased_page(mtd, chip, buf, 1948 addr); 1949 /* erased page bitflips corrected */ 1950 if (err >= 0) 1951 return err; 1952 } 1953 1954 dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n", 1955 (unsigned long long)err_addr); 1956 mtd->ecc_stats.failed++; 1957 /* NAND layer expects zero on ECC errors */ 1958 return 0; 1959 } 1960 1961 if (mtd_is_bitflip(err)) { 1962 unsigned int corrected = brcmnand_count_corrected(ctrl); 1963 1964 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n", 1965 (unsigned long long)err_addr); 1966 mtd->ecc_stats.corrected += corrected; 1967 /* Always exceed the software-imposed threshold */ 1968 return max(mtd->bitflip_threshold, corrected); 1969 } 1970 1971 return 0; 1972} 1973 1974static int brcmnand_read_page(struct mtd_info *mtd, struct nand_chip *chip, 1975 uint8_t *buf, int oob_required, int page) 1976{ 1977 struct brcmnand_host *host = nand_get_controller_data(chip); 1978 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL; 1979 1980 nand_read_page_op(chip, page, 0, NULL, 0); 1981 1982 return brcmnand_read(mtd, chip, host->last_addr, 1983 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob); 1984} 1985 1986static int brcmnand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip, 1987 uint8_t *buf, int oob_required, int page) 1988{ 1989 struct brcmnand_host *host = nand_get_controller_data(chip); 1990 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL; 1991 int ret; 1992 1993 nand_read_page_op(chip, page, 0, NULL, 0); 1994 1995 brcmnand_set_ecc_enabled(host, 0); 1996 ret = brcmnand_read(mtd, chip, host->last_addr, 1997 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob); 1998 brcmnand_set_ecc_enabled(host, 1); 1999 return ret; 2000} 2001 2002static int brcmnand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, 2003 int page) 2004{ 2005 return brcmnand_read(mtd, chip, (u64)page << chip->page_shift, 2006 mtd->writesize >> FC_SHIFT, 2007 NULL, (u8 *)chip->oob_poi); 2008} 2009 2010static int brcmnand_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip, 2011 int page) 2012{ 2013 struct brcmnand_host *host = nand_get_controller_data(chip); 2014 2015 brcmnand_set_ecc_enabled(host, 0); 2016 brcmnand_read(mtd, chip, (u64)page << chip->page_shift, 2017 mtd->writesize >> FC_SHIFT, 2018 NULL, (u8 *)chip->oob_poi); 2019 brcmnand_set_ecc_enabled(host, 1); 2020 return 0; 2021} 2022 2023static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip, 2024 u64 addr, const u32 *buf, u8 *oob) 2025{ 2026 struct brcmnand_host *host = nand_get_controller_data(chip); 2027 struct brcmnand_controller *ctrl = host->ctrl; 2028 unsigned int i, j, trans = mtd->writesize >> FC_SHIFT; 2029 int status, ret = 0; 2030 2031 dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf); 2032 2033 if (unlikely((unsigned long)buf & 0x03)) { 2034 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf); 2035 buf = (u32 *)((unsigned long)buf & ~0x03); 2036 } 2037 2038 brcmnand_wp(mtd, 0); 2039 2040 for (i = 0; i < ctrl->max_oob; i += 4) 2041 oob_reg_write(ctrl, i, 0xffffffff); 2042 2043#ifndef __UBOOT__ 2044 if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) { 2045 if (brcmnand_dma_trans(host, addr, (u32 *)buf, 2046 mtd->writesize, CMD_PROGRAM_PAGE)) 2047 ret = -EIO; 2048 goto out; 2049 } 2050#endif /* __UBOOT__ */ 2051 2052 for (i = 0; i < trans; i++, addr += FC_BYTES) { 2053 /* full address MUST be set before populating FC */ 2054 brcmnand_set_cmd_addr(mtd, addr); 2055 2056 if (buf) { 2057 brcmnand_soc_data_bus_prepare(ctrl->soc, false); 2058 2059 for (j = 0; j < FC_WORDS; j++, buf++) 2060 brcmnand_write_fc(ctrl, j, *buf); 2061 2062 brcmnand_soc_data_bus_unprepare(ctrl->soc, false); 2063 } else if (oob) { 2064 for (j = 0; j < FC_WORDS; j++) 2065 brcmnand_write_fc(ctrl, j, 0xffffffff); 2066 } 2067 2068 if (oob) { 2069 oob += write_oob_to_regs(ctrl, i, oob, 2070 mtd->oobsize / trans, 2071 host->hwcfg.sector_size_1k); 2072 } 2073 2074 /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */ 2075 brcmnand_send_cmd(host, CMD_PROGRAM_PAGE); 2076 status = brcmnand_waitfunc(mtd, chip); 2077 2078 if (status & NAND_STATUS_FAIL) { 2079 dev_info(ctrl->dev, "program failed at %llx\n", 2080 (unsigned long long)addr); 2081 ret = -EIO; 2082 goto out; 2083 } 2084 } 2085out: 2086 brcmnand_wp(mtd, 1); 2087 return ret; 2088} 2089 2090static int brcmnand_write_page(struct mtd_info *mtd, struct nand_chip *chip, 2091 const uint8_t *buf, int oob_required, int page) 2092{ 2093 struct brcmnand_host *host = nand_get_controller_data(chip); 2094 void *oob = oob_required ? chip->oob_poi : NULL; 2095 2096 nand_prog_page_begin_op(chip, page, 0, NULL, 0); 2097 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob); 2098 2099 return nand_prog_page_end_op(chip); 2100} 2101 2102static int brcmnand_write_page_raw(struct mtd_info *mtd, 2103 struct nand_chip *chip, const uint8_t *buf, 2104 int oob_required, int page) 2105{ 2106 struct brcmnand_host *host = nand_get_controller_data(chip); 2107 void *oob = oob_required ? chip->oob_poi : NULL; 2108 2109 nand_prog_page_begin_op(chip, page, 0, NULL, 0); 2110 brcmnand_set_ecc_enabled(host, 0); 2111 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob); 2112 brcmnand_set_ecc_enabled(host, 1); 2113 2114 return nand_prog_page_end_op(chip); 2115} 2116 2117static int brcmnand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, 2118 int page) 2119{ 2120 return brcmnand_write(mtd, chip, (u64)page << chip->page_shift, 2121 NULL, chip->oob_poi); 2122} 2123 2124static int brcmnand_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip, 2125 int page) 2126{ 2127 struct brcmnand_host *host = nand_get_controller_data(chip); 2128 int ret; 2129 2130 brcmnand_set_ecc_enabled(host, 0); 2131 ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL, 2132 (u8 *)chip->oob_poi); 2133 brcmnand_set_ecc_enabled(host, 1); 2134 2135 return ret; 2136} 2137 2138/*********************************************************************** 2139 * Per-CS setup (1 NAND device) 2140 ***********************************************************************/ 2141 2142static int brcmnand_set_cfg(struct brcmnand_host *host, 2143 struct brcmnand_cfg *cfg) 2144{ 2145 struct brcmnand_controller *ctrl = host->ctrl; 2146 struct nand_chip *chip = &host->chip; 2147 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); 2148 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, 2149 BRCMNAND_CS_CFG_EXT); 2150 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, 2151 BRCMNAND_CS_ACC_CONTROL); 2152 u8 block_size = 0, page_size = 0, device_size = 0; 2153 u32 tmp; 2154 2155 if (ctrl->block_sizes) { 2156 int i, found; 2157 2158 for (i = 0, found = 0; ctrl->block_sizes[i]; i++) 2159 if (ctrl->block_sizes[i] * 1024 == cfg->block_size) { 2160 block_size = i; 2161 found = 1; 2162 } 2163 if (!found) { 2164 dev_warn(ctrl->dev, "invalid block size %u\n", 2165 cfg->block_size); 2166 return -EINVAL; 2167 } 2168 } else { 2169 block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE); 2170 } 2171 2172 if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size && 2173 cfg->block_size > ctrl->max_block_size)) { 2174 dev_warn(ctrl->dev, "invalid block size %u\n", 2175 cfg->block_size); 2176 block_size = 0; 2177 } 2178 2179 if (ctrl->page_sizes) { 2180 int i, found; 2181 2182 for (i = 0, found = 0; ctrl->page_sizes[i]; i++) 2183 if (ctrl->page_sizes[i] == cfg->page_size) { 2184 page_size = i; 2185 found = 1; 2186 } 2187 if (!found) { 2188 dev_warn(ctrl->dev, "invalid page size %u\n", 2189 cfg->page_size); 2190 return -EINVAL; 2191 } 2192 } else { 2193 page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE); 2194 } 2195 2196 if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size && 2197 cfg->page_size > ctrl->max_page_size)) { 2198 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size); 2199 return -EINVAL; 2200 } 2201 2202 if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) { 2203 dev_warn(ctrl->dev, "invalid device size 0x%llx\n", 2204 (unsigned long long)cfg->device_size); 2205 return -EINVAL; 2206 } 2207 device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE); 2208 2209 tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) | 2210 (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) | 2211 (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) | 2212 (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) | 2213 (device_size << CFG_DEVICE_SIZE_SHIFT); 2214 if (cfg_offs == cfg_ext_offs) { 2215 tmp |= (page_size << ctrl->page_size_shift) | 2216 (block_size << CFG_BLK_SIZE_SHIFT); 2217 nand_writereg(ctrl, cfg_offs, tmp); 2218 } else { 2219 nand_writereg(ctrl, cfg_offs, tmp); 2220 tmp = (page_size << CFG_EXT_PAGE_SIZE_SHIFT) | 2221 (block_size << CFG_EXT_BLK_SIZE_SHIFT); 2222 nand_writereg(ctrl, cfg_ext_offs, tmp); 2223 } 2224 2225 tmp = nand_readreg(ctrl, acc_control_offs); 2226 tmp &= ~brcmnand_ecc_level_mask(ctrl); 2227 tmp &= ~brcmnand_spare_area_mask(ctrl); 2228 if (ctrl->nand_version >= 0x0302) { 2229 tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT; 2230 tmp |= cfg->spare_area_size; 2231 } 2232 nand_writereg(ctrl, acc_control_offs, tmp); 2233 2234 brcmnand_set_sector_size_1k(host, cfg->sector_size_1k); 2235 2236 /* threshold = ceil(BCH-level * 0.75) */ 2237 brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4)); 2238 2239 return 0; 2240} 2241 2242static void brcmnand_print_cfg(struct brcmnand_host *host, 2243 char *buf, struct brcmnand_cfg *cfg) 2244{ 2245 buf += sprintf(buf, 2246 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit", 2247 (unsigned long long)cfg->device_size >> 20, 2248 cfg->block_size >> 10, 2249 cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size, 2250 cfg->page_size >= 1024 ? "KiB" : "B", 2251 cfg->spare_area_size, cfg->device_width); 2252 2253 /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */ 2254 if (is_hamming_ecc(host->ctrl, cfg)) 2255 sprintf(buf, ", Hamming ECC"); 2256 else if (cfg->sector_size_1k) 2257 sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1); 2258 else 2259 sprintf(buf, ", BCH-%u", cfg->ecc_level); 2260} 2261 2262/* 2263 * Minimum number of bytes to address a page. Calculated as: 2264 * roundup(log2(size / page-size) / 8) 2265 * 2266 * NB: the following does not "round up" for non-power-of-2 'size'; but this is 2267 * OK because many other things will break if 'size' is irregular... 2268 */ 2269static inline int get_blk_adr_bytes(u64 size, u32 writesize) 2270{ 2271 return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3; 2272} 2273 2274static int brcmnand_setup_dev(struct brcmnand_host *host) 2275{ 2276 struct mtd_info *mtd = nand_to_mtd(&host->chip); 2277 struct nand_chip *chip = &host->chip; 2278 struct brcmnand_controller *ctrl = host->ctrl; 2279 struct brcmnand_cfg *cfg = &host->hwcfg; 2280 char msg[128]; 2281 u32 offs, tmp, oob_sector; 2282 int ret; 2283 2284 memset(cfg, 0, sizeof(*cfg)); 2285 2286#ifndef __UBOOT__ 2287 ret = of_property_read_u32(nand_get_flash_node(chip), 2288 "brcm,nand-oob-sector-size", 2289 &oob_sector); 2290#else 2291 ret = ofnode_read_u32(nand_get_flash_node(chip), 2292 "brcm,nand-oob-sector-size", 2293 &oob_sector); 2294#endif /* __UBOOT__ */ 2295 if (ret) { 2296 /* Use detected size */ 2297 cfg->spare_area_size = mtd->oobsize / 2298 (mtd->writesize >> FC_SHIFT); 2299 } else { 2300 cfg->spare_area_size = oob_sector; 2301 } 2302 if (cfg->spare_area_size > ctrl->max_oob) 2303 cfg->spare_area_size = ctrl->max_oob; 2304 /* 2305 * Set oobsize to be consistent with controller's spare_area_size, as 2306 * the rest is inaccessible. 2307 */ 2308 mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT); 2309 2310 cfg->device_size = mtd->size; 2311 cfg->block_size = mtd->erasesize; 2312 cfg->page_size = mtd->writesize; 2313 cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8; 2314 cfg->col_adr_bytes = 2; 2315 cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize); 2316 2317 if (chip->ecc.mode != NAND_ECC_HW) { 2318 dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n", 2319 chip->ecc.mode); 2320 return -EINVAL; 2321 } 2322 2323 if (chip->ecc.algo == NAND_ECC_UNKNOWN) { 2324 if (chip->ecc.strength == 1 && chip->ecc.size == 512) 2325 /* Default to Hamming for 1-bit ECC, if unspecified */ 2326 chip->ecc.algo = NAND_ECC_HAMMING; 2327 else 2328 /* Otherwise, BCH */ 2329 chip->ecc.algo = NAND_ECC_BCH; 2330 } 2331 2332 if (chip->ecc.algo == NAND_ECC_HAMMING && (chip->ecc.strength != 1 || 2333 chip->ecc.size != 512)) { 2334 dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n", 2335 chip->ecc.strength, chip->ecc.size); 2336 return -EINVAL; 2337 } 2338 2339 switch (chip->ecc.size) { 2340 case 512: 2341 if (chip->ecc.algo == NAND_ECC_HAMMING) 2342 cfg->ecc_level = 15; 2343 else 2344 cfg->ecc_level = chip->ecc.strength; 2345 cfg->sector_size_1k = 0; 2346 break; 2347 case 1024: 2348 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) { 2349 dev_err(ctrl->dev, "1KB sectors not supported\n"); 2350 return -EINVAL; 2351 } 2352 if (chip->ecc.strength & 0x1) { 2353 dev_err(ctrl->dev, 2354 "odd ECC not supported with 1KB sectors\n"); 2355 return -EINVAL; 2356 } 2357 2358 cfg->ecc_level = chip->ecc.strength >> 1; 2359 cfg->sector_size_1k = 1; 2360 break; 2361 default: 2362 dev_err(ctrl->dev, "unsupported ECC size: %d\n", 2363 chip->ecc.size); 2364 return -EINVAL; 2365 } 2366 2367 cfg->ful_adr_bytes = cfg->blk_adr_bytes; 2368 if (mtd->writesize > 512) 2369 cfg->ful_adr_bytes += cfg->col_adr_bytes; 2370 else 2371 cfg->ful_adr_bytes += 1; 2372 2373 ret = brcmnand_set_cfg(host, cfg); 2374 if (ret) 2375 return ret; 2376 2377 brcmnand_set_ecc_enabled(host, 1); 2378 2379 brcmnand_print_cfg(host, msg, cfg); 2380 dev_info(ctrl->dev, "detected %s\n", msg); 2381 2382 /* Configure ACC_CONTROL */ 2383 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); 2384 tmp = nand_readreg(ctrl, offs); 2385 tmp &= ~ACC_CONTROL_PARTIAL_PAGE; 2386 tmp &= ~ACC_CONTROL_RD_ERASED; 2387 2388 /* We need to turn on Read from erased paged protected by ECC */ 2389 if (ctrl->nand_version >= 0x0702) 2390 tmp |= ACC_CONTROL_RD_ERASED; 2391 tmp &= ~ACC_CONTROL_FAST_PGM_RDIN; 2392 if (ctrl->features & BRCMNAND_HAS_PREFETCH) 2393 tmp &= ~ACC_CONTROL_PREFETCH; 2394 2395 nand_writereg(ctrl, offs, tmp); 2396 2397 return 0; 2398} 2399 2400#ifndef __UBOOT__ 2401static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn) 2402#else 2403static int brcmnand_init_cs(struct brcmnand_host *host, ofnode dn) 2404#endif 2405{ 2406 struct brcmnand_controller *ctrl = host->ctrl; 2407#ifndef __UBOOT__ 2408 struct platform_device *pdev = host->pdev; 2409#else 2410 struct udevice *pdev = host->pdev; 2411#endif /* __UBOOT__ */ 2412 struct mtd_info *mtd; 2413 struct nand_chip *chip; 2414 int ret; 2415 u16 cfg_offs; 2416 2417#ifndef __UBOOT__ 2418 ret = of_property_read_u32(dn, "reg", &host->cs); 2419#else 2420 ret = ofnode_read_s32(dn, "reg", &host->cs); 2421#endif 2422 if (ret) { 2423 dev_err(pdev, "can't get chip-select\n"); 2424 return -ENXIO; 2425 } 2426 2427 mtd = nand_to_mtd(&host->chip); 2428 chip = &host->chip; 2429 2430 nand_set_flash_node(chip, dn); 2431 nand_set_controller_data(chip, host); 2432#ifndef __UBOOT__ 2433 mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d", 2434 host->cs); 2435#else 2436 mtd->name = devm_kasprintf(pdev, GFP_KERNEL, "brcmnand.%d", 2437 host->cs); 2438#endif /* __UBOOT__ */ 2439 if (!mtd->name) 2440 return -ENOMEM; 2441 2442 mtd->owner = THIS_MODULE; 2443#ifndef __UBOOT__ 2444 mtd->dev.parent = &pdev->dev; 2445#else 2446 mtd->dev->parent = pdev; 2447#endif /* __UBOOT__ */ 2448 2449 chip->IO_ADDR_R = (void __iomem *)0xdeadbeef; 2450 chip->IO_ADDR_W = (void __iomem *)0xdeadbeef; 2451 2452 chip->cmd_ctrl = brcmnand_cmd_ctrl; 2453 chip->cmdfunc = brcmnand_cmdfunc; 2454 chip->waitfunc = brcmnand_waitfunc; 2455 chip->read_byte = brcmnand_read_byte; 2456 chip->read_buf = brcmnand_read_buf; 2457 chip->write_buf = brcmnand_write_buf; 2458 2459 chip->ecc.mode = NAND_ECC_HW; 2460 chip->ecc.read_page = brcmnand_read_page; 2461 chip->ecc.write_page = brcmnand_write_page; 2462 chip->ecc.read_page_raw = brcmnand_read_page_raw; 2463 chip->ecc.write_page_raw = brcmnand_write_page_raw; 2464 chip->ecc.write_oob_raw = brcmnand_write_oob_raw; 2465 chip->ecc.read_oob_raw = brcmnand_read_oob_raw; 2466 chip->ecc.read_oob = brcmnand_read_oob; 2467 chip->ecc.write_oob = brcmnand_write_oob; 2468 2469 chip->controller = &ctrl->controller; 2470 2471 /* 2472 * The bootloader might have configured 16bit mode but 2473 * NAND READID command only works in 8bit mode. We force 2474 * 8bit mode here to ensure that NAND READID commands works. 2475 */ 2476 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); 2477 nand_writereg(ctrl, cfg_offs, 2478 nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH); 2479 2480 ret = nand_scan_ident(mtd, 1, NULL); 2481 if (ret) 2482 return ret; 2483 2484 chip->options |= NAND_NO_SUBPAGE_WRITE; 2485 /* 2486 * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA 2487 * to/from, and have nand_base pass us a bounce buffer instead, as 2488 * needed. 2489 */ 2490 chip->options |= NAND_USE_BOUNCE_BUFFER; 2491 2492 if (chip->bbt_options & NAND_BBT_USE_FLASH) 2493 chip->bbt_options |= NAND_BBT_NO_OOB; 2494 2495 if (brcmnand_setup_dev(host)) 2496 return -ENXIO; 2497 2498 chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512; 2499 /* only use our internal HW threshold */ 2500 mtd->bitflip_threshold = 1; 2501 2502 chip->ecc.layout = brcmstb_choose_ecc_layout(host); 2503 if (!chip->ecc.layout) 2504 return -ENXIO; 2505 2506 ret = nand_scan_tail(mtd); 2507 if (ret) 2508 return ret; 2509 2510#ifndef __UBOOT__ 2511 ret = mtd_device_register(mtd, NULL, 0); 2512 if (ret) 2513 nand_cleanup(chip); 2514#else 2515 ret = nand_register(0, mtd); 2516#endif /* __UBOOT__ */ 2517 2518 /* If OOB is written with ECC enabled it will cause ECC errors */ 2519 if (is_hamming_ecc(host->ctrl, &host->hwcfg)) { 2520 chip->ecc.write_oob = brcmnand_write_oob_raw; 2521 chip->ecc.read_oob = brcmnand_read_oob_raw; 2522 } 2523 2524 return ret; 2525} 2526 2527#ifndef __UBOOT__ 2528static void brcmnand_save_restore_cs_config(struct brcmnand_host *host, 2529 int restore) 2530{ 2531 struct brcmnand_controller *ctrl = host->ctrl; 2532 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); 2533 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, 2534 BRCMNAND_CS_CFG_EXT); 2535 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, 2536 BRCMNAND_CS_ACC_CONTROL); 2537 u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1); 2538 u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2); 2539 2540 if (restore) { 2541 nand_writereg(ctrl, cfg_offs, host->hwcfg.config); 2542 if (cfg_offs != cfg_ext_offs) 2543 nand_writereg(ctrl, cfg_ext_offs, 2544 host->hwcfg.config_ext); 2545 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control); 2546 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1); 2547 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2); 2548 } else { 2549 host->hwcfg.config = nand_readreg(ctrl, cfg_offs); 2550 if (cfg_offs != cfg_ext_offs) 2551 host->hwcfg.config_ext = 2552 nand_readreg(ctrl, cfg_ext_offs); 2553 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs); 2554 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs); 2555 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs); 2556 } 2557} 2558 2559static int brcmnand_suspend(struct device *dev) 2560{ 2561 struct brcmnand_controller *ctrl = dev_get_drvdata(dev); 2562 struct brcmnand_host *host; 2563 2564 list_for_each_entry(host, &ctrl->host_list, node) 2565 brcmnand_save_restore_cs_config(host, 0); 2566 2567 ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT); 2568 ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR); 2569 ctrl->corr_stat_threshold = 2570 brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD); 2571 2572 if (has_flash_dma(ctrl)) 2573 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE); 2574 2575 return 0; 2576} 2577 2578static int brcmnand_resume(struct device *dev) 2579{ 2580 struct brcmnand_controller *ctrl = dev_get_drvdata(dev); 2581 struct brcmnand_host *host; 2582 2583 if (has_flash_dma(ctrl)) { 2584 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode); 2585 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0); 2586 } 2587 2588 brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select); 2589 brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor); 2590 brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD, 2591 ctrl->corr_stat_threshold); 2592 if (ctrl->soc) { 2593 /* Clear/re-enable interrupt */ 2594 ctrl->soc->ctlrdy_ack(ctrl->soc); 2595 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); 2596 } 2597 2598 list_for_each_entry(host, &ctrl->host_list, node) { 2599 struct nand_chip *chip = &host->chip; 2600 2601 brcmnand_save_restore_cs_config(host, 1); 2602 2603 /* Reset the chip, required by some chips after power-up */ 2604 nand_reset_op(chip); 2605 } 2606 2607 return 0; 2608} 2609 2610const struct dev_pm_ops brcmnand_pm_ops = { 2611 .suspend = brcmnand_suspend, 2612 .resume = brcmnand_resume, 2613}; 2614EXPORT_SYMBOL_GPL(brcmnand_pm_ops); 2615 2616static const struct of_device_id brcmnand_of_match[] = { 2617 { .compatible = "brcm,brcmnand-v2.1" }, 2618 { .compatible = "brcm,brcmnand-v2.2" }, 2619 { .compatible = "brcm,brcmnand-v4.0" }, 2620 { .compatible = "brcm,brcmnand-v5.0" }, 2621 { .compatible = "brcm,brcmnand-v6.0" }, 2622 { .compatible = "brcm,brcmnand-v6.1" }, 2623 { .compatible = "brcm,brcmnand-v6.2" }, 2624 { .compatible = "brcm,brcmnand-v7.0" }, 2625 { .compatible = "brcm,brcmnand-v7.1" }, 2626 { .compatible = "brcm,brcmnand-v7.2" }, 2627 { .compatible = "brcm,brcmnand-v7.3" }, 2628 {}, 2629}; 2630MODULE_DEVICE_TABLE(of, brcmnand_of_match); 2631#endif /* __UBOOT__ */ 2632 2633/*********************************************************************** 2634 * Platform driver setup (per controller) 2635 ***********************************************************************/ 2636 2637#ifndef __UBOOT__ 2638int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc) 2639#else 2640int brcmnand_probe(struct udevice *dev, struct brcmnand_soc *soc) 2641#endif /* __UBOOT__ */ 2642{ 2643#ifndef __UBOOT__ 2644 struct device *dev = &pdev->dev; 2645 struct device_node *dn = dev->of_node, *child; 2646#else 2647 ofnode child; 2648 struct udevice *pdev = dev; 2649#endif /* __UBOOT__ */ 2650 struct brcmnand_controller *ctrl; 2651#ifndef __UBOOT__ 2652 struct resource *res; 2653#else 2654 struct resource res; 2655#endif /* __UBOOT__ */ 2656 int ret; 2657 2658#ifndef __UBOOT__ 2659 /* We only support device-tree instantiation */ 2660 if (!dn) 2661 return -ENODEV; 2662 2663 if (!of_match_node(brcmnand_of_match, dn)) 2664 return -ENODEV; 2665#endif /* __UBOOT__ */ 2666 2667 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); 2668 if (!ctrl) 2669 return -ENOMEM; 2670 2671#ifndef __UBOOT__ 2672 dev_set_drvdata(dev, ctrl); 2673#else 2674 /* 2675 * in u-boot, the data for the driver is allocated before probing 2676 * so to keep the reference to ctrl, we store it in the variable soc 2677 */ 2678 soc->ctrl = ctrl; 2679#endif /* __UBOOT__ */ 2680 ctrl->dev = dev; 2681 2682 init_completion(&ctrl->done); 2683 init_completion(&ctrl->dma_done); 2684 nand_hw_control_init(&ctrl->controller); 2685 INIT_LIST_HEAD(&ctrl->host_list); 2686 2687 /* Is parameter page in big endian ? */ 2688 ctrl->parameter_page_big_endian = 2689 dev_read_u32_default(dev, "parameter-page-big-endian", 1); 2690 2691 /* NAND register range */ 2692#ifndef __UBOOT__ 2693 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2694 ctrl->nand_base = devm_ioremap_resource(dev, res); 2695#else 2696 dev_read_resource(pdev, 0, &res); 2697 ctrl->nand_base = devm_ioremap(pdev, res.start, resource_size(&res)); 2698#endif 2699 if (IS_ERR(ctrl->nand_base)) 2700 return PTR_ERR(ctrl->nand_base); 2701 2702 /* Enable clock before using NAND registers */ 2703 ctrl->clk = devm_clk_get(dev, "nand"); 2704 if (!IS_ERR(ctrl->clk)) { 2705 ret = clk_prepare_enable(ctrl->clk); 2706 if (ret) 2707 return ret; 2708 } else { 2709 /* Ignore PTR_ERR(ctrl->clk) */ 2710 ctrl->clk = NULL; 2711 } 2712 2713 /* Initialize NAND revision */ 2714 ret = brcmnand_revision_init(ctrl); 2715 if (ret) 2716 goto err; 2717 2718 /* 2719 * Most chips have this cache at a fixed offset within 'nand' block. 2720 * Some must specify this region separately. 2721 */ 2722#ifndef __UBOOT__ 2723 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache"); 2724 if (res) { 2725 ctrl->nand_fc = devm_ioremap_resource(dev, res); 2726 if (IS_ERR(ctrl->nand_fc)) { 2727 ret = PTR_ERR(ctrl->nand_fc); 2728 goto err; 2729 } 2730 } else { 2731 ctrl->nand_fc = ctrl->nand_base + 2732 ctrl->reg_offsets[BRCMNAND_FC_BASE]; 2733 } 2734#else 2735 if (!dev_read_resource_byname(pdev, "nand-cache", &res)) { 2736 ctrl->nand_fc = devm_ioremap(dev, res.start, 2737 resource_size(&res)); 2738 if (IS_ERR(ctrl->nand_fc)) { 2739 ret = PTR_ERR(ctrl->nand_fc); 2740 goto err; 2741 } 2742 } else { 2743 ctrl->nand_fc = ctrl->nand_base + 2744 ctrl->reg_offsets[BRCMNAND_FC_BASE]; 2745 } 2746#endif 2747 2748#ifndef __UBOOT__ 2749 /* FLASH_DMA */ 2750 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma"); 2751 if (res) { 2752 ctrl->flash_dma_base = devm_ioremap_resource(dev, res); 2753 if (IS_ERR(ctrl->flash_dma_base)) { 2754 ret = PTR_ERR(ctrl->flash_dma_base); 2755 goto err; 2756 } 2757 2758 /* initialize the dma version */ 2759 brcmnand_flash_dma_revision_init(ctrl); 2760 2761 /* linked-list and stop on error */ 2762 flash_dma_writel(ctrl, FLASH_DMA_MODE, FLASH_DMA_MODE_MASK); 2763 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0); 2764 2765 /* Allocate descriptor(s) */ 2766 ctrl->dma_desc = dmam_alloc_coherent(dev, 2767 sizeof(*ctrl->dma_desc), 2768 &ctrl->dma_pa, GFP_KERNEL); 2769 if (!ctrl->dma_desc) { 2770 ret = -ENOMEM; 2771 goto err; 2772 } 2773 2774 ctrl->dma_irq = platform_get_irq(pdev, 1); 2775 if ((int)ctrl->dma_irq < 0) { 2776 dev_err(dev, "missing FLASH_DMA IRQ\n"); 2777 ret = -ENODEV; 2778 goto err; 2779 } 2780 2781 ret = devm_request_irq(dev, ctrl->dma_irq, 2782 brcmnand_dma_irq, 0, DRV_NAME, 2783 ctrl); 2784 if (ret < 0) { 2785 dev_err(dev, "can't allocate IRQ %d: error %d\n", 2786 ctrl->dma_irq, ret); 2787 goto err; 2788 } 2789 2790 dev_info(dev, "enabling FLASH_DMA\n"); 2791 } 2792#endif /* __UBOOT__ */ 2793 2794 /* Disable automatic device ID config, direct addressing */ 2795 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, 2796 CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0); 2797 /* Disable XOR addressing */ 2798 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0); 2799 2800 /* Read the write-protect configuration in the device tree */ 2801 wp_on = dev_read_u32_default(dev, "write-protect", wp_on); 2802 2803 if (ctrl->features & BRCMNAND_HAS_WP) { 2804 /* Permanently disable write protection */ 2805 if (wp_on == 2) 2806 brcmnand_set_wp(ctrl, false); 2807 } else { 2808 wp_on = 0; 2809 } 2810 2811#ifndef __UBOOT__ 2812 /* IRQ */ 2813 ctrl->irq = platform_get_irq(pdev, 0); 2814 if ((int)ctrl->irq < 0) { 2815 dev_err(dev, "no IRQ defined\n"); 2816 ret = -ENODEV; 2817 goto err; 2818 } 2819 2820 /* 2821 * Some SoCs integrate this controller (e.g., its interrupt bits) in 2822 * interesting ways 2823 */ 2824 if (soc) { 2825 ctrl->soc = soc; 2826 2827 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0, 2828 DRV_NAME, ctrl); 2829 2830 /* Enable interrupt */ 2831 ctrl->soc->ctlrdy_ack(ctrl->soc); 2832 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); 2833 } else { 2834 /* Use standard interrupt infrastructure */ 2835 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0, 2836 DRV_NAME, ctrl); 2837 } 2838 if (ret < 0) { 2839 dev_err(dev, "can't allocate IRQ %d: error %d\n", 2840 ctrl->irq, ret); 2841 goto err; 2842 } 2843#endif /* __UBOOT__ */ 2844 2845#ifndef __UBOOT__ 2846 for_each_available_child_of_node(dn, child) { 2847 if (of_device_is_compatible(child, "brcm,nandcs")) { 2848 struct brcmnand_host *host; 2849 2850 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); 2851 if (!host) { 2852 of_node_put(child); 2853 ret = -ENOMEM; 2854 goto err; 2855 } 2856 host->pdev = pdev; 2857 host->ctrl = ctrl; 2858 2859 ret = brcmnand_init_cs(host, child); 2860 if (ret) { 2861 devm_kfree(dev, host); 2862 continue; /* Try all chip-selects */ 2863 } 2864 2865 list_add_tail(&host->node, &ctrl->host_list); 2866 } 2867 } 2868#else 2869 ofnode_for_each_subnode(child, dev_ofnode(dev)) { 2870 if (ofnode_device_is_compatible(child, "brcm,nandcs")) { 2871 struct brcmnand_host *host; 2872 2873 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); 2874 if (!host) { 2875 ret = -ENOMEM; 2876 goto err; 2877 } 2878 host->pdev = pdev; 2879 host->ctrl = ctrl; 2880 2881 ret = brcmnand_init_cs(host, child); 2882 if (ret) { 2883 devm_kfree(dev, host); 2884 continue; /* Try all chip-selects */ 2885 } 2886 2887 list_add_tail(&host->node, &ctrl->host_list); 2888 } 2889 } 2890#endif /* __UBOOT__ */ 2891 2892 /* No chip-selects could initialize properly */ 2893 if (list_empty(&ctrl->host_list)) { 2894 ret = -ENODEV; 2895 goto err; 2896 } 2897 2898 return 0; 2899 2900err: 2901#ifndef __UBOOT__ 2902 clk_disable_unprepare(ctrl->clk); 2903#else 2904 if (ctrl->clk) 2905 clk_disable(ctrl->clk); 2906#endif /* __UBOOT__ */ 2907 return ret; 2908} 2909EXPORT_SYMBOL_GPL(brcmnand_probe); 2910 2911#ifndef __UBOOT__ 2912int brcmnand_remove(struct platform_device *pdev) 2913{ 2914 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); 2915 struct brcmnand_host *host; 2916 2917 list_for_each_entry(host, &ctrl->host_list, node) 2918 nand_release(nand_to_mtd(&host->chip)); 2919 2920 clk_disable_unprepare(ctrl->clk); 2921 2922 dev_set_drvdata(&pdev->dev, NULL); 2923 2924 return 0; 2925} 2926#else 2927int brcmnand_remove(struct udevice *pdev) 2928{ 2929 return 0; 2930} 2931#endif /* __UBOOT__ */ 2932EXPORT_SYMBOL_GPL(brcmnand_remove); 2933 2934MODULE_LICENSE("GPL v2"); 2935MODULE_AUTHOR("Kevin Cernekee"); 2936MODULE_AUTHOR("Brian Norris"); 2937MODULE_DESCRIPTION("NAND driver for Broadcom chips"); 2938MODULE_ALIAS("platform:brcmnand"); 2939