1// SPDX-License-Identifier: GPL-2.0 2/* 3 * drivers/mtd/nand/raw/pxa3xx_nand.c 4 * 5 * Copyright �� 2005 Intel Corporation 6 * Copyright �� 2006 Marvell International Ltd. 7 */ 8 9#include <common.h> 10#include <malloc.h> 11#include <fdtdec.h> 12#include <nand.h> 13#include <asm/global_data.h> 14#include <dm/device_compat.h> 15#include <dm/devres.h> 16#include <linux/bitops.h> 17#include <linux/bug.h> 18#include <linux/delay.h> 19#include <linux/err.h> 20#include <linux/errno.h> 21#include <asm/io.h> 22#include <asm/arch/cpu.h> 23#include <linux/mtd/mtd.h> 24#include <linux/mtd/rawnand.h> 25#include <linux/printk.h> 26#include <linux/types.h> 27#include <syscon.h> 28#include <regmap.h> 29#include <dm/uclass.h> 30#include <dm/read.h> 31 32#include "pxa3xx_nand.h" 33 34DECLARE_GLOBAL_DATA_PTR; 35 36#define TIMEOUT_DRAIN_FIFO 5 /* in ms */ 37#define CHIP_DELAY_TIMEOUT 200 38#define NAND_STOP_DELAY 40 39 40/* 41 * Define a buffer size for the initial command that detects the flash device: 42 * STATUS, READID and PARAM. 43 * ONFI param page is 256 bytes, and there are three redundant copies 44 * to be read. JEDEC param page is 512 bytes, and there are also three 45 * redundant copies to be read. 46 * Hence this buffer should be at least 512 x 3. Let's pick 2048. 47 */ 48#define INIT_BUFFER_SIZE 2048 49 50/* registers and bit definitions */ 51#define NDCR (0x00) /* Control register */ 52#define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */ 53#define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */ 54#define NDSR (0x14) /* Status Register */ 55#define NDPCR (0x18) /* Page Count Register */ 56#define NDBDR0 (0x1C) /* Bad Block Register 0 */ 57#define NDBDR1 (0x20) /* Bad Block Register 1 */ 58#define NDECCCTRL (0x28) /* ECC control */ 59#define NDDB (0x40) /* Data Buffer */ 60#define NDCB0 (0x48) /* Command Buffer0 */ 61#define NDCB1 (0x4C) /* Command Buffer1 */ 62#define NDCB2 (0x50) /* Command Buffer2 */ 63 64#define NDCR_SPARE_EN (0x1 << 31) 65#define NDCR_ECC_EN (0x1 << 30) 66#define NDCR_DMA_EN (0x1 << 29) 67#define NDCR_ND_RUN (0x1 << 28) 68#define NDCR_DWIDTH_C (0x1 << 27) 69#define NDCR_DWIDTH_M (0x1 << 26) 70#define NDCR_PAGE_SZ (0x1 << 24) 71#define NDCR_NCSX (0x1 << 23) 72#define NDCR_ND_MODE (0x3 << 21) 73#define NDCR_NAND_MODE (0x0) 74#define NDCR_CLR_PG_CNT (0x1 << 20) 75#define NFCV1_NDCR_ARB_CNTL (0x1 << 19) 76#define NDCR_RD_ID_CNT_MASK (0x7 << 16) 77#define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK) 78 79#define NDCR_RA_START (0x1 << 15) 80#define NDCR_PG_PER_BLK (0x1 << 14) 81#define NDCR_ND_ARB_EN (0x1 << 12) 82#define NDCR_INT_MASK (0xFFF) 83 84#define NDSR_MASK (0xfff) 85#define NDSR_ERR_CNT_OFF (16) 86#define NDSR_ERR_CNT_MASK (0x1f) 87#define NDSR_ERR_CNT(sr) ((sr >> NDSR_ERR_CNT_OFF) & NDSR_ERR_CNT_MASK) 88#define NDSR_RDY (0x1 << 12) 89#define NDSR_FLASH_RDY (0x1 << 11) 90#define NDSR_CS0_PAGED (0x1 << 10) 91#define NDSR_CS1_PAGED (0x1 << 9) 92#define NDSR_CS0_CMDD (0x1 << 8) 93#define NDSR_CS1_CMDD (0x1 << 7) 94#define NDSR_CS0_BBD (0x1 << 6) 95#define NDSR_CS1_BBD (0x1 << 5) 96#define NDSR_UNCORERR (0x1 << 4) 97#define NDSR_CORERR (0x1 << 3) 98#define NDSR_WRDREQ (0x1 << 2) 99#define NDSR_RDDREQ (0x1 << 1) 100#define NDSR_WRCMDREQ (0x1) 101 102#define NDCB0_LEN_OVRD (0x1 << 28) 103#define NDCB0_ST_ROW_EN (0x1 << 26) 104#define NDCB0_AUTO_RS (0x1 << 25) 105#define NDCB0_CSEL (0x1 << 24) 106#define NDCB0_EXT_CMD_TYPE_MASK (0x7 << 29) 107#define NDCB0_EXT_CMD_TYPE(x) (((x) << 29) & NDCB0_EXT_CMD_TYPE_MASK) 108#define NDCB0_CMD_TYPE_MASK (0x7 << 21) 109#define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK) 110#define NDCB0_NC (0x1 << 20) 111#define NDCB0_DBC (0x1 << 19) 112#define NDCB0_ADDR_CYC_MASK (0x7 << 16) 113#define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK) 114#define NDCB0_CMD2_MASK (0xff << 8) 115#define NDCB0_CMD1_MASK (0xff) 116#define NDCB0_ADDR_CYC_SHIFT (16) 117 118#define EXT_CMD_TYPE_DISPATCH 6 /* Command dispatch */ 119#define EXT_CMD_TYPE_NAKED_RW 5 /* Naked read or Naked write */ 120#define EXT_CMD_TYPE_READ 4 /* Read */ 121#define EXT_CMD_TYPE_DISP_WR 4 /* Command dispatch with write */ 122#define EXT_CMD_TYPE_FINAL 3 /* Final command */ 123#define EXT_CMD_TYPE_LAST_RW 1 /* Last naked read/write */ 124#define EXT_CMD_TYPE_MONO 0 /* Monolithic read/write */ 125 126/* System control register and bit to enable NAND on some SoCs */ 127#define GENCONF_SOC_DEVICE_MUX 0x208 128#define GENCONF_SOC_DEVICE_MUX_NFC_EN BIT(0) 129#define GENCONF_SOC_DEVICE_MUX_NFC_DEVBUS_ARB_EN BIT(27) 130 131/* 132 * This should be large enough to read 'ONFI' and 'JEDEC'. 133 * Let's use 7 bytes, which is the maximum ID count supported 134 * by the controller (see NDCR_RD_ID_CNT_MASK). 135 */ 136#define READ_ID_BYTES 7 137 138/* macros for registers read/write */ 139#define nand_writel(info, off, val) \ 140 writel((val), (info)->mmio_base + (off)) 141 142#define nand_readl(info, off) \ 143 readl((info)->mmio_base + (off)) 144 145/* error code and state */ 146enum { 147 ERR_NONE = 0, 148 ERR_DMABUSERR = -1, 149 ERR_SENDCMD = -2, 150 ERR_UNCORERR = -3, 151 ERR_BBERR = -4, 152 ERR_CORERR = -5, 153}; 154 155enum { 156 STATE_IDLE = 0, 157 STATE_PREPARED, 158 STATE_CMD_HANDLE, 159 STATE_DMA_READING, 160 STATE_DMA_WRITING, 161 STATE_DMA_DONE, 162 STATE_PIO_READING, 163 STATE_PIO_WRITING, 164 STATE_CMD_DONE, 165 STATE_READY, 166}; 167 168enum pxa3xx_nand_variant { 169 PXA3XX_NAND_VARIANT_PXA, 170 PXA3XX_NAND_VARIANT_ARMADA370, 171 PXA3XX_NAND_VARIANT_ARMADA_8K, 172 PXA3XX_NAND_VARIANT_AC5, 173}; 174 175struct pxa3xx_nand_host { 176 struct nand_chip chip; 177 void *info_data; 178 179 /* page size of attached chip */ 180 int use_ecc; 181 int cs; 182 183 /* calculated from pxa3xx_nand_flash data */ 184 unsigned int col_addr_cycles; 185 unsigned int row_addr_cycles; 186}; 187 188struct pxa3xx_nand_info { 189 struct nand_hw_control controller; 190 struct pxa3xx_nand_platform_data *pdata; 191 192 struct clk *clk; 193 void __iomem *mmio_base; 194 unsigned long mmio_phys; 195 int cmd_complete, dev_ready; 196 197 unsigned int buf_start; 198 unsigned int buf_count; 199 unsigned int buf_size; 200 unsigned int data_buff_pos; 201 unsigned int oob_buff_pos; 202 203 unsigned char *data_buff; 204 unsigned char *oob_buff; 205 206 struct pxa3xx_nand_host *host[NUM_CHIP_SELECT]; 207 unsigned int state; 208 209 /* 210 * This driver supports NFCv1 (as found in PXA SoC) 211 * and NFCv2 (as found in Armada 370/XP SoC). 212 */ 213 enum pxa3xx_nand_variant variant; 214 215 int cs; 216 int use_ecc; /* use HW ECC ? */ 217 int force_raw; /* prevent use_ecc to be set */ 218 int ecc_bch; /* using BCH ECC? */ 219 int use_spare; /* use spare ? */ 220 int need_wait; 221 222 /* Amount of real data per full chunk */ 223 unsigned int chunk_size; 224 225 /* Amount of spare data per full chunk */ 226 unsigned int spare_size; 227 228 /* Number of full chunks (i.e chunk_size + spare_size) */ 229 unsigned int nfullchunks; 230 231 /* 232 * Total number of chunks. If equal to nfullchunks, then there 233 * are only full chunks. Otherwise, there is one last chunk of 234 * size (last_chunk_size + last_spare_size) 235 */ 236 unsigned int ntotalchunks; 237 238 /* Amount of real data in the last chunk */ 239 unsigned int last_chunk_size; 240 241 /* Amount of spare data in the last chunk */ 242 unsigned int last_spare_size; 243 244 unsigned int ecc_size; 245 unsigned int ecc_err_cnt; 246 unsigned int max_bitflips; 247 int retcode; 248 249 /* 250 * Variables only valid during command 251 * execution. step_chunk_size and step_spare_size is the 252 * amount of real data and spare data in the current 253 * chunk. cur_chunk is the current chunk being 254 * read/programmed. 255 */ 256 unsigned int step_chunk_size; 257 unsigned int step_spare_size; 258 unsigned int cur_chunk; 259 260 /* cached register value */ 261 uint32_t reg_ndcr; 262 uint32_t ndtr0cs0; 263 uint32_t ndtr1cs0; 264 265 /* generated NDCBx register values */ 266 uint32_t ndcb0; 267 uint32_t ndcb1; 268 uint32_t ndcb2; 269 uint32_t ndcb3; 270}; 271 272static struct pxa3xx_nand_timing timing[] = { 273 /* 274 * tCH Enable signal hold time 275 * tCS Enable signal setup time 276 * tWH ND_nWE high duration 277 * tWP ND_nWE pulse time 278 * tRH ND_nRE high duration 279 * tRP ND_nRE pulse width 280 * tR ND_nWE high to ND_nRE low for read 281 * tWHR ND_nWE high to ND_nRE low for status read 282 * tAR ND_ALE low to ND_nRE low delay 283 */ 284 /*ch cs wh wp rh rp r whr ar */ 285 { 40, 80, 60, 100, 80, 100, 90000, 400, 40, }, 286 { 10, 0, 20, 40, 30, 40, 11123, 110, 10, }, 287 { 10, 25, 15, 25, 15, 30, 25000, 60, 10, }, 288 { 10, 35, 15, 25, 15, 25, 25000, 60, 10, }, 289 { 5, 20, 10, 12, 10, 12, 25000, 60, 10, }, 290}; 291 292static struct pxa3xx_nand_flash builtin_flash_types[] = { 293 /* 294 * chip_id 295 * flash_width Width of Flash memory (DWIDTH_M) 296 * dfc_width Width of flash controller(DWIDTH_C) 297 * *timing 298 * http://www.linux-mtd.infradead.org/nand-data/nanddata.html 299 */ 300 { 0x46ec, 16, 16, &timing[1] }, 301 { 0xdaec, 8, 8, &timing[1] }, 302 { 0xd7ec, 8, 8, &timing[1] }, 303 { 0xa12c, 8, 8, &timing[2] }, 304 { 0xb12c, 16, 16, &timing[2] }, 305 { 0xdc2c, 8, 8, &timing[2] }, 306 { 0xcc2c, 16, 16, &timing[2] }, 307 { 0xba20, 16, 16, &timing[3] }, 308 { 0xda98, 8, 8, &timing[4] }, 309}; 310 311#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT 312static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' }; 313static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' }; 314 315static struct nand_bbt_descr bbt_main_descr = { 316 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE 317 | NAND_BBT_2BIT | NAND_BBT_VERSION, 318 .offs = 8, 319 .len = 6, 320 .veroffs = 14, 321 .maxblocks = 8, /* Last 8 blocks in each chip */ 322 .pattern = bbt_pattern 323}; 324 325static struct nand_bbt_descr bbt_mirror_descr = { 326 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE 327 | NAND_BBT_2BIT | NAND_BBT_VERSION, 328 .offs = 8, 329 .len = 6, 330 .veroffs = 14, 331 .maxblocks = 8, /* Last 8 blocks in each chip */ 332 .pattern = bbt_mirror_pattern 333}; 334#endif 335 336struct marvell_hw_ecc_layout { 337 int page_size; 338 int strength; 339 unsigned int ecc_size; 340 unsigned int nfullchunks; 341 unsigned int chunk_size; 342 unsigned int spare_size; 343 unsigned int last_chunk_size; 344 unsigned int last_spare_size; 345}; 346 347static const struct marvell_hw_ecc_layout nfc_layouts[] = { 348 /* page_size strength ecc_size nfullchunks chunk_size spare_size last_chunk last_spare */ 349 { 512, 1, 8, 1, 512, 8, 0, 0 }, 350 { 2048, 1, 24, 1, 2048, 40, 0, 0 }, 351 352 { 2048, 4, 32, 1, 2048, 32, 0, 0 }, 353 { 2048, 8, 32, 1, 1024, 0, 1024, 32 }, 354 { 2048, 12, 32, 2, 704, 0, 640, 0 }, 355 { 2048, 16, 32, 4, 512, 0, 0, 32 }, 356 { 4096, 4, 32, 2, 2048, 32, 0, 0 }, 357 { 4096, 8, 32, 4, 1024, 0, 0, 64 }, 358 { 4096, 12, 32, 5, 704, 0, 576, 32 }, 359 { 4096, 16, 32, 8, 512, 0, 0, 32 }, 360 361 { 8192, 4, 32, 4, 2048, 32, 0, 0 }, 362 { 8192, 8, 32, 8, 1024, 0, 0, 160 }, 363 { 8192, 12, 32, 11, 704, 0, 448, 64 }, 364 { 8192, 16, 32, 16, 512, 0, 0, 32 }, 365 { }, 366}; 367 368static struct nand_ecclayout ecc_layout_empty = { 369 .eccbytes = 0, 370 .eccpos = { }, 371 .oobfree = { } 372}; 373 374#define NDTR0_tCH(c) (min((c), 7) << 19) 375#define NDTR0_tCS(c) (min((c), 7) << 16) 376#define NDTR0_tWH(c) (min((c), 7) << 11) 377#define NDTR0_tWP(c) (min((c), 7) << 8) 378#define NDTR0_tRH(c) (min((c), 7) << 3) 379#define NDTR0_tRP(c) (min((c), 7) << 0) 380 381#define NDTR1_tR(c) (min((c), 65535) << 16) 382#define NDTR1_tWHR(c) (min((c), 15) << 4) 383#define NDTR1_tAR(c) (min((c), 15) << 0) 384 385/* convert nano-seconds to nand flash controller clock cycles */ 386#define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000) 387 388static const struct udevice_id pxa3xx_nand_dt_ids[] = { 389 { 390 .compatible = "marvell,armada370-nand-controller", 391 .data = PXA3XX_NAND_VARIANT_ARMADA370, 392 }, 393 { 394 .compatible = "marvell,armada-8k-nand-controller", 395 .data = PXA3XX_NAND_VARIANT_ARMADA_8K, 396 }, 397 { 398 .compatible = "marvell,mvebu-ac5-pxa3xx-nand", 399 .data = PXA3XX_NAND_VARIANT_AC5, 400 }, 401 {} 402}; 403 404static enum pxa3xx_nand_variant pxa3xx_nand_get_variant(struct udevice *dev) 405{ 406 return dev_get_driver_data(dev); 407} 408 409static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host, 410 const struct pxa3xx_nand_timing *t) 411{ 412 struct pxa3xx_nand_info *info = host->info_data; 413 unsigned long nand_clk = mvebu_get_nand_clock(); 414 uint32_t ndtr0, ndtr1; 415 416 ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) | 417 NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) | 418 NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) | 419 NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) | 420 NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) | 421 NDTR0_tRP(ns2cycle(t->tRP, nand_clk)); 422 423 ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) | 424 NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) | 425 NDTR1_tAR(ns2cycle(t->tAR, nand_clk)); 426 427 info->ndtr0cs0 = ndtr0; 428 info->ndtr1cs0 = ndtr1; 429 nand_writel(info, NDTR0CS0, ndtr0); 430 nand_writel(info, NDTR1CS0, ndtr1); 431} 432 433static void pxa3xx_nand_set_sdr_timing(struct pxa3xx_nand_host *host, 434 const struct nand_sdr_timings *t) 435{ 436 struct pxa3xx_nand_info *info = host->info_data; 437 struct nand_chip *chip = &host->chip; 438 unsigned long nand_clk = mvebu_get_nand_clock(); 439 uint32_t ndtr0, ndtr1; 440 441 u32 tCH_min = DIV_ROUND_UP(t->tCH_min, 1000); 442 u32 tCS_min = DIV_ROUND_UP(t->tCS_min, 1000); 443 u32 tWH_min = DIV_ROUND_UP(t->tWH_min, 1000); 444 u32 tWP_min = DIV_ROUND_UP(t->tWC_min - t->tWH_min, 1000); 445 u32 tREH_min = DIV_ROUND_UP(t->tREH_min, 1000); 446 u32 tRP_min = DIV_ROUND_UP(t->tRC_min - t->tREH_min, 1000); 447 u32 tR = chip->chip_delay * 1000; 448 u32 tWHR_min = DIV_ROUND_UP(t->tWHR_min, 1000); 449 u32 tAR_min = DIV_ROUND_UP(t->tAR_min, 1000); 450 451 /* fallback to a default value if tR = 0 */ 452 if (!tR) 453 tR = 20000; 454 455 ndtr0 = NDTR0_tCH(ns2cycle(tCH_min, nand_clk)) | 456 NDTR0_tCS(ns2cycle(tCS_min, nand_clk)) | 457 NDTR0_tWH(ns2cycle(tWH_min, nand_clk)) | 458 NDTR0_tWP(ns2cycle(tWP_min, nand_clk)) | 459 NDTR0_tRH(ns2cycle(tREH_min, nand_clk)) | 460 NDTR0_tRP(ns2cycle(tRP_min, nand_clk)); 461 462 ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) | 463 NDTR1_tWHR(ns2cycle(tWHR_min, nand_clk)) | 464 NDTR1_tAR(ns2cycle(tAR_min, nand_clk)); 465 466 info->ndtr0cs0 = ndtr0; 467 info->ndtr1cs0 = ndtr1; 468 nand_writel(info, NDTR0CS0, ndtr0); 469 nand_writel(info, NDTR1CS0, ndtr1); 470} 471 472static int pxa3xx_nand_init_timings(struct pxa3xx_nand_host *host) 473{ 474 const struct nand_sdr_timings *timings; 475 struct nand_chip *chip = &host->chip; 476 struct pxa3xx_nand_info *info = host->info_data; 477 const struct pxa3xx_nand_flash *f = NULL; 478 struct mtd_info *mtd = nand_to_mtd(&host->chip); 479 int mode, id, ntypes, i; 480 481 mode = onfi_get_async_timing_mode(chip); 482 if (mode == ONFI_TIMING_MODE_UNKNOWN) { 483 ntypes = ARRAY_SIZE(builtin_flash_types); 484 485 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); 486 487 id = chip->read_byte(mtd); 488 id |= chip->read_byte(mtd) << 0x8; 489 490 for (i = 0; i < ntypes; i++) { 491 f = &builtin_flash_types[i]; 492 493 if (f->chip_id == id) 494 break; 495 } 496 497 if (i == ntypes) { 498 dev_err(mtd->dev, "Error: timings not found\n"); 499 return -EINVAL; 500 } 501 502 pxa3xx_nand_set_timing(host, f->timing); 503 504 if (f->flash_width == 16) { 505 info->reg_ndcr |= NDCR_DWIDTH_M; 506 chip->options |= NAND_BUSWIDTH_16; 507 } 508 509 info->reg_ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0; 510 } else { 511 mode = fls(mode) - 1; 512 if (mode < 0) 513 mode = 0; 514 515 if (info->variant == PXA3XX_NAND_VARIANT_AC5) 516 mode = min(mode, 3); 517 518 timings = onfi_async_timing_mode_to_sdr_timings(mode); 519 if (IS_ERR(timings)) 520 return PTR_ERR(timings); 521 522 pxa3xx_nand_set_sdr_timing(host, timings); 523 } 524 525 return 0; 526} 527 528/** 529 * NOTE: it is a must to set ND_RUN first, then write 530 * command buffer, otherwise, it does not work. 531 * We enable all the interrupt at the same time, and 532 * let pxa3xx_nand_irq to handle all logic. 533 */ 534static void pxa3xx_nand_start(struct pxa3xx_nand_info *info) 535{ 536 uint32_t ndcr; 537 538 ndcr = info->reg_ndcr; 539 540 if (info->use_ecc) { 541 ndcr |= NDCR_ECC_EN; 542 if (info->ecc_bch) 543 nand_writel(info, NDECCCTRL, 0x1); 544 } else { 545 ndcr &= ~NDCR_ECC_EN; 546 if (info->ecc_bch) 547 nand_writel(info, NDECCCTRL, 0x0); 548 } 549 550 ndcr &= ~NDCR_DMA_EN; 551 552 if (info->use_spare) 553 ndcr |= NDCR_SPARE_EN; 554 else 555 ndcr &= ~NDCR_SPARE_EN; 556 557 ndcr |= NDCR_ND_RUN; 558 559 /* clear status bits and run */ 560 nand_writel(info, NDSR, NDSR_MASK); 561 nand_writel(info, NDCR, 0); 562 nand_writel(info, NDCR, ndcr); 563} 564 565static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask) 566{ 567 uint32_t ndcr; 568 569 ndcr = nand_readl(info, NDCR); 570 nand_writel(info, NDCR, ndcr | int_mask); 571} 572 573static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len) 574{ 575 if (info->ecc_bch && !info->force_raw) { 576 u32 ts; 577 578 /* 579 * According to the datasheet, when reading from NDDB 580 * with BCH enabled, after each 32 bytes reads, we 581 * have to make sure that the NDSR.RDDREQ bit is set. 582 * 583 * Drain the FIFO 8 32 bits reads at a time, and skip 584 * the polling on the last read. 585 */ 586 while (len > 8) { 587 readsl(info->mmio_base + NDDB, data, 8); 588 589 ts = get_timer(0); 590 while (!(nand_readl(info, NDSR) & NDSR_RDDREQ)) { 591 if (get_timer(ts) > TIMEOUT_DRAIN_FIFO) { 592 dev_err(info->controller.active->mtd.dev, 593 "Timeout on RDDREQ while draining the FIFO\n"); 594 return; 595 } 596 } 597 598 data += 32; 599 len -= 8; 600 } 601 } 602 603 readsl(info->mmio_base + NDDB, data, len); 604} 605 606static void handle_data_pio(struct pxa3xx_nand_info *info) 607{ 608 int data_len = info->step_chunk_size; 609 610 /* 611 * In raw mode, include the spare area and the ECC bytes that are not 612 * consumed by the controller in the data section. Do not reorganize 613 * here, do it in the ->read_page_raw() handler instead. 614 */ 615 if (info->force_raw) 616 data_len += info->step_spare_size + info->ecc_size; 617 618 switch (info->state) { 619 case STATE_PIO_WRITING: 620 if (info->step_chunk_size) 621 writesl(info->mmio_base + NDDB, 622 info->data_buff + info->data_buff_pos, 623 DIV_ROUND_UP(data_len, 4)); 624 625 if (info->step_spare_size) 626 writesl(info->mmio_base + NDDB, 627 info->oob_buff + info->oob_buff_pos, 628 DIV_ROUND_UP(info->step_spare_size, 4)); 629 break; 630 case STATE_PIO_READING: 631 if (data_len) 632 drain_fifo(info, 633 info->data_buff + info->data_buff_pos, 634 DIV_ROUND_UP(data_len, 4)); 635 636 if (info->force_raw) 637 break; 638 639 if (info->step_spare_size) 640 drain_fifo(info, 641 info->oob_buff + info->oob_buff_pos, 642 DIV_ROUND_UP(info->step_spare_size, 4)); 643 break; 644 default: 645 dev_err(info->controller.active->mtd.dev, 646 "%s: invalid state %d\n", __func__, info->state); 647 BUG(); 648 } 649 650 /* Update buffer pointers for multi-page read/write */ 651 info->data_buff_pos += data_len; 652 info->oob_buff_pos += info->step_spare_size; 653} 654 655static void pxa3xx_nand_irq_thread(struct pxa3xx_nand_info *info) 656{ 657 handle_data_pio(info); 658 659 info->state = STATE_CMD_DONE; 660 nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ); 661} 662 663static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info) 664{ 665 unsigned int status, is_completed = 0, is_ready = 0; 666 unsigned int ready, cmd_done; 667 irqreturn_t ret = IRQ_HANDLED; 668 669 if (info->cs == 0) { 670 ready = NDSR_FLASH_RDY; 671 cmd_done = NDSR_CS0_CMDD; 672 } else { 673 ready = NDSR_RDY; 674 cmd_done = NDSR_CS1_CMDD; 675 } 676 677 /* TODO - find out why we need the delay during write operation. */ 678 ndelay(1); 679 680 status = nand_readl(info, NDSR); 681 682 if (status & NDSR_UNCORERR) 683 info->retcode = ERR_UNCORERR; 684 if (status & NDSR_CORERR) { 685 info->retcode = ERR_CORERR; 686 if ((info->variant == PXA3XX_NAND_VARIANT_ARMADA370 || 687 info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) && 688 info->ecc_bch) 689 info->ecc_err_cnt = NDSR_ERR_CNT(status); 690 else 691 info->ecc_err_cnt = 1; 692 693 /* 694 * Each chunk composing a page is corrected independently, 695 * and we need to store maximum number of corrected bitflips 696 * to return it to the MTD layer in ecc.read_page(). 697 */ 698 info->max_bitflips = max_t(unsigned int, 699 info->max_bitflips, 700 info->ecc_err_cnt); 701 } 702 if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) { 703 info->state = (status & NDSR_RDDREQ) ? 704 STATE_PIO_READING : STATE_PIO_WRITING; 705 /* Call the IRQ thread in U-Boot directly */ 706 pxa3xx_nand_irq_thread(info); 707 return 0; 708 } 709 if (status & cmd_done) { 710 info->state = STATE_CMD_DONE; 711 is_completed = 1; 712 } 713 if (status & ready) { 714 info->state = STATE_READY; 715 is_ready = 1; 716 } 717 718 /* 719 * Clear all status bit before issuing the next command, which 720 * can and will alter the status bits and will deserve a new 721 * interrupt on its own. This lets the controller exit the IRQ 722 */ 723 nand_writel(info, NDSR, status); 724 725 if (status & NDSR_WRCMDREQ) { 726 status &= ~NDSR_WRCMDREQ; 727 info->state = STATE_CMD_HANDLE; 728 729 /* 730 * Command buffer registers NDCB{0-2} (and optionally NDCB3) 731 * must be loaded by writing directly either 12 or 16 732 * bytes directly to NDCB0, four bytes at a time. 733 * 734 * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored 735 * but each NDCBx register can be read. 736 */ 737 nand_writel(info, NDCB0, info->ndcb0); 738 nand_writel(info, NDCB0, info->ndcb1); 739 nand_writel(info, NDCB0, info->ndcb2); 740 741 /* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */ 742 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 || 743 info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K || 744 info->variant == PXA3XX_NAND_VARIANT_AC5) 745 nand_writel(info, NDCB0, info->ndcb3); 746 } 747 748 if (is_completed) 749 info->cmd_complete = 1; 750 if (is_ready) 751 info->dev_ready = 1; 752 753 return ret; 754} 755 756static inline int is_buf_blank(uint8_t *buf, size_t len) 757{ 758 for (; len > 0; len--) 759 if (*buf++ != 0xff) 760 return 0; 761 return 1; 762} 763 764static void set_command_address(struct pxa3xx_nand_info *info, 765 unsigned int page_size, uint16_t column, int page_addr) 766{ 767 /* small page addr setting */ 768 if (page_size < info->chunk_size) { 769 info->ndcb1 = ((page_addr & 0xFFFFFF) << 8) 770 | (column & 0xFF); 771 772 info->ndcb2 = 0; 773 } else { 774 info->ndcb1 = ((page_addr & 0xFFFF) << 16) 775 | (column & 0xFFFF); 776 777 if (page_addr & 0xFF0000) 778 info->ndcb2 = (page_addr & 0xFF0000) >> 16; 779 else 780 info->ndcb2 = 0; 781 } 782} 783 784static void prepare_start_command(struct pxa3xx_nand_info *info, int command) 785{ 786 struct pxa3xx_nand_host *host = info->host[info->cs]; 787 struct mtd_info *mtd = nand_to_mtd(&host->chip); 788 789 /* reset data and oob column point to handle data */ 790 info->buf_start = 0; 791 info->buf_count = 0; 792 info->data_buff_pos = 0; 793 info->oob_buff_pos = 0; 794 info->step_chunk_size = 0; 795 info->step_spare_size = 0; 796 info->cur_chunk = 0; 797 info->use_ecc = 0; 798 info->use_spare = 1; 799 info->retcode = ERR_NONE; 800 info->ecc_err_cnt = 0; 801 info->ndcb3 = 0; 802 info->need_wait = 0; 803 804 switch (command) { 805 case NAND_CMD_READ0: 806 case NAND_CMD_READOOB: 807 case NAND_CMD_PAGEPROG: 808 if (!info->force_raw) 809 info->use_ecc = 1; 810 break; 811 case NAND_CMD_PARAM: 812 info->use_spare = 0; 813 break; 814 default: 815 info->ndcb1 = 0; 816 info->ndcb2 = 0; 817 break; 818 } 819 820 /* 821 * If we are about to issue a read command, or about to set 822 * the write address, then clean the data buffer. 823 */ 824 if (command == NAND_CMD_READ0 || 825 command == NAND_CMD_READOOB || 826 command == NAND_CMD_SEQIN) { 827 info->buf_count = mtd->writesize + mtd->oobsize; 828 memset(info->data_buff, 0xFF, info->buf_count); 829 } 830} 831 832static int prepare_set_command(struct pxa3xx_nand_info *info, int command, 833 int ext_cmd_type, uint16_t column, int page_addr) 834{ 835 int addr_cycle, exec_cmd; 836 struct pxa3xx_nand_host *host; 837 struct mtd_info *mtd; 838 839 host = info->host[info->cs]; 840 mtd = nand_to_mtd(&host->chip); 841 addr_cycle = 0; 842 exec_cmd = 1; 843 844 if (info->cs != 0) 845 info->ndcb0 = NDCB0_CSEL; 846 else 847 info->ndcb0 = 0; 848 849 if (command == NAND_CMD_SEQIN) 850 exec_cmd = 0; 851 852 addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles 853 + host->col_addr_cycles); 854 855 switch (command) { 856 case NAND_CMD_READOOB: 857 case NAND_CMD_READ0: 858 info->buf_start = column; 859 info->ndcb0 |= NDCB0_CMD_TYPE(0) 860 | addr_cycle 861 | NAND_CMD_READ0; 862 863 if (command == NAND_CMD_READOOB) 864 info->buf_start += mtd->writesize; 865 866 if (info->cur_chunk < info->nfullchunks) { 867 info->step_chunk_size = info->chunk_size; 868 info->step_spare_size = info->spare_size; 869 } else { 870 info->step_chunk_size = info->last_chunk_size; 871 info->step_spare_size = info->last_spare_size; 872 } 873 874 /* 875 * Multiple page read needs an 'extended command type' field, 876 * which is either naked-read or last-read according to the 877 * state. 878 */ 879 if (info->force_raw) { 880 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8) | 881 NDCB0_LEN_OVRD | 882 NDCB0_EXT_CMD_TYPE(ext_cmd_type); 883 info->ndcb3 = info->step_chunk_size + 884 info->step_spare_size + info->ecc_size; 885 } else if (mtd->writesize == info->chunk_size) { 886 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8); 887 } else if (mtd->writesize > info->chunk_size) { 888 info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8) 889 | NDCB0_LEN_OVRD 890 | NDCB0_EXT_CMD_TYPE(ext_cmd_type); 891 info->ndcb3 = info->step_chunk_size + 892 info->step_spare_size; 893 } 894 895 set_command_address(info, mtd->writesize, column, page_addr); 896 break; 897 898 case NAND_CMD_SEQIN: 899 900 info->buf_start = column; 901 set_command_address(info, mtd->writesize, 0, page_addr); 902 903 /* 904 * Multiple page programming needs to execute the initial 905 * SEQIN command that sets the page address. 906 */ 907 if (mtd->writesize > info->chunk_size) { 908 info->ndcb0 |= NDCB0_CMD_TYPE(0x1) 909 | NDCB0_EXT_CMD_TYPE(ext_cmd_type) 910 | addr_cycle 911 | command; 912 exec_cmd = 1; 913 } 914 break; 915 916 case NAND_CMD_PAGEPROG: 917 if (is_buf_blank(info->data_buff, 918 (mtd->writesize + mtd->oobsize))) { 919 exec_cmd = 0; 920 break; 921 } 922 923 if (info->cur_chunk < info->nfullchunks) { 924 info->step_chunk_size = info->chunk_size; 925 info->step_spare_size = info->spare_size; 926 } else { 927 info->step_chunk_size = info->last_chunk_size; 928 info->step_spare_size = info->last_spare_size; 929 } 930 931 /* Second command setting for large pages */ 932 if (mtd->writesize > info->chunk_size) { 933 /* 934 * Multiple page write uses the 'extended command' 935 * field. This can be used to issue a command dispatch 936 * or a naked-write depending on the current stage. 937 */ 938 info->ndcb0 |= NDCB0_CMD_TYPE(0x1) 939 | NDCB0_LEN_OVRD 940 | NDCB0_EXT_CMD_TYPE(ext_cmd_type); 941 info->ndcb3 = info->step_chunk_size + 942 info->step_spare_size; 943 944 /* 945 * This is the command dispatch that completes a chunked 946 * page program operation. 947 */ 948 if (info->cur_chunk == info->ntotalchunks) { 949 info->ndcb0 = NDCB0_CMD_TYPE(0x1) 950 | NDCB0_EXT_CMD_TYPE(ext_cmd_type) 951 | command; 952 info->ndcb1 = 0; 953 info->ndcb2 = 0; 954 info->ndcb3 = 0; 955 } 956 } else { 957 info->ndcb0 |= NDCB0_CMD_TYPE(0x1) 958 | NDCB0_AUTO_RS 959 | NDCB0_ST_ROW_EN 960 | NDCB0_DBC 961 | (NAND_CMD_PAGEPROG << 8) 962 | NAND_CMD_SEQIN 963 | addr_cycle; 964 } 965 break; 966 967 case NAND_CMD_PARAM: 968 info->buf_count = INIT_BUFFER_SIZE; 969 info->ndcb0 |= NDCB0_CMD_TYPE(0) 970 | NDCB0_ADDR_CYC(1) 971 | NDCB0_LEN_OVRD 972 | command; 973 info->ndcb1 = (column & 0xFF); 974 info->ndcb3 = INIT_BUFFER_SIZE; 975 info->step_chunk_size = INIT_BUFFER_SIZE; 976 break; 977 978 case NAND_CMD_READID: 979 info->buf_count = READ_ID_BYTES; 980 info->ndcb0 |= NDCB0_CMD_TYPE(3) 981 | NDCB0_ADDR_CYC(1) 982 | command; 983 info->ndcb1 = (column & 0xFF); 984 985 info->step_chunk_size = 8; 986 break; 987 case NAND_CMD_STATUS: 988 info->buf_count = 1; 989 info->ndcb0 |= NDCB0_CMD_TYPE(4) 990 | NDCB0_ADDR_CYC(1) 991 | command; 992 993 info->step_chunk_size = 8; 994 break; 995 996 case NAND_CMD_ERASE1: 997 info->ndcb0 |= NDCB0_CMD_TYPE(2) 998 | NDCB0_AUTO_RS 999 | NDCB0_ADDR_CYC(3) 1000 | NDCB0_DBC 1001 | (NAND_CMD_ERASE2 << 8) 1002 | NAND_CMD_ERASE1; 1003 info->ndcb1 = page_addr; 1004 info->ndcb2 = 0; 1005 1006 break; 1007 case NAND_CMD_RESET: 1008 info->ndcb0 |= NDCB0_CMD_TYPE(5) 1009 | command; 1010 1011 break; 1012 1013 case NAND_CMD_ERASE2: 1014 exec_cmd = 0; 1015 break; 1016 1017 default: 1018 exec_cmd = 0; 1019 dev_err(mtd->dev, "non-supported command %x\n", 1020 command); 1021 break; 1022 } 1023 1024 return exec_cmd; 1025} 1026 1027static void nand_cmdfunc(struct mtd_info *mtd, unsigned command, 1028 int column, int page_addr) 1029{ 1030 struct nand_chip *chip = mtd_to_nand(mtd); 1031 struct pxa3xx_nand_host *host = nand_get_controller_data(chip); 1032 struct pxa3xx_nand_info *info = host->info_data; 1033 int exec_cmd; 1034 1035 /* 1036 * if this is a x16 device ,then convert the input 1037 * "byte" address into a "word" address appropriate 1038 * for indexing a word-oriented device 1039 */ 1040 if (info->reg_ndcr & NDCR_DWIDTH_M) 1041 column /= 2; 1042 1043 /* 1044 * There may be different NAND chip hooked to 1045 * different chip select, so check whether 1046 * chip select has been changed, if yes, reset the timing 1047 */ 1048 if (info->cs != host->cs) { 1049 info->cs = host->cs; 1050 nand_writel(info, NDTR0CS0, info->ndtr0cs0); 1051 nand_writel(info, NDTR1CS0, info->ndtr1cs0); 1052 } 1053 1054 prepare_start_command(info, command); 1055 1056 info->state = STATE_PREPARED; 1057 exec_cmd = prepare_set_command(info, command, 0, column, page_addr); 1058 1059 if (exec_cmd) { 1060 u32 ts; 1061 1062 info->cmd_complete = 0; 1063 info->dev_ready = 0; 1064 info->need_wait = 1; 1065 pxa3xx_nand_start(info); 1066 1067 ts = get_timer(0); 1068 while (1) { 1069 u32 status; 1070 1071 status = nand_readl(info, NDSR); 1072 if (status) 1073 pxa3xx_nand_irq(info); 1074 1075 if (info->cmd_complete) 1076 break; 1077 1078 if (get_timer(ts) > CHIP_DELAY_TIMEOUT) { 1079 dev_err(mtd->dev, "Wait timeout!!!\n"); 1080 return; 1081 } 1082 } 1083 } 1084 info->state = STATE_IDLE; 1085} 1086 1087static void nand_cmdfunc_extended(struct mtd_info *mtd, 1088 const unsigned command, 1089 int column, int page_addr) 1090{ 1091 struct nand_chip *chip = mtd_to_nand(mtd); 1092 struct pxa3xx_nand_host *host = nand_get_controller_data(chip); 1093 struct pxa3xx_nand_info *info = host->info_data; 1094 int exec_cmd, ext_cmd_type; 1095 1096 /* 1097 * if this is a x16 device then convert the input 1098 * "byte" address into a "word" address appropriate 1099 * for indexing a word-oriented device 1100 */ 1101 if (info->reg_ndcr & NDCR_DWIDTH_M) 1102 column /= 2; 1103 1104 /* 1105 * There may be different NAND chip hooked to 1106 * different chip select, so check whether 1107 * chip select has been changed, if yes, reset the timing 1108 */ 1109 if (info->cs != host->cs) { 1110 info->cs = host->cs; 1111 nand_writel(info, NDTR0CS0, info->ndtr0cs0); 1112 nand_writel(info, NDTR1CS0, info->ndtr1cs0); 1113 } 1114 1115 /* Select the extended command for the first command */ 1116 switch (command) { 1117 case NAND_CMD_READ0: 1118 case NAND_CMD_READOOB: 1119 ext_cmd_type = EXT_CMD_TYPE_MONO; 1120 break; 1121 case NAND_CMD_SEQIN: 1122 ext_cmd_type = EXT_CMD_TYPE_DISPATCH; 1123 break; 1124 case NAND_CMD_PAGEPROG: 1125 ext_cmd_type = EXT_CMD_TYPE_NAKED_RW; 1126 break; 1127 default: 1128 ext_cmd_type = 0; 1129 break; 1130 } 1131 1132 prepare_start_command(info, command); 1133 1134 /* 1135 * Prepare the "is ready" completion before starting a command 1136 * transaction sequence. If the command is not executed the 1137 * completion will be completed, see below. 1138 * 1139 * We can do that inside the loop because the command variable 1140 * is invariant and thus so is the exec_cmd. 1141 */ 1142 info->need_wait = 1; 1143 info->dev_ready = 0; 1144 1145 do { 1146 u32 ts; 1147 1148 info->state = STATE_PREPARED; 1149 exec_cmd = prepare_set_command(info, command, ext_cmd_type, 1150 column, page_addr); 1151 if (!exec_cmd) { 1152 info->need_wait = 0; 1153 info->dev_ready = 1; 1154 break; 1155 } 1156 1157 info->cmd_complete = 0; 1158 pxa3xx_nand_start(info); 1159 1160 ts = get_timer(0); 1161 while (1) { 1162 u32 status; 1163 1164 status = nand_readl(info, NDSR); 1165 if (status) 1166 pxa3xx_nand_irq(info); 1167 1168 if (info->cmd_complete) 1169 break; 1170 1171 if (get_timer(ts) > CHIP_DELAY_TIMEOUT) { 1172 dev_err(mtd->dev, "Wait timeout!!!\n"); 1173 return; 1174 } 1175 } 1176 1177 /* Only a few commands need several steps */ 1178 if (command != NAND_CMD_PAGEPROG && 1179 command != NAND_CMD_READ0 && 1180 command != NAND_CMD_READOOB) 1181 break; 1182 1183 info->cur_chunk++; 1184 1185 /* Check if the sequence is complete */ 1186 if (info->cur_chunk == info->ntotalchunks && 1187 command != NAND_CMD_PAGEPROG) 1188 break; 1189 1190 /* 1191 * After a splitted program command sequence has issued 1192 * the command dispatch, the command sequence is complete. 1193 */ 1194 if (info->cur_chunk == (info->ntotalchunks + 1) && 1195 command == NAND_CMD_PAGEPROG && 1196 ext_cmd_type == EXT_CMD_TYPE_DISPATCH) 1197 break; 1198 1199 if (command == NAND_CMD_READ0 || command == NAND_CMD_READOOB) { 1200 /* Last read: issue a 'last naked read' */ 1201 if (info->cur_chunk == info->ntotalchunks - 1) 1202 ext_cmd_type = EXT_CMD_TYPE_LAST_RW; 1203 else 1204 ext_cmd_type = EXT_CMD_TYPE_NAKED_RW; 1205 1206 /* 1207 * If a splitted program command has no more data to transfer, 1208 * the command dispatch must be issued to complete. 1209 */ 1210 } else if (command == NAND_CMD_PAGEPROG && 1211 info->cur_chunk == info->ntotalchunks) { 1212 ext_cmd_type = EXT_CMD_TYPE_DISPATCH; 1213 } 1214 } while (1); 1215 1216 info->state = STATE_IDLE; 1217} 1218 1219static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd, 1220 struct nand_chip *chip, const uint8_t *buf, int oob_required, 1221 int page) 1222{ 1223 chip->write_buf(mtd, buf, mtd->writesize); 1224 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize); 1225 1226 return 0; 1227} 1228 1229static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd, 1230 struct nand_chip *chip, uint8_t *buf, int oob_required, 1231 int page) 1232{ 1233 struct pxa3xx_nand_host *host = nand_get_controller_data(chip); 1234 struct pxa3xx_nand_info *info = host->info_data; 1235 int bf; 1236 1237 chip->read_buf(mtd, buf, mtd->writesize); 1238 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 1239 1240 if (info->retcode == ERR_CORERR && info->use_ecc) { 1241 mtd->ecc_stats.corrected += info->ecc_err_cnt; 1242 1243 } else if (info->retcode == ERR_UNCORERR && info->ecc_bch) { 1244 /* 1245 * Empty pages will trigger uncorrectable errors. Re-read the 1246 * entire page in raw mode and check for bits not being "1". 1247 * If there are more than the supported strength, then it means 1248 * this is an actual uncorrectable error. 1249 */ 1250 chip->ecc.read_page_raw(mtd, chip, buf, oob_required, page); 1251 bf = nand_check_erased_ecc_chunk(buf, mtd->writesize, 1252 chip->oob_poi, mtd->oobsize, 1253 NULL, 0, chip->ecc.strength); 1254 if (bf < 0) { 1255 mtd->ecc_stats.failed++; 1256 } else if (bf) { 1257 mtd->ecc_stats.corrected += bf; 1258 info->max_bitflips = max_t(unsigned int, 1259 info->max_bitflips, bf); 1260 info->retcode = ERR_CORERR; 1261 } else { 1262 info->retcode = ERR_NONE; 1263 } 1264 1265 } else if (info->retcode == ERR_UNCORERR && !info->ecc_bch) { 1266 /* Raw read is not supported with Hamming ECC engine */ 1267 if (is_buf_blank(buf, mtd->writesize)) 1268 info->retcode = ERR_NONE; 1269 else 1270 mtd->ecc_stats.failed++; 1271 } 1272 1273 return info->max_bitflips; 1274} 1275 1276static int pxa3xx_nand_read_page_raw(struct mtd_info *mtd, 1277 struct nand_chip *chip, uint8_t *buf, 1278 int oob_required, int page) 1279{ 1280 struct pxa3xx_nand_host *host = chip->priv; 1281 struct pxa3xx_nand_info *info = host->info_data; 1282 int chunk, ecc_off_buf; 1283 1284 if (!info->ecc_bch) 1285 return -ENOTSUPP; 1286 1287 /* 1288 * Set the force_raw boolean, then re-call ->cmdfunc() that will run 1289 * pxa3xx_nand_start(), which will actually disable the ECC engine. 1290 */ 1291 info->force_raw = true; 1292 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); 1293 1294 ecc_off_buf = (info->nfullchunks * info->spare_size) + 1295 info->last_spare_size; 1296 for (chunk = 0; chunk < info->nfullchunks; chunk++) { 1297 chip->read_buf(mtd, 1298 buf + (chunk * info->chunk_size), 1299 info->chunk_size); 1300 chip->read_buf(mtd, 1301 chip->oob_poi + 1302 (chunk * (info->spare_size)), 1303 info->spare_size); 1304 chip->read_buf(mtd, 1305 chip->oob_poi + ecc_off_buf + 1306 (chunk * (info->ecc_size)), 1307 info->ecc_size - 2); 1308 } 1309 1310 if (info->ntotalchunks > info->nfullchunks) { 1311 chip->read_buf(mtd, 1312 buf + (info->nfullchunks * info->chunk_size), 1313 info->last_chunk_size); 1314 chip->read_buf(mtd, 1315 chip->oob_poi + 1316 (info->nfullchunks * (info->spare_size)), 1317 info->last_spare_size); 1318 chip->read_buf(mtd, 1319 chip->oob_poi + ecc_off_buf + 1320 (info->nfullchunks * (info->ecc_size)), 1321 info->ecc_size - 2); 1322 } 1323 1324 info->force_raw = false; 1325 1326 return 0; 1327} 1328 1329static int pxa3xx_nand_read_oob_raw(struct mtd_info *mtd, 1330 struct nand_chip *chip, int page) 1331{ 1332 /* Invalidate page cache */ 1333 chip->pagebuf = -1; 1334 1335 return chip->ecc.read_page_raw(mtd, chip, chip->buffers->databuf, true, 1336 page); 1337} 1338 1339static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd) 1340{ 1341 struct nand_chip *chip = mtd_to_nand(mtd); 1342 struct pxa3xx_nand_host *host = nand_get_controller_data(chip); 1343 struct pxa3xx_nand_info *info = host->info_data; 1344 char retval = 0xFF; 1345 1346 if (info->buf_start < info->buf_count) 1347 /* Has just send a new command? */ 1348 retval = info->data_buff[info->buf_start++]; 1349 1350 return retval; 1351} 1352 1353static u16 pxa3xx_nand_read_word(struct mtd_info *mtd) 1354{ 1355 struct nand_chip *chip = mtd_to_nand(mtd); 1356 struct pxa3xx_nand_host *host = nand_get_controller_data(chip); 1357 struct pxa3xx_nand_info *info = host->info_data; 1358 u16 retval = 0xFFFF; 1359 1360 if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) { 1361 retval = *((u16 *)(info->data_buff+info->buf_start)); 1362 info->buf_start += 2; 1363 } 1364 return retval; 1365} 1366 1367static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) 1368{ 1369 struct nand_chip *chip = mtd_to_nand(mtd); 1370 struct pxa3xx_nand_host *host = nand_get_controller_data(chip); 1371 struct pxa3xx_nand_info *info = host->info_data; 1372 int real_len = min_t(size_t, len, info->buf_count - info->buf_start); 1373 1374 memcpy(buf, info->data_buff + info->buf_start, real_len); 1375 info->buf_start += real_len; 1376} 1377 1378static void pxa3xx_nand_write_buf(struct mtd_info *mtd, 1379 const uint8_t *buf, int len) 1380{ 1381 struct nand_chip *chip = mtd_to_nand(mtd); 1382 struct pxa3xx_nand_host *host = nand_get_controller_data(chip); 1383 struct pxa3xx_nand_info *info = host->info_data; 1384 int real_len = min_t(size_t, len, info->buf_count - info->buf_start); 1385 1386 memcpy(info->data_buff + info->buf_start, buf, real_len); 1387 info->buf_start += real_len; 1388} 1389 1390static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip) 1391{ 1392 return; 1393} 1394 1395static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this) 1396{ 1397 struct nand_chip *chip = mtd_to_nand(mtd); 1398 struct pxa3xx_nand_host *host = nand_get_controller_data(chip); 1399 struct pxa3xx_nand_info *info = host->info_data; 1400 1401 if (info->need_wait) { 1402 u32 ts; 1403 1404 info->need_wait = 0; 1405 1406 ts = get_timer(0); 1407 while (1) { 1408 u32 status; 1409 1410 status = nand_readl(info, NDSR); 1411 if (status) 1412 pxa3xx_nand_irq(info); 1413 1414 if (info->dev_ready) 1415 break; 1416 1417 if (get_timer(ts) > CHIP_DELAY_TIMEOUT) { 1418 dev_err(mtd->dev, "Ready timeout!!!\n"); 1419 return NAND_STATUS_FAIL; 1420 } 1421 } 1422 } 1423 1424 /* pxa3xx_nand_send_command has waited for command complete */ 1425 if (this->state == FL_WRITING || this->state == FL_ERASING) { 1426 if (info->retcode == ERR_NONE) 1427 return 0; 1428 else 1429 return NAND_STATUS_FAIL; 1430 } 1431 1432 return NAND_STATUS_READY; 1433} 1434 1435static int pxa3xx_nand_config_ident(struct pxa3xx_nand_info *info) 1436{ 1437 struct pxa3xx_nand_platform_data *pdata = info->pdata; 1438 1439 /* Configure default flash values */ 1440 info->reg_ndcr = 0x0; /* enable all interrupts */ 1441 info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; 1442 info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES); 1443 info->reg_ndcr |= NDCR_SPARE_EN; 1444 1445 return 0; 1446} 1447 1448static void pxa3xx_nand_config_tail(struct pxa3xx_nand_info *info) 1449{ 1450 struct pxa3xx_nand_host *host = info->host[info->cs]; 1451 struct mtd_info *mtd = nand_to_mtd(&info->host[info->cs]->chip); 1452 struct nand_chip *chip = mtd_to_nand(mtd); 1453 1454 info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0; 1455 info->reg_ndcr |= (chip->page_shift == 6) ? NDCR_PG_PER_BLK : 0; 1456 info->reg_ndcr |= (mtd->writesize == 2048) ? NDCR_PAGE_SZ : 0; 1457} 1458 1459static void pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info) 1460{ 1461 struct pxa3xx_nand_platform_data *pdata = info->pdata; 1462 uint32_t ndcr = nand_readl(info, NDCR); 1463 1464 /* Set an initial chunk size */ 1465 info->chunk_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512; 1466 info->reg_ndcr = ndcr & 1467 ~(NDCR_INT_MASK | NDCR_ND_ARB_EN | NFCV1_NDCR_ARB_CNTL); 1468 info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; 1469 info->ndtr0cs0 = nand_readl(info, NDTR0CS0); 1470 info->ndtr1cs0 = nand_readl(info, NDTR1CS0); 1471} 1472 1473static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info) 1474{ 1475 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL); 1476 if (info->data_buff == NULL) 1477 return -ENOMEM; 1478 return 0; 1479} 1480 1481static int pxa3xx_nand_sensing(struct pxa3xx_nand_host *host) 1482{ 1483 struct pxa3xx_nand_info *info = host->info_data; 1484 struct pxa3xx_nand_platform_data *pdata = info->pdata; 1485 struct mtd_info *mtd; 1486 struct nand_chip *chip; 1487 const struct nand_sdr_timings *timings; 1488 int ret; 1489 1490 mtd = nand_to_mtd(&info->host[info->cs]->chip); 1491 chip = mtd_to_nand(mtd); 1492 1493 /* configure default flash values */ 1494 info->reg_ndcr = 0x0; /* enable all interrupts */ 1495 info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0; 1496 info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES); 1497 info->reg_ndcr |= NDCR_SPARE_EN; /* enable spare by default */ 1498 1499 /* use the common timing to make a try */ 1500 timings = onfi_async_timing_mode_to_sdr_timings(0); 1501 if (IS_ERR(timings)) 1502 return PTR_ERR(timings); 1503 1504 pxa3xx_nand_set_sdr_timing(host, timings); 1505 1506 chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0); 1507 ret = chip->waitfunc(mtd, chip); 1508 if (ret & NAND_STATUS_FAIL) 1509 return -ENODEV; 1510 1511 return 0; 1512} 1513 1514static int pxa_ecc_init(struct pxa3xx_nand_info *info, 1515 struct nand_ecc_ctrl *ecc, 1516 int strength, int ecc_stepsize, int page_size) 1517{ 1518 int i = 0; 1519 1520 /* if ecc strength is 1 ecc algo is Hamming else bch */ 1521 info->ecc_bch = (strength == 1) ? 0 : 1; 1522 1523 ecc->mode = NAND_ECC_HW; 1524 1525 /* ecc->layout is not in use for pxa driver (but shouldn't be NULL)*/ 1526 if (info->ecc_bch == 1) 1527 ecc->layout = &ecc_layout_empty; 1528 1529 /* for bch actual ecc strength is 16 per chunk */ 1530 ecc->strength = (info->ecc_bch == 1) ? 16 : 1; 1531 1532 while (nfc_layouts[i].strength) { 1533 if (strength == nfc_layouts[i].strength && page_size == nfc_layouts[i].page_size) { 1534 info->nfullchunks = nfc_layouts[i].nfullchunks; 1535 info->chunk_size = nfc_layouts[i].chunk_size; 1536 info->spare_size = nfc_layouts[i].spare_size; 1537 info->last_chunk_size = nfc_layouts[i].last_chunk_size; 1538 info->last_spare_size = nfc_layouts[i].last_spare_size; 1539 info->ntotalchunks = (info->last_spare_size || info->last_chunk_size) ? 1540 info->nfullchunks + 1 : info->nfullchunks; 1541 info->ecc_size = nfc_layouts[i].ecc_size; 1542 break; 1543 } 1544 ++i; 1545 } 1546 1547 /* for bch the ecc is calculated per chunk size and for Hamming it is 512 */ 1548 ecc->size = (info->ecc_bch) ? info->chunk_size : 512; 1549 1550 /* nand_scan_tail func perform validity tests for ECC strength, and it 1551 * assumes that all chunks are with same size. in our case when ecc is 12 1552 * the chunk size is 704 but the last chunk is with different size so 1553 * we cheat it nand_scan_tail validity tests by set info->ecc_size value to 512 1554 */ 1555 if (strength == 12) 1556 ecc->size = 512; 1557 1558 if (ecc_stepsize != 512 || !(nfc_layouts[i].strength)) { 1559 dev_err(info->controller.active->mtd.dev, 1560 "ECC strength %d at page size %d is not supported\n", 1561 strength, page_size); 1562 return -ENODEV; 1563 } 1564 1565 return 0; 1566} 1567 1568static int pxa3xx_nand_scan(struct mtd_info *mtd) 1569{ 1570 struct nand_chip *chip = mtd_to_nand(mtd); 1571 struct pxa3xx_nand_host *host = nand_get_controller_data(chip); 1572 struct pxa3xx_nand_info *info = host->info_data; 1573 struct pxa3xx_nand_platform_data *pdata = info->pdata; 1574 int ret; 1575 uint16_t ecc_strength, ecc_step; 1576 1577 if (pdata->keep_config) { 1578 pxa3xx_nand_detect_config(info); 1579 } else { 1580 ret = pxa3xx_nand_config_ident(info); 1581 if (ret) 1582 return ret; 1583 ret = pxa3xx_nand_sensing(host); 1584 if (ret) { 1585 dev_info(mtd->dev, "There is no chip on cs %d!\n", 1586 info->cs); 1587 return ret; 1588 } 1589 } 1590 1591 /* Device detection must be done with ECC disabled */ 1592 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 || 1593 info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K || 1594 info->variant == PXA3XX_NAND_VARIANT_AC5) 1595 nand_writel(info, NDECCCTRL, 0x0); 1596 1597 if (nand_scan_ident(mtd, 1, NULL)) 1598 return -ENODEV; 1599 1600 if (!pdata->keep_config) { 1601 ret = pxa3xx_nand_init_timings(host); 1602 if (ret) { 1603 dev_err(mtd->dev, 1604 "Failed to set timings: %d\n", ret); 1605 return ret; 1606 } 1607 } 1608 1609#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT 1610 /* 1611 * We'll use a bad block table stored in-flash and don't 1612 * allow writing the bad block marker to the flash. 1613 */ 1614 chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB_BBM; 1615 chip->bbt_td = &bbt_main_descr; 1616 chip->bbt_md = &bbt_mirror_descr; 1617#endif 1618 1619 if (pdata->ecc_strength && pdata->ecc_step_size) { 1620 ecc_strength = pdata->ecc_strength; 1621 ecc_step = pdata->ecc_step_size; 1622 } else { 1623 ecc_strength = chip->ecc_strength_ds; 1624 ecc_step = chip->ecc_step_ds; 1625 } 1626 1627 /* Set default ECC strength requirements on non-ONFI devices */ 1628 if (ecc_strength < 1 && ecc_step < 1) { 1629 ecc_strength = 1; 1630 ecc_step = 512; 1631 } 1632 1633 ret = pxa_ecc_init(info, &chip->ecc, ecc_strength, 1634 ecc_step, mtd->writesize); 1635 if (ret) 1636 return ret; 1637 1638 /* 1639 * If the page size is bigger than the FIFO size, let's check 1640 * we are given the right variant and then switch to the extended 1641 * (aka split) command handling, 1642 */ 1643 if (mtd->writesize > info->chunk_size) { 1644 if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 || 1645 info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K || 1646 info->variant == PXA3XX_NAND_VARIANT_AC5) { 1647 chip->cmdfunc = nand_cmdfunc_extended; 1648 } else { 1649 dev_err(mtd->dev, 1650 "unsupported page size on this variant\n"); 1651 return -ENODEV; 1652 } 1653 } 1654 1655 /* calculate addressing information */ 1656 if (mtd->writesize >= 2048) 1657 host->col_addr_cycles = 2; 1658 else 1659 host->col_addr_cycles = 1; 1660 1661 /* release the initial buffer */ 1662 kfree(info->data_buff); 1663 1664 /* allocate the real data + oob buffer */ 1665 info->buf_size = mtd->writesize + mtd->oobsize; 1666 ret = pxa3xx_nand_init_buff(info); 1667 if (ret) 1668 return ret; 1669 info->oob_buff = info->data_buff + mtd->writesize; 1670 1671 if ((mtd->size >> chip->page_shift) > 65536) 1672 host->row_addr_cycles = 3; 1673 else 1674 host->row_addr_cycles = 2; 1675 1676 if (!pdata->keep_config) 1677 pxa3xx_nand_config_tail(info); 1678 1679 return nand_scan_tail(mtd); 1680} 1681 1682static int alloc_nand_resource(struct udevice *dev, struct pxa3xx_nand_info *info) 1683{ 1684 struct pxa3xx_nand_platform_data *pdata; 1685 struct pxa3xx_nand_host *host; 1686 struct nand_chip *chip = NULL; 1687 struct mtd_info *mtd; 1688 int cs; 1689 1690 pdata = info->pdata; 1691 if (pdata->num_cs <= 0) 1692 return -ENODEV; 1693 1694 info->variant = pxa3xx_nand_get_variant(dev); 1695 for (cs = 0; cs < pdata->num_cs; cs++) { 1696 chip = (struct nand_chip *) 1697 ((u8 *)&info[1] + sizeof(*host) * cs); 1698 mtd = nand_to_mtd(chip); 1699 host = (struct pxa3xx_nand_host *)chip; 1700 info->host[cs] = host; 1701 host->cs = cs; 1702 host->info_data = info; 1703 mtd->owner = THIS_MODULE; 1704 1705 nand_set_controller_data(chip, host); 1706 chip->ecc.read_page = pxa3xx_nand_read_page_hwecc; 1707 chip->ecc.read_page_raw = pxa3xx_nand_read_page_raw; 1708 chip->ecc.read_oob_raw = pxa3xx_nand_read_oob_raw; 1709 chip->ecc.write_page = pxa3xx_nand_write_page_hwecc; 1710 chip->controller = &info->controller; 1711 chip->waitfunc = pxa3xx_nand_waitfunc; 1712 chip->select_chip = pxa3xx_nand_select_chip; 1713 chip->read_word = pxa3xx_nand_read_word; 1714 chip->read_byte = pxa3xx_nand_read_byte; 1715 chip->read_buf = pxa3xx_nand_read_buf; 1716 chip->write_buf = pxa3xx_nand_write_buf; 1717 chip->options |= NAND_NO_SUBPAGE_WRITE; 1718 chip->cmdfunc = nand_cmdfunc; 1719 } 1720 1721 /* Allocate a buffer to allow flash detection */ 1722 info->buf_size = INIT_BUFFER_SIZE; 1723 info->data_buff = kmalloc(info->buf_size, GFP_KERNEL); 1724 if (info->data_buff == NULL) 1725 return -ENOMEM; 1726 1727 /* initialize all interrupts to be disabled */ 1728 disable_int(info, NDSR_MASK); 1729 1730 /* 1731 * Some SoCs like A7k/A8k need to enable manually the NAND 1732 * controller to avoid being bootloader dependent. This is done 1733 * through the use of a single bit in the System Functions registers. 1734 */ 1735 if (pxa3xx_nand_get_variant(dev) == PXA3XX_NAND_VARIANT_ARMADA_8K) { 1736 struct regmap *sysctrl_base = syscon_regmap_lookup_by_phandle( 1737 dev, "marvell,system-controller"); 1738 u32 reg; 1739 1740 if (IS_ERR(sysctrl_base)) 1741 return PTR_ERR(sysctrl_base); 1742 1743 regmap_read(sysctrl_base, GENCONF_SOC_DEVICE_MUX, ®); 1744 reg |= GENCONF_SOC_DEVICE_MUX_NFC_EN | GENCONF_SOC_DEVICE_MUX_NFC_DEVBUS_ARB_EN; 1745 regmap_write(sysctrl_base, GENCONF_SOC_DEVICE_MUX, reg); 1746 } 1747 1748 return 0; 1749} 1750 1751static int pxa3xx_nand_probe_dt(struct udevice *dev, struct pxa3xx_nand_info *info) 1752{ 1753 struct pxa3xx_nand_platform_data *pdata; 1754 1755 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); 1756 if (!pdata) 1757 return -ENOMEM; 1758 1759 info->mmio_base = dev_read_addr_ptr(dev); 1760 1761 pdata->num_cs = dev_read_u32_default(dev, "num-cs", 1); 1762 if (pdata->num_cs != 1) { 1763 pr_err("pxa3xx driver supports single CS only\n"); 1764 return -EINVAL; 1765 } 1766 1767 if (dev_read_bool(dev, "marvell,nand-enable-arbiter")) 1768 pdata->enable_arbiter = 1; 1769 1770 if (dev_read_bool(dev, "marvell,nand-keep-config")) 1771 pdata->keep_config = 1; 1772 1773 /* 1774 * ECC parameters. 1775 * If these are not set, they will be selected according 1776 * to the detected flash type. 1777 */ 1778 /* ECC strength */ 1779 pdata->ecc_strength = dev_read_u32_default(dev, "nand-ecc-strength", 0); 1780 1781 /* ECC step size */ 1782 pdata->ecc_step_size = dev_read_u32_default(dev, "nand-ecc-step-size", 1783 0); 1784 1785 info->pdata = pdata; 1786 1787 return 0; 1788} 1789 1790static int pxa3xx_nand_probe(struct udevice *dev) 1791{ 1792 struct pxa3xx_nand_platform_data *pdata; 1793 int ret, cs, probe_success; 1794 struct pxa3xx_nand_info *info = dev_get_priv(dev); 1795 1796 ret = pxa3xx_nand_probe_dt(dev, info); 1797 if (ret) 1798 return ret; 1799 1800 pdata = info->pdata; 1801 1802 ret = alloc_nand_resource(dev, info); 1803 if (ret) { 1804 dev_err(dev, "alloc nand resource failed\n"); 1805 return ret; 1806 } 1807 1808 probe_success = 0; 1809 for (cs = 0; cs < pdata->num_cs; cs++) { 1810 struct mtd_info *mtd = nand_to_mtd(&info->host[cs]->chip); 1811 1812 /* 1813 * The mtd name matches the one used in 'mtdparts' kernel 1814 * parameter. This name cannot be changed or otherwise 1815 * user's mtd partitions configuration would get broken. 1816 */ 1817 mtd->name = "pxa3xx_nand-0"; 1818 mtd->dev = dev; 1819 info->cs = cs; 1820 ret = pxa3xx_nand_scan(mtd); 1821 if (ret) { 1822 dev_info(mtd->dev, "failed to scan nand at cs %d\n", 1823 cs); 1824 continue; 1825 } 1826 1827 if (nand_register(cs, mtd)) 1828 continue; 1829 1830 probe_success = 1; 1831 } 1832 1833 if (!probe_success) 1834 return -ENODEV; 1835 1836 return 0; 1837} 1838 1839U_BOOT_DRIVER(pxa3xx_nand) = { 1840 .name = "pxa3xx-nand", 1841 .id = UCLASS_MTD, 1842 .of_match = pxa3xx_nand_dt_ids, 1843 .probe = pxa3xx_nand_probe, 1844 .priv_auto = sizeof(struct pxa3xx_nand_info) + 1845 sizeof(struct pxa3xx_nand_host) * CONFIG_SYS_MAX_NAND_DEVICE, 1846}; 1847 1848void board_nand_init(void) 1849{ 1850 struct udevice *dev; 1851 int ret; 1852 1853 ret = uclass_get_device_by_driver(UCLASS_MTD, 1854 DM_DRIVER_GET(pxa3xx_nand), &dev); 1855 if (ret && ret != -ENODEV) { 1856 pr_err("Failed to initialize %s. (error %d)\n", dev->name, 1857 ret); 1858 } 1859} 1860