1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Rockchip NAND Flash controller driver. 4 * Copyright (C) 2021 Rockchip Inc. 5 * Author: Yifeng Zhao <yifeng.zhao@rock-chips.com> 6 */ 7 8#include <common.h> 9#include <asm/io.h> 10#include <clk.h> 11#include <dm.h> 12#include <dm/device_compat.h> 13#include <dm/devres.h> 14#include <fdtdec.h> 15#include <inttypes.h> 16#include <linux/delay.h> 17#include <linux/dma-direction.h> 18#include <linux/dma-mapping.h> 19#include <linux/io.h> 20#include <linux/kernel.h> 21#include <linux/mtd/mtd.h> 22#include <linux/mtd/nand.h> 23#include <linux/mtd/partitions.h> 24#include <linux/mtd/rawnand.h> 25#include <memalign.h> 26#include <nand.h> 27 28/* 29 * NFC Page Data Layout: 30 * 1024 bytes data + 4Bytes sys data + 28Bytes~124Bytes ECC data + 31 * 1024 bytes data + 4Bytes sys data + 28Bytes~124Bytes ECC data + 32 * ...... 33 * NAND Page Data Layout: 34 * 1024 * n data + m Bytes oob 35 * Original Bad Block Mask Location: 36 * First byte of oob(spare). 37 * nand_chip->oob_poi data layout: 38 * 4Bytes sys data + .... + 4Bytes sys data + ECC data. 39 */ 40 41/* NAND controller register definition */ 42#define NFC_READ (0) 43#define NFC_WRITE (1) 44 45#define NFC_FMCTL (0x00) 46#define FMCTL_CE_SEL_M 0xFF 47#define FMCTL_CE_SEL(x) (1 << (x)) 48#define FMCTL_WP BIT(8) 49#define FMCTL_RDY BIT(9) 50 51#define NFC_FMWAIT (0x04) 52#define FLCTL_RST BIT(0) 53#define FLCTL_WR (1) /* 0: read, 1: write */ 54#define FLCTL_XFER_ST BIT(2) 55#define FLCTL_XFER_EN BIT(3) 56#define FLCTL_ACORRECT BIT(10) /* Auto correct error bits. */ 57#define FLCTL_XFER_READY BIT(20) 58#define FLCTL_XFER_SECTOR (22) 59#define FLCTL_TOG_FIX BIT(29) 60 61#define BCHCTL_BANK_M (7 << 5) 62#define BCHCTL_BANK (5) 63 64#define DMA_ST BIT(0) 65#define DMA_WR (1) /* 0: write, 1: read */ 66#define DMA_EN BIT(2) 67#define DMA_AHB_SIZE (3) /* 0: 1, 1: 2, 2: 4 */ 68#define DMA_BURST_SIZE (6) /* 0: 1, 3: 4, 5: 8, 7: 16 */ 69#define DMA_INC_NUM (9) /* 1 - 16 */ 70 71#define ECC_ERR_CNT(x, e) ((((x) >> (e).low) & (e).low_mask) |\ 72 (((x) >> (e).high) & (e).high_mask) << (e).low_bn) 73#define INT_DMA BIT(0) 74#define NFC_BANK (0x800) 75#define NFC_BANK_STEP (0x100) 76#define BANK_DATA (0x00) 77#define BANK_ADDR (0x04) 78#define BANK_CMD (0x08) 79#define NFC_SRAM0 (0x1000) 80#define NFC_SRAM1 (0x1400) 81#define NFC_SRAM_SIZE (0x400) 82#define NFC_TIMEOUT_MS (500) 83#define NFC_MAX_OOB_PER_STEP 128 84#define NFC_MIN_OOB_PER_STEP 64 85#define MAX_DATA_SIZE 0xFFFC 86#define MAX_ADDRESS_CYC 6 87#define NFC_ECC_MAX_MODES 4 88#define NFC_RB_DELAY_US 50 89#define NFC_MAX_PAGE_SIZE (16 * 1024) 90#define NFC_MAX_OOB_SIZE (16 * 128) 91#define NFC_MAX_NSELS (8) /* Some Socs only have 1 or 2 CSs. */ 92#define NFC_SYS_DATA_SIZE (4) /* 4 bytes sys data in oob pre 1024 data.*/ 93#define RK_DEFAULT_CLOCK_RATE (150 * 1000 * 1000) /* 150 Mhz */ 94#define ACCTIMING(csrw, rwpw, rwcs) ((csrw) << 12 | (rwpw) << 5 | (rwcs)) 95 96enum nfc_type { 97 NFC_V6, 98 NFC_V8, 99 NFC_V9, 100}; 101 102/** 103 * struct rk_ecc_cnt_status: represent a ecc status data. 104 * @err_flag_bit: error flag bit index at register. 105 * @low: ECC count low bit index at register. 106 * @low_mask: mask bit. 107 * @low_bn: ECC count low bit number. 108 * @high: ECC count high bit index at register. 109 * @high_mask: mask bit 110 */ 111struct ecc_cnt_status { 112 u8 err_flag_bit; 113 u8 low; 114 u8 low_mask; 115 u8 low_bn; 116 u8 high; 117 u8 high_mask; 118}; 119 120/** 121 * @type: NFC version 122 * @ecc_strengths: ECC strengths 123 * @ecc_cfgs: ECC config values 124 * @flctl_off: FLCTL register offset 125 * @bchctl_off: BCHCTL register offset 126 * @dma_data_buf_off: DMA_DATA_BUF register offset 127 * @dma_oob_buf_off: DMA_OOB_BUF register offset 128 * @dma_cfg_off: DMA_CFG register offset 129 * @dma_st_off: DMA_ST register offset 130 * @bch_st_off: BCG_ST register offset 131 * @randmz_off: RANDMZ register offset 132 * @int_en_off: interrupt enable register offset 133 * @int_clr_off: interrupt clean register offset 134 * @int_st_off: interrupt status register offset 135 * @oob0_off: oob0 register offset 136 * @oob1_off: oob1 register offset 137 * @ecc0: represent ECC0 status data 138 * @ecc1: represent ECC1 status data 139 */ 140struct nfc_cfg { 141 enum nfc_type type; 142 u8 ecc_strengths[NFC_ECC_MAX_MODES]; 143 u32 ecc_cfgs[NFC_ECC_MAX_MODES]; 144 u32 flctl_off; 145 u32 bchctl_off; 146 u32 dma_cfg_off; 147 u32 dma_data_buf_off; 148 u32 dma_oob_buf_off; 149 u32 dma_st_off; 150 u32 bch_st_off; 151 u32 randmz_off; 152 u32 int_en_off; 153 u32 int_clr_off; 154 u32 int_st_off; 155 u32 oob0_off; 156 u32 oob1_off; 157 struct ecc_cnt_status ecc0; 158 struct ecc_cnt_status ecc1; 159}; 160 161struct rk_nfc_nand_chip { 162 struct nand_chip chip; 163 164 u16 boot_blks; 165 u16 metadata_size; 166 u32 boot_ecc; 167 u32 timing; 168 169 u8 nsels; 170 u8 sels[0]; 171 /* Nothing after this field. */ 172}; 173 174struct rk_nfc { 175 struct nand_hw_control controller; 176 const struct nfc_cfg *cfg; 177 struct udevice *dev; 178 179 struct clk *nfc_clk; 180 struct clk *ahb_clk; 181 void __iomem *regs; 182 183 int selected_bank; 184 u32 band_offset; 185 u32 cur_ecc; 186 u32 cur_timing; 187 188 u8 *page_buf; 189 u32 *oob_buf; 190 191 unsigned long assigned_cs; 192}; 193 194static inline struct rk_nfc_nand_chip *rk_nfc_to_rknand(struct nand_chip *chip) 195{ 196 return container_of(chip, struct rk_nfc_nand_chip, chip); 197} 198 199static inline u8 *rk_nfc_buf_to_data_ptr(struct nand_chip *chip, const u8 *p, int i) 200{ 201 return (u8 *)p + i * chip->ecc.size; 202} 203 204static inline u8 *rk_nfc_buf_to_oob_ptr(struct nand_chip *chip, int i) 205{ 206 u8 *poi; 207 208 poi = chip->oob_poi + i * NFC_SYS_DATA_SIZE; 209 210 return poi; 211} 212 213static inline u8 *rk_nfc_buf_to_oob_ecc_ptr(struct nand_chip *chip, int i) 214{ 215 struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); 216 u8 *poi; 217 218 poi = chip->oob_poi + rknand->metadata_size + chip->ecc.bytes * i; 219 220 return poi; 221} 222 223static inline int rk_nfc_data_len(struct nand_chip *chip) 224{ 225 return chip->ecc.size + chip->ecc.bytes + NFC_SYS_DATA_SIZE; 226} 227 228static inline u8 *rk_nfc_data_ptr(struct nand_chip *chip, int i) 229{ 230 struct rk_nfc *nfc = nand_get_controller_data(chip); 231 232 return nfc->page_buf + i * rk_nfc_data_len(chip); 233} 234 235static inline u8 *rk_nfc_oob_ptr(struct nand_chip *chip, int i) 236{ 237 struct rk_nfc *nfc = nand_get_controller_data(chip); 238 239 return nfc->page_buf + i * rk_nfc_data_len(chip) + chip->ecc.size; 240} 241 242static int rk_nfc_hw_ecc_setup(struct nand_chip *chip, u32 strength) 243{ 244 struct rk_nfc *nfc = nand_get_controller_data(chip); 245 u32 reg, i; 246 247 for (i = 0; i < NFC_ECC_MAX_MODES; i++) { 248 if (strength == nfc->cfg->ecc_strengths[i]) { 249 reg = nfc->cfg->ecc_cfgs[i]; 250 break; 251 } 252 } 253 254 if (i >= NFC_ECC_MAX_MODES) 255 return -EINVAL; 256 257 writel(reg, nfc->regs + nfc->cfg->bchctl_off); 258 259 /* Save chip ECC setting */ 260 nfc->cur_ecc = strength; 261 262 return 0; 263} 264 265static void rk_nfc_select_chip(struct mtd_info *mtd, int cs) 266{ 267 struct nand_chip *chip = mtd_to_nand(mtd); 268 struct rk_nfc *nfc = nand_get_controller_data(chip); 269 struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); 270 struct nand_ecc_ctrl *ecc = &chip->ecc; 271 u32 val; 272 273 if (cs < 0) { 274 nfc->selected_bank = -1; 275 /* Deselect the currently selected target. */ 276 val = readl(nfc->regs + NFC_FMCTL); 277 val &= ~FMCTL_CE_SEL_M; 278 writel(val, nfc->regs + NFC_FMCTL); 279 return; 280 } 281 282 nfc->selected_bank = rknand->sels[cs]; 283 nfc->band_offset = NFC_BANK + nfc->selected_bank * NFC_BANK_STEP; 284 285 val = readl(nfc->regs + NFC_FMCTL); 286 val &= ~FMCTL_CE_SEL_M; 287 val |= FMCTL_CE_SEL(nfc->selected_bank); 288 289 writel(val, nfc->regs + NFC_FMCTL); 290 291 /* 292 * Compare current chip timing with selected chip timing and 293 * change if needed. 294 */ 295 if (nfc->cur_timing != rknand->timing) { 296 writel(rknand->timing, nfc->regs + NFC_FMWAIT); 297 nfc->cur_timing = rknand->timing; 298 } 299 300 /* 301 * Compare current chip ECC setting with selected chip ECC setting and 302 * change if needed. 303 */ 304 if (nfc->cur_ecc != ecc->strength) 305 rk_nfc_hw_ecc_setup(chip, ecc->strength); 306} 307 308static inline int rk_nfc_wait_ioready(struct rk_nfc *nfc) 309{ 310 u32 timeout = (CONFIG_SYS_HZ * NFC_TIMEOUT_MS) / 1000; 311 u32 time_start; 312 313 time_start = get_timer(0); 314 do { 315 if (readl(nfc->regs + NFC_FMCTL) & FMCTL_RDY) 316 return 0; 317 } while (get_timer(time_start) < timeout); 318 319 dev_err(nfc->dev, "wait for io ready timedout\n"); 320 return -ETIMEDOUT; 321} 322 323static void rk_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) 324{ 325 struct nand_chip *chip = mtd_to_nand(mtd); 326 struct rk_nfc *nfc = nand_get_controller_data(chip); 327 void __iomem *bank_base; 328 int i = 0; 329 330 bank_base = nfc->regs + nfc->band_offset + BANK_DATA; 331 332 for (i = 0; i < len; i++) 333 buf[i] = readl(bank_base); 334} 335 336static void rk_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) 337{ 338 struct nand_chip *chip = mtd_to_nand(mtd); 339 struct rk_nfc *nfc = nand_get_controller_data(chip); 340 void __iomem *bank_base; 341 int i = 0; 342 343 bank_base = nfc->regs + nfc->band_offset + BANK_DATA; 344 345 for (i = 0; i < len; i++) 346 writel(buf[i], bank_base); 347} 348 349static void rk_nfc_cmd(struct mtd_info *mtd, int dat, unsigned int ctrl) 350{ 351 struct nand_chip *chip = mtd_to_nand(mtd); 352 struct rk_nfc *nfc = nand_get_controller_data(chip); 353 void __iomem *bank_base; 354 355 bank_base = nfc->regs + nfc->band_offset; 356 357 if (ctrl & NAND_CTRL_CHANGE) { 358 if (ctrl & NAND_ALE) 359 bank_base += BANK_ADDR; 360 else if (ctrl & NAND_CLE) 361 bank_base += BANK_CMD; 362 chip->IO_ADDR_W = bank_base; 363 } 364 365 if (dat != NAND_CMD_NONE) 366 writel(dat & 0xFF, chip->IO_ADDR_W); 367} 368 369static uint8_t rockchip_nand_read_byte(struct mtd_info *mtd) 370{ 371 uint8_t ret; 372 373 rk_nfc_read_buf(mtd, &ret, 1); 374 375 return ret; 376} 377 378static int rockchip_nand_dev_ready(struct mtd_info *mtd) 379{ 380 struct nand_chip *chip = mtd_to_nand(mtd); 381 struct rk_nfc *nfc = nand_get_controller_data(chip); 382 383 if (readl(nfc->regs + NFC_FMCTL) & FMCTL_RDY) 384 return 1; 385 386 return 0; 387} 388 389static void rk_nfc_xfer_start(struct rk_nfc *nfc, u8 rw, u8 n_KB, 390 dma_addr_t dma_data, dma_addr_t dma_oob) 391{ 392 u32 dma_reg, fl_reg, bch_reg; 393 394 dma_reg = DMA_ST | ((!rw) << DMA_WR) | DMA_EN | (2 << DMA_AHB_SIZE) | 395 (7 << DMA_BURST_SIZE) | (16 << DMA_INC_NUM); 396 397 fl_reg = (rw << FLCTL_WR) | FLCTL_XFER_EN | FLCTL_ACORRECT | 398 (n_KB << FLCTL_XFER_SECTOR) | FLCTL_TOG_FIX; 399 400 if (nfc->cfg->type == NFC_V6 || nfc->cfg->type == NFC_V8) { 401 bch_reg = readl_relaxed(nfc->regs + nfc->cfg->bchctl_off); 402 bch_reg = (bch_reg & (~BCHCTL_BANK_M)) | 403 (nfc->selected_bank << BCHCTL_BANK); 404 writel(bch_reg, nfc->regs + nfc->cfg->bchctl_off); 405 } 406 407 writel(dma_reg, nfc->regs + nfc->cfg->dma_cfg_off); 408 writel((u32)dma_data, nfc->regs + nfc->cfg->dma_data_buf_off); 409 writel((u32)dma_oob, nfc->regs + nfc->cfg->dma_oob_buf_off); 410 writel(fl_reg, nfc->regs + nfc->cfg->flctl_off); 411 fl_reg |= FLCTL_XFER_ST; 412 writel(fl_reg, nfc->regs + nfc->cfg->flctl_off); 413} 414 415static int rk_nfc_wait_for_xfer_done(struct rk_nfc *nfc) 416{ 417 unsigned long timeout = (CONFIG_SYS_HZ * NFC_TIMEOUT_MS) / 1000; 418 void __iomem *ptr = nfc->regs + nfc->cfg->flctl_off; 419 u32 time_start; 420 421 time_start = get_timer(0); 422 423 do { 424 if (readl(ptr) & FLCTL_XFER_READY) 425 return 0; 426 } while (get_timer(time_start) < timeout); 427 428 dev_err(nfc->dev, "wait for io ready timedout\n"); 429 return -ETIMEDOUT; 430} 431 432static int rk_nfc_write_page_raw(struct mtd_info *mtd, 433 struct nand_chip *chip, 434 const u8 *buf, 435 int oob_required, 436 int page) 437{ 438 struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); 439 struct rk_nfc *nfc = nand_get_controller_data(chip); 440 struct nand_ecc_ctrl *ecc = &chip->ecc; 441 int i, pages_per_blk; 442 443 pages_per_blk = mtd->erasesize / mtd->writesize; 444 if ((page < (pages_per_blk * rknand->boot_blks)) && 445 rknand->boot_ecc != ecc->strength) { 446 /* 447 * There's currently no method to notify the MTD framework that 448 * a different ECC strength is in use for the boot blocks. 449 */ 450 return -EIO; 451 } 452 453 if (!buf) 454 memset(nfc->page_buf, 0xff, mtd->writesize + mtd->oobsize); 455 456 for (i = 0; i < ecc->steps; i++) { 457 /* Copy data to the NFC buffer. */ 458 if (buf) 459 memcpy(rk_nfc_data_ptr(chip, i), 460 rk_nfc_buf_to_data_ptr(chip, buf, i), 461 ecc->size); 462 /* 463 * The first four bytes of OOB are reserved for the 464 * boot ROM. In some debugging cases, such as with a 465 * read, erase and write back test these 4 bytes stored 466 * in OOB also need to be written back. 467 * 468 * The function nand_block_bad detects bad blocks like: 469 * 470 * bad = chip->oob_poi[chip->badblockpos]; 471 * 472 * chip->badblockpos == 0 for a large page NAND Flash, 473 * so chip->oob_poi[0] is the bad block mask (BBM). 474 * 475 * The OOB data layout on the NFC is: 476 * 477 * PA0 PA1 PA2 PA3 | BBM OOB1 OOB2 OOB3 | ... 478 * 479 * or 480 * 481 * 0xFF 0xFF 0xFF 0xFF | BBM OOB1 OOB2 OOB3 | ... 482 * 483 * The code here just swaps the first 4 bytes with the last 484 * 4 bytes without losing any data. 485 * 486 * The chip->oob_poi data layout: 487 * 488 * BBM OOB1 OOB2 OOB3 |......| PA0 PA1 PA2 PA3 489 * 490 * The oobfree structure already has reserved these 4 bytes 491 * together with 2 bytes for BBM by reducing it's length: 492 * 493 * oobfree[0].length = rknand->metadata_size - NFC_SYS_DATA_SIZE - 2; 494 */ 495 if (!i) 496 memcpy(rk_nfc_oob_ptr(chip, i), 497 rk_nfc_buf_to_oob_ptr(chip, ecc->steps - 1), 498 NFC_SYS_DATA_SIZE); 499 else 500 memcpy(rk_nfc_oob_ptr(chip, i), 501 rk_nfc_buf_to_oob_ptr(chip, i - 1), 502 NFC_SYS_DATA_SIZE); 503 /* Copy ECC data to the NFC buffer. */ 504 memcpy(rk_nfc_oob_ptr(chip, i) + NFC_SYS_DATA_SIZE, 505 rk_nfc_buf_to_oob_ecc_ptr(chip, i), 506 ecc->bytes); 507 } 508 509 nand_prog_page_begin_op(chip, page, 0, NULL, 0); 510 rk_nfc_write_buf(mtd, buf, mtd->writesize + mtd->oobsize); 511 return nand_prog_page_end_op(chip); 512} 513 514static int rk_nfc_write_page_hwecc(struct mtd_info *mtd, 515 struct nand_chip *chip, 516 const u8 *buf, 517 int oob_required, 518 int page) 519{ 520 struct rk_nfc *nfc = nand_get_controller_data(chip); 521 struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); 522 struct nand_ecc_ctrl *ecc = &chip->ecc; 523 int oob_step = (ecc->bytes > 60) ? NFC_MAX_OOB_PER_STEP : 524 NFC_MIN_OOB_PER_STEP; 525 int pages_per_blk = mtd->erasesize / mtd->writesize; 526 int ret = 0, i, boot_rom_mode = 0; 527 dma_addr_t dma_data, dma_oob; 528 u32 tmp; 529 u8 *oob; 530 531 nand_prog_page_begin_op(chip, page, 0, NULL, 0); 532 533 if (buf) 534 memcpy(nfc->page_buf, buf, mtd->writesize); 535 else 536 memset(nfc->page_buf, 0xFF, mtd->writesize); 537 538 /* 539 * The first blocks (4, 8 or 16 depending on the device) are used 540 * by the boot ROM and the first 32 bits of OOB need to link to 541 * the next page address in the same block. We can't directly copy 542 * OOB data from the MTD framework, because this page address 543 * conflicts for example with the bad block marker (BBM), 544 * so we shift all OOB data including the BBM with 4 byte positions. 545 * As a consequence the OOB size available to the MTD framework is 546 * also reduced with 4 bytes. 547 * 548 * PA0 PA1 PA2 PA3 | BBM OOB1 OOB2 OOB3 | ... 549 * 550 * If a NAND is not a boot medium or the page is not a boot block, 551 * the first 4 bytes are left untouched by writing 0xFF to them. 552 * 553 * 0xFF 0xFF 0xFF 0xFF | BBM OOB1 OOB2 OOB3 | ... 554 * 555 * The code here just swaps the first 4 bytes with the last 556 * 4 bytes without losing any data. 557 * 558 * The chip->oob_poi data layout: 559 * 560 * BBM OOB1 OOB2 OOB3 |......| PA0 PA1 PA2 PA3 561 * 562 * Configure the ECC algorithm supported by the boot ROM. 563 */ 564 if (page < (pages_per_blk * rknand->boot_blks)) { 565 boot_rom_mode = 1; 566 if (rknand->boot_ecc != ecc->strength) 567 rk_nfc_hw_ecc_setup(chip, rknand->boot_ecc); 568 } 569 570 for (i = 0; i < ecc->steps; i++) { 571 if (!i) 572 oob = chip->oob_poi + (ecc->steps - 1) * NFC_SYS_DATA_SIZE; 573 else 574 oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE; 575 576 tmp = oob[0] | oob[1] << 8 | oob[2] << 16 | oob[3] << 24; 577 578 if (nfc->cfg->type == NFC_V9) 579 nfc->oob_buf[i] = tmp; 580 else 581 nfc->oob_buf[i * (oob_step / 4)] = tmp; 582 } 583 584 dma_data = dma_map_single((void *)nfc->page_buf, 585 mtd->writesize, DMA_TO_DEVICE); 586 dma_oob = dma_map_single(nfc->oob_buf, 587 ecc->steps * oob_step, 588 DMA_TO_DEVICE); 589 590 rk_nfc_xfer_start(nfc, NFC_WRITE, ecc->steps, dma_data, 591 dma_oob); 592 ret = rk_nfc_wait_for_xfer_done(nfc); 593 594 dma_unmap_single(dma_data, mtd->writesize, 595 DMA_TO_DEVICE); 596 dma_unmap_single(dma_oob, ecc->steps * oob_step, 597 DMA_TO_DEVICE); 598 599 if (boot_rom_mode && rknand->boot_ecc != ecc->strength) 600 rk_nfc_hw_ecc_setup(chip, ecc->strength); 601 602 if (ret) { 603 dev_err(nfc->dev, "write: wait transfer done timeout.\n"); 604 return -ETIMEDOUT; 605 } 606 607 return nand_prog_page_end_op(chip); 608} 609 610static int rk_nfc_write_oob(struct mtd_info *mtd, 611 struct nand_chip *chip, int page) 612{ 613 return rk_nfc_write_page_hwecc(mtd, chip, NULL, 1, page); 614} 615 616static int rk_nfc_read_page_raw(struct mtd_info *mtd, 617 struct nand_chip *chip, 618 u8 *buf, 619 int oob_required, 620 int page) 621{ 622 struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); 623 struct rk_nfc *nfc = nand_get_controller_data(chip); 624 struct nand_ecc_ctrl *ecc = &chip->ecc; 625 int i, pages_per_blk; 626 627 pages_per_blk = mtd->erasesize / mtd->writesize; 628 if ((page < (pages_per_blk * rknand->boot_blks)) && 629 nfc->selected_bank == 0 && 630 rknand->boot_ecc != ecc->strength) { 631 /* 632 * There's currently no method to notify the MTD framework that 633 * a different ECC strength is in use for the boot blocks. 634 */ 635 return -EIO; 636 } 637 638 nand_read_page_op(chip, page, 0, NULL, 0); 639 rk_nfc_read_buf(mtd, nfc->page_buf, mtd->writesize + mtd->oobsize); 640 for (i = 0; i < ecc->steps; i++) { 641 /* 642 * The first four bytes of OOB are reserved for the 643 * boot ROM. In some debugging cases, such as with a read, 644 * erase and write back test, these 4 bytes also must be 645 * saved somewhere, otherwise this information will be 646 * lost during a write back. 647 */ 648 if (!i) 649 memcpy(rk_nfc_buf_to_oob_ptr(chip, ecc->steps - 1), 650 rk_nfc_oob_ptr(chip, i), 651 NFC_SYS_DATA_SIZE); 652 else 653 memcpy(rk_nfc_buf_to_oob_ptr(chip, i - 1), 654 rk_nfc_oob_ptr(chip, i), 655 NFC_SYS_DATA_SIZE); 656 657 /* Copy ECC data from the NFC buffer. */ 658 memcpy(rk_nfc_buf_to_oob_ecc_ptr(chip, i), 659 rk_nfc_oob_ptr(chip, i) + NFC_SYS_DATA_SIZE, 660 ecc->bytes); 661 662 /* Copy data from the NFC buffer. */ 663 if (buf) 664 memcpy(rk_nfc_buf_to_data_ptr(chip, buf, i), 665 rk_nfc_data_ptr(chip, i), 666 ecc->size); 667 } 668 669 return 0; 670} 671 672static int rk_nfc_read_page_hwecc(struct mtd_info *mtd, 673 struct nand_chip *chip, 674 u8 *buf, 675 int oob_required, 676 int page) 677{ 678 struct rk_nfc *nfc = nand_get_controller_data(chip); 679 struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); 680 struct nand_ecc_ctrl *ecc = &chip->ecc; 681 int oob_step = (ecc->bytes > 60) ? NFC_MAX_OOB_PER_STEP : 682 NFC_MIN_OOB_PER_STEP; 683 int pages_per_blk = mtd->erasesize / mtd->writesize; 684 dma_addr_t dma_data, dma_oob; 685 int ret = 0, i, cnt, boot_rom_mode = 0; 686 int max_bitflips = 0, bch_st, ecc_fail = 0; 687 u8 *oob; 688 u32 tmp; 689 690 nand_read_page_op(chip, page, 0, NULL, 0); 691 692 dma_data = dma_map_single(nfc->page_buf, 693 mtd->writesize, 694 DMA_FROM_DEVICE); 695 dma_oob = dma_map_single(nfc->oob_buf, 696 ecc->steps * oob_step, 697 DMA_FROM_DEVICE); 698 699 /* 700 * The first blocks (4, 8 or 16 depending on the device) 701 * are used by the boot ROM. 702 * Configure the ECC algorithm supported by the boot ROM. 703 */ 704 if (page < (pages_per_blk * rknand->boot_blks) && 705 nfc->selected_bank == 0) { 706 boot_rom_mode = 1; 707 if (rknand->boot_ecc != ecc->strength) 708 rk_nfc_hw_ecc_setup(chip, rknand->boot_ecc); 709 } 710 711 rk_nfc_xfer_start(nfc, NFC_READ, ecc->steps, dma_data, 712 dma_oob); 713 ret = rk_nfc_wait_for_xfer_done(nfc); 714 715 dma_unmap_single(dma_data, mtd->writesize, 716 DMA_FROM_DEVICE); 717 dma_unmap_single(dma_oob, ecc->steps * oob_step, 718 DMA_FROM_DEVICE); 719 720 if (ret) { 721 ret = -ETIMEDOUT; 722 dev_err(nfc->dev, "read: wait transfer done timeout.\n"); 723 goto timeout_err; 724 } 725 726 for (i = 0; i < ecc->steps; i++) { 727 if (!i) 728 oob = chip->oob_poi + (ecc->steps - 1) * NFC_SYS_DATA_SIZE; 729 else 730 oob = chip->oob_poi + (i - 1) * NFC_SYS_DATA_SIZE; 731 732 if (nfc->cfg->type == NFC_V9) 733 tmp = nfc->oob_buf[i]; 734 else 735 tmp = nfc->oob_buf[i * (oob_step / 4)]; 736 737 *oob++ = (u8)tmp; 738 *oob++ = (u8)(tmp >> 8); 739 *oob++ = (u8)(tmp >> 16); 740 *oob++ = (u8)(tmp >> 24); 741 } 742 743 for (i = 0; i < (ecc->steps / 2); i++) { 744 bch_st = readl_relaxed(nfc->regs + 745 nfc->cfg->bch_st_off + i * 4); 746 if (bch_st & BIT(nfc->cfg->ecc0.err_flag_bit) || 747 bch_st & BIT(nfc->cfg->ecc1.err_flag_bit)) { 748 mtd->ecc_stats.failed++; 749 ecc_fail = 1; 750 } else { 751 cnt = ECC_ERR_CNT(bch_st, nfc->cfg->ecc0); 752 mtd->ecc_stats.corrected += cnt; 753 max_bitflips = max_t(u32, max_bitflips, cnt); 754 755 cnt = ECC_ERR_CNT(bch_st, nfc->cfg->ecc1); 756 mtd->ecc_stats.corrected += cnt; 757 max_bitflips = max_t(u32, max_bitflips, cnt); 758 } 759 } 760 761 if (buf) 762 memcpy(buf, nfc->page_buf, mtd->writesize); 763 764timeout_err: 765 if (boot_rom_mode && rknand->boot_ecc != ecc->strength) 766 rk_nfc_hw_ecc_setup(chip, ecc->strength); 767 768 if (ret) 769 return ret; 770 771 if (ecc_fail) { 772 dev_err(nfc->dev, "read page: %x ecc error!\n", page); 773 return 0; 774 } 775 776 return max_bitflips; 777} 778 779static int rk_nfc_read_oob(struct mtd_info *mtd, 780 struct nand_chip *chip, int page) 781{ 782 return rk_nfc_read_page_hwecc(mtd, chip, NULL, 1, page); 783} 784 785static inline void rk_nfc_hw_init(struct rk_nfc *nfc) 786{ 787 /* Disable flash wp. */ 788 writel(FMCTL_WP, nfc->regs + NFC_FMCTL); 789 /* Config default timing 40ns at 150 Mhz NFC clock. */ 790 writel(0x1081, nfc->regs + NFC_FMWAIT); 791 nfc->cur_timing = 0x1081; 792 /* Disable randomizer and DMA. */ 793 writel(0, nfc->regs + nfc->cfg->randmz_off); 794 writel(0, nfc->regs + nfc->cfg->dma_cfg_off); 795 writel(FLCTL_RST, nfc->regs + nfc->cfg->flctl_off); 796} 797 798static int rk_nfc_enable_clks(struct udevice *dev, struct rk_nfc *nfc) 799{ 800 int ret; 801 802 if (!IS_ERR(nfc->nfc_clk)) { 803 ret = clk_prepare_enable(nfc->nfc_clk); 804 if (ret) 805 dev_err(dev, "failed to enable NFC clk\n"); 806 } 807 808 ret = clk_prepare_enable(nfc->ahb_clk); 809 if (ret) { 810 dev_err(dev, "failed to enable ahb clk\n"); 811 if (!IS_ERR(nfc->nfc_clk)) 812 clk_disable_unprepare(nfc->nfc_clk); 813 } 814 815 return 0; 816} 817 818static void rk_nfc_disable_clks(struct rk_nfc *nfc) 819{ 820 if (!IS_ERR(nfc->nfc_clk)) 821 clk_disable_unprepare(nfc->nfc_clk); 822 clk_disable_unprepare(nfc->ahb_clk); 823} 824 825static int rk_nfc_ecc_init(struct rk_nfc *nfc, struct nand_chip *chip) 826{ 827 struct rk_nfc_nand_chip *rknand = rk_nfc_to_rknand(chip); 828 const u8 *strengths = nfc->cfg->ecc_strengths; 829 struct mtd_info *mtd = nand_to_mtd(chip); 830 struct nand_ecc_ctrl *ecc = &chip->ecc; 831 u8 max_strength, nfc_max_strength; 832 int i; 833 834 nfc_max_strength = nfc->cfg->ecc_strengths[0]; 835 /* If optional dt settings not present. */ 836 if (!ecc->size || !ecc->strength || 837 ecc->strength > nfc_max_strength) { 838 chip->ecc.size = 1024; 839 ecc->steps = mtd->writesize / ecc->size; 840 841 /* 842 * HW ECC always requests the number of ECC bytes per 1024 byte 843 * blocks. The first 4 OOB bytes are reserved for sys data. 844 */ 845 max_strength = ((mtd->oobsize / ecc->steps) - 4) * 8 / 846 fls(8 * 1024); 847 if (max_strength > nfc_max_strength) 848 max_strength = nfc_max_strength; 849 850 for (i = 0; i < 4; i++) { 851 if (max_strength >= strengths[i]) 852 break; 853 } 854 855 if (i >= 4) { 856 dev_err(nfc->dev, "unsupported ECC strength\n"); 857 return -EOPNOTSUPP; 858 } 859 860 ecc->strength = strengths[i]; 861 } 862 ecc->steps = mtd->writesize / ecc->size; 863 ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * chip->ecc.size), 8); 864 865 if (ecc->bytes * ecc->steps > mtd->oobsize - rknand->metadata_size) 866 return -EINVAL; 867 868 ecc->layout = kzalloc(sizeof(*ecc->layout), GFP_KERNEL); 869 if (!ecc->layout) 870 return -ENOMEM; 871 872 ecc->layout->eccbytes = ecc->bytes * ecc->steps; 873 874 for (i = 0; i < ecc->layout->eccbytes; i++) 875 ecc->layout->eccpos[i] = rknand->metadata_size + i; 876 877 ecc->layout->oobfree[0].length = rknand->metadata_size - NFC_SYS_DATA_SIZE - 2; 878 ecc->layout->oobfree[0].offset = 2; 879 880 return 0; 881} 882 883static int rk_nfc_nand_chip_init(ofnode node, struct rk_nfc *nfc, int devnum) 884{ 885 struct rk_nfc_nand_chip *rknand; 886 struct udevice *dev = nfc->dev; 887 struct nand_ecc_ctrl *ecc; 888 struct nand_chip *chip; 889 struct mtd_info *mtd; 890 u32 cs[NFC_MAX_NSELS]; 891 int nsels, i, ret; 892 u32 tmp; 893 894 if (!ofnode_get_property(node, "reg", &nsels)) 895 return -ENODEV; 896 nsels /= sizeof(u32); 897 if (!nsels || nsels > NFC_MAX_NSELS) { 898 dev_err(dev, "invalid reg property size %d\n", nsels); 899 return -EINVAL; 900 } 901 902 rknand = kzalloc(sizeof(*rknand) + nsels * sizeof(u8), GFP_KERNEL); 903 if (!rknand) 904 return -ENOMEM; 905 906 rknand->nsels = nsels; 907 rknand->timing = nfc->cur_timing; 908 909 ret = ofnode_read_u32_array(node, "reg", cs, nsels); 910 if (ret < 0) { 911 dev_err(dev, "Could not retrieve reg property\n"); 912 return -EINVAL; 913 } 914 915 for (i = 0; i < nsels; i++) { 916 if (cs[i] >= NFC_MAX_NSELS) { 917 dev_err(dev, "invalid CS: %u\n", cs[i]); 918 return -EINVAL; 919 } 920 921 if (test_and_set_bit(cs[i], &nfc->assigned_cs)) { 922 dev_err(dev, "CS %u already assigned\n", cs[i]); 923 return -EINVAL; 924 } 925 926 rknand->sels[i] = cs[i]; 927 } 928 929 chip = &rknand->chip; 930 ecc = &chip->ecc; 931 ecc->mode = NAND_ECC_HW_SYNDROME; 932 933 ret = ofnode_read_u32(node, "nand-ecc-strength", &tmp); 934 ecc->strength = ret ? 0 : tmp; 935 936 ret = ofnode_read_u32(node, "nand-ecc-step-size", &tmp); 937 ecc->size = ret ? 0 : tmp; 938 939 mtd = nand_to_mtd(chip); 940 mtd->owner = THIS_MODULE; 941 mtd->dev->parent = dev; 942 943 nand_set_controller_data(chip, nfc); 944 945 chip->flash_node = node; 946 chip->chip_delay = NFC_RB_DELAY_US; 947 chip->select_chip = rk_nfc_select_chip; 948 chip->cmd_ctrl = rk_nfc_cmd; 949 chip->read_buf = rk_nfc_read_buf; 950 chip->write_buf = rk_nfc_write_buf; 951 chip->read_byte = rockchip_nand_read_byte; 952 chip->dev_ready = rockchip_nand_dev_ready; 953 chip->controller = &nfc->controller; 954 955 chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB; 956 chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER; 957 958 if (IS_ENABLED(CONFIG_ROCKCHIP_NAND_SKIP_BBTSCAN)) 959 chip->options |= NAND_SKIP_BBTSCAN; 960 961 rk_nfc_hw_init(nfc); 962 ret = nand_scan_ident(mtd, nsels, NULL); 963 if (ret) 964 return ret; 965 966 ret = rk_nfc_ecc_init(nfc, chip); 967 if (ret) { 968 dev_err(dev, "rk_nfc_ecc_init failed: %d\n", ret); 969 return ret; 970 } 971 972 ret = ofnode_read_u32(node, "rockchip,boot-blks", &tmp); 973 rknand->boot_blks = ret ? 0 : tmp; 974 975 ret = ofnode_read_u32(node, "rockchip,boot-ecc-strength", &tmp); 976 rknand->boot_ecc = ret ? ecc->strength : tmp; 977 978 rknand->metadata_size = NFC_SYS_DATA_SIZE * ecc->steps; 979 980 if (rknand->metadata_size < NFC_SYS_DATA_SIZE + 2) { 981 dev_err(dev, 982 "driver needs at least %d bytes of meta data\n", 983 NFC_SYS_DATA_SIZE + 2); 984 return -EIO; 985 } 986 987 if (!nfc->page_buf) { 988 nfc->page_buf = kzalloc(NFC_MAX_PAGE_SIZE, GFP_KERNEL); 989 if (!nfc->page_buf) { 990 kfree(ecc->layout); 991 return -ENOMEM; 992 } 993 } 994 995 if (!nfc->oob_buf) { 996 nfc->oob_buf = kzalloc(NFC_MAX_OOB_SIZE, GFP_KERNEL); 997 if (!nfc->oob_buf) { 998 kfree(ecc->layout); 999 kfree(nfc->page_buf); 1000 nfc->page_buf = NULL; 1001 return -ENOMEM; 1002 } 1003 } 1004 1005 ecc->read_page = rk_nfc_read_page_hwecc; 1006 ecc->read_page_raw = rk_nfc_read_page_raw; 1007 ecc->read_oob = rk_nfc_read_oob; 1008 ecc->write_page = rk_nfc_write_page_hwecc; 1009 ecc->write_page_raw = rk_nfc_write_page_raw; 1010 ecc->write_oob = rk_nfc_write_oob; 1011 1012 ret = nand_scan_tail(mtd); 1013 if (ret) { 1014 dev_err(dev, "nand_scan_tail failed: %d\n", ret); 1015 return ret; 1016 } 1017 1018 return nand_register(devnum, mtd); 1019} 1020 1021static int rk_nfc_nand_chips_init(struct udevice *dev, struct rk_nfc *nfc) 1022{ 1023 int ret, i = 0; 1024 ofnode child; 1025 1026 ofnode_for_each_subnode(child, dev_ofnode(dev)) { 1027 ret = rk_nfc_nand_chip_init(child, nfc, i++); 1028 if (ret) 1029 return ret; 1030 } 1031 1032 return 0; 1033} 1034 1035static struct nfc_cfg nfc_v6_cfg = { 1036 .type = NFC_V6, 1037 .ecc_strengths = {60, 40, 24, 16}, 1038 .ecc_cfgs = { 1039 0x00040011, 0x00040001, 0x00000011, 0x00000001, 1040 }, 1041 .flctl_off = 0x08, 1042 .bchctl_off = 0x0C, 1043 .dma_cfg_off = 0x10, 1044 .dma_data_buf_off = 0x14, 1045 .dma_oob_buf_off = 0x18, 1046 .dma_st_off = 0x1C, 1047 .bch_st_off = 0x20, 1048 .randmz_off = 0x150, 1049 .int_en_off = 0x16C, 1050 .int_clr_off = 0x170, 1051 .int_st_off = 0x174, 1052 .oob0_off = 0x200, 1053 .oob1_off = 0x230, 1054 .ecc0 = { 1055 .err_flag_bit = 2, 1056 .low = 3, 1057 .low_mask = 0x1F, 1058 .low_bn = 5, 1059 .high = 27, 1060 .high_mask = 0x1, 1061 }, 1062 .ecc1 = { 1063 .err_flag_bit = 15, 1064 .low = 16, 1065 .low_mask = 0x1F, 1066 .low_bn = 5, 1067 .high = 29, 1068 .high_mask = 0x1, 1069 }, 1070}; 1071 1072static struct nfc_cfg nfc_v8_cfg = { 1073 .type = NFC_V8, 1074 .ecc_strengths = {16, 16, 16, 16}, 1075 .ecc_cfgs = { 1076 0x00000001, 0x00000001, 0x00000001, 0x00000001, 1077 }, 1078 .flctl_off = 0x08, 1079 .bchctl_off = 0x0C, 1080 .dma_cfg_off = 0x10, 1081 .dma_data_buf_off = 0x14, 1082 .dma_oob_buf_off = 0x18, 1083 .dma_st_off = 0x1C, 1084 .bch_st_off = 0x20, 1085 .randmz_off = 0x150, 1086 .int_en_off = 0x16C, 1087 .int_clr_off = 0x170, 1088 .int_st_off = 0x174, 1089 .oob0_off = 0x200, 1090 .oob1_off = 0x230, 1091 .ecc0 = { 1092 .err_flag_bit = 2, 1093 .low = 3, 1094 .low_mask = 0x1F, 1095 .low_bn = 5, 1096 .high = 27, 1097 .high_mask = 0x1, 1098 }, 1099 .ecc1 = { 1100 .err_flag_bit = 15, 1101 .low = 16, 1102 .low_mask = 0x1F, 1103 .low_bn = 5, 1104 .high = 29, 1105 .high_mask = 0x1, 1106 }, 1107}; 1108 1109static struct nfc_cfg nfc_v9_cfg = { 1110 .type = NFC_V9, 1111 .ecc_strengths = {70, 60, 40, 16}, 1112 .ecc_cfgs = { 1113 0x00000001, 0x06000001, 0x04000001, 0x02000001, 1114 }, 1115 .flctl_off = 0x10, 1116 .bchctl_off = 0x20, 1117 .dma_cfg_off = 0x30, 1118 .dma_data_buf_off = 0x34, 1119 .dma_oob_buf_off = 0x38, 1120 .dma_st_off = 0x3C, 1121 .bch_st_off = 0x150, 1122 .randmz_off = 0x208, 1123 .int_en_off = 0x120, 1124 .int_clr_off = 0x124, 1125 .int_st_off = 0x128, 1126 .oob0_off = 0x200, 1127 .oob1_off = 0x204, 1128 .ecc0 = { 1129 .err_flag_bit = 2, 1130 .low = 3, 1131 .low_mask = 0x7F, 1132 .low_bn = 7, 1133 .high = 0, 1134 .high_mask = 0x0, 1135 }, 1136 .ecc1 = { 1137 .err_flag_bit = 18, 1138 .low = 19, 1139 .low_mask = 0x7F, 1140 .low_bn = 7, 1141 .high = 0, 1142 .high_mask = 0x0, 1143 }, 1144}; 1145 1146static const struct udevice_id rk_nfc_id_table[] = { 1147 { 1148 .compatible = "rockchip,px30-nfc", 1149 .data = (unsigned long)&nfc_v9_cfg 1150 }, 1151 { 1152 .compatible = "rockchip,rk2928-nfc", 1153 .data = (unsigned long)&nfc_v6_cfg 1154 }, 1155 { 1156 .compatible = "rockchip,rv1108-nfc", 1157 .data = (unsigned long)&nfc_v8_cfg 1158 }, 1159 { /* sentinel */ } 1160}; 1161 1162static int rk_nfc_probe(struct udevice *dev) 1163{ 1164 struct rk_nfc *nfc = dev_get_priv(dev); 1165 int ret = 0; 1166 1167 nfc->cfg = (void *)dev_get_driver_data(dev); 1168 nfc->dev = dev; 1169 1170 nfc->regs = dev_read_addr_ptr(dev); 1171 if (!nfc->regs) { 1172 ret = -EINVAL; 1173 goto release_nfc; 1174 } 1175 1176 nfc->nfc_clk = devm_clk_get(dev, "nfc"); 1177 if (IS_ERR(nfc->nfc_clk)) { 1178 dev_dbg(dev, "no NFC clk\n"); 1179 /* Some earlier models, such as rk3066, have no NFC clk. */ 1180 } 1181 1182 nfc->ahb_clk = devm_clk_get(dev, "ahb"); 1183 if (IS_ERR(nfc->ahb_clk)) { 1184 dev_err(dev, "no ahb clk\n"); 1185 ret = PTR_ERR(nfc->ahb_clk); 1186 goto release_nfc; 1187 } 1188 1189 ret = rk_nfc_enable_clks(dev, nfc); 1190 if (ret) 1191 goto release_nfc; 1192 1193 spin_lock_init(&nfc->controller.lock); 1194 init_waitqueue_head(&nfc->controller.wq); 1195 1196 rk_nfc_hw_init(nfc); 1197 1198 ret = rk_nfc_nand_chips_init(dev, nfc); 1199 if (ret) { 1200 dev_err(dev, "failed to init NAND chips\n"); 1201 goto clk_disable; 1202 } 1203 return 0; 1204 1205clk_disable: 1206 rk_nfc_disable_clks(nfc); 1207release_nfc: 1208 return ret; 1209} 1210 1211U_BOOT_DRIVER(rockchip_nfc) = { 1212 .name = "rockchip_nfc", 1213 .id = UCLASS_MTD, 1214 .of_match = rk_nfc_id_table, 1215 .probe = rk_nfc_probe, 1216 .priv_auto = sizeof(struct rk_nfc), 1217}; 1218 1219void board_nand_init(void) 1220{ 1221 struct udevice *dev; 1222 int ret; 1223 1224 ret = uclass_get_device_by_driver(UCLASS_MTD, 1225 DM_DRIVER_GET(rockchip_nfc), 1226 &dev); 1227 if (ret && ret != -ENODEV) 1228 log_err("Failed to initialize ROCKCHIP NAND controller. (error %d)\n", 1229 ret); 1230} 1231 1232int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) 1233{ 1234 struct mtd_info *mtd; 1235 size_t length = size; 1236 1237 mtd = get_nand_dev_by_index(0); 1238 return nand_read_skip_bad(mtd, offs, &length, NULL, size, (u_char *)dst); 1239} 1240 1241void nand_deselect(void) {} 1242