Searched refs:clk (Results 251 - 275 of 956) sorted by relevance

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/u-boot/arch/arm/mach-sunxi/
H A Ddram_suniv.c44 u32 clk; /* dram work clock (unit: MHz) */ member in struct:dram_para
58 .clk = 156,
94 static void dram_set_autofresh_cycle(u32 clk) argument
105 if (clk >= 1000000) {
106 temp = clk + (clk >> 3) + (clk >> 4) + (clk >> 5);
112 val = (clk * 499) >> 6;
115 if (clk >
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H A Dclock_sun8i_a83t.c72 void clock_set_pll1(unsigned int clk) argument
85 /* clk = 24*n/p, p is ignored if clock is >288MHz */
87 CCM_PLL1_CTRL_N(clk / 24000000),
92 CCM_PLL1_CTRL_N(clk / (24000000)),
106 void clock_set_pll5(unsigned int clk) argument
114 CCM_PLL5_CTRL_N(clk / (24000000)) |
/u-boot/drivers/clk/sifive/
H A Dsifive-prci.c26 #include <clk-uclass.h>
27 #include <clk.h>
570 static ulong sifive_prci_get_rate(struct clk *clk) argument
574 (struct prci_clk_desc *)dev_get_driver_data(clk->dev);
576 if (data->num_clks <= clk->id)
579 pc = &data->clks[clk->id];
586 static ulong sifive_prci_set_rate(struct clk *clk, ulong rate) argument
591 (struct prci_clk_desc *)dev_get_driver_data(clk
607 sifive_prci_enable(struct clk *clk) argument
627 sifive_prci_disable(struct clk *clk) argument
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/u-boot/arch/arm/include/asm/ti-common/
H A Dkeystone_serdes.h45 enum ks2_serdes_clock clk; member in struct:ks2_serdes
/u-boot/arch/arm/include/asm/arch-mx31/
H A Dclock.h25 unsigned int mxc_get_clock(enum mxc_clock clk);
/u-boot/drivers/usb/dwc3/
H A Ddwc3-generic.h12 #include <clk.h>
/u-boot/arch/arm/mach-mediatek/
H A Dspl.c7 #include <clk.h>
/u-boot/arch/arm/mach-zynqmp/
H A Dclk.c10 #include <asm/arch/clk.h>
/u-boot/board/ea/ea-lpc3250devkitv2/
H A Dea-lpc3250devkitv2.c12 #include <asm/arch/clk.h>
/u-boot/test/dm/
H A Dof_platdata.c4 #include <clk.h>
183 struct udevice *dev, *clk; local
189 ut_assertok(device_get_by_ofplat_idx(plat->clocks[0].idx, &clk));
190 ut_asserteq_str("sandbox_fixed_clock", clk->name);
192 ut_assertok(device_get_by_ofplat_idx(plat->clocks[1].idx, &clk));
193 ut_asserteq_str("sandbox_clk", clk->name);
196 ut_assertok(device_get_by_ofplat_idx(plat->clocks[2].idx, &clk));
197 ut_asserteq_str("sandbox_clk", clk->name);
200 ut_assertok(device_get_by_ofplat_idx(plat->clocks[3].idx, &clk));
201 ut_asserteq_str("sandbox_clk", clk
232 struct clk clk; local
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/u-boot/arch/sandbox/include/asm/
H A Dscmi_test.h62 * @clk: Simulated clocks
73 struct sandbox_scmi_clk *clk; member in struct:sandbox_scmi_agent
93 * @clk: Array the clock devices
103 struct clk *clk; member in struct:sandbox_scmi_devices
/u-boot/drivers/clk/qcom/
H A Dclock-sm8250.c8 #include <clk-uclass.h>
62 static ulong sm8250_set_rate(struct clk *clk, ulong rate) argument
64 struct msm_clk_priv *priv = dev_get_priv(clk->dev);
67 if (clk->id < priv->data->num_clks)
69 priv->data->clks[clk->id].name, rate);
71 switch (clk->id) {
176 static int sm8250_enable(struct clk *clk) argument
178 struct msm_clk_priv *priv = dev_get_priv(clk
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/u-boot/arch/arm/cpu/arm926ejs/mxs/
H A Dclock.c203 uint32_t clk, clkreg; local
216 clk = XTAL_FREQ_KHZ;
218 clk = mxs_get_ioclk(ssp >> 1);
220 if (freq > clk)
224 clk /= freq;
225 if (clk > CLKCTRL_SSP_DIV_MASK)
226 clk = CLKCTRL_SSP_DIV_MASK;
228 clrsetbits_le32(clkreg, CLKCTRL_SSP_DIV_MASK, clk);
248 uint32_t clk, tmp; local
265 clk
276 const enum mxs_sspclock clk = mxs_ssp_clock_by_bus(bus); local
405 mxc_get_clock(enum mxc_clock clk) argument
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/u-boot/drivers/clk/rockchip/
H A Dclk_rk322x.c7 #include <clk-uclass.h>
354 static ulong rk322x_clk_get_rate(struct clk *clk) argument
356 struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
360 switch (clk->id) {
362 rate = rkclk_pll_get_rate(priv->cru, clk->id);
368 rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
377 static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate) argument
379 struct rk322x_clk_priv *priv = dev_get_priv(clk
406 rk322x_gmac_set_parent(struct clk *clk, struct clk *parent) argument
434 rk322x_gmac_extclk_set_parent(struct clk *clk, struct clk *parent) argument
459 rk322x_clk_set_parent(struct clk *clk, struct clk *parent) argument
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/u-boot/drivers/net/
H A Dhifemac_mdio.c9 #include <clk.h>
23 struct clk *clk; member in struct:hisi_femac_mdio_data
82 // clk is optional
83 data->clk = devm_clk_get_optional(dev, NULL);
93 ret = clk_prepare_enable(data->clk);
96 return log_msg_ret("clk", ret);
/u-boot/drivers/rng/
H A Dmsm_rng.c12 #include <clk.h>
36 struct clk clk; member in struct:msm_rng_priv
107 ret = clk_get_by_index(dev, 0, &priv->clk);
111 ret = clk_enable(&priv->clk);
/u-boot/drivers/phy/
H A Dbcm6318-usbh-phy.c11 #include <clk.h>
85 struct clk clk; local
93 ret = clk_get_by_name(dev, "usbh", &clk);
97 ret = clk_enable(&clk);
/u-boot/drivers/sound/
H A Drockchip_sound.c11 #include <clk.h>
52 struct clk clk; local
90 ret = clk_get_by_index(uc_priv->i2s, 1, &clk);
95 ret = clk_set_rate(&clk, 12288000);
/u-boot/drivers/ram/starfive/
H A Dstarfive_ddr.c10 #include <clk.h>
30 struct clk clk; member in struct:starfive_ddr_priv
115 ret = clk_get_by_index(dev, 0, &priv->clk);
119 ret = clk_set_rate(&priv->clk, rate);
/u-boot/drivers/serial/
H A Dserial_owl.c10 #include <clk.h>
82 struct clk clk; local
94 ret = clk_get_by_index(dev, 0, &clk);
98 ret = clk_enable(&clk);
/u-boot/drivers/clk/altera/
H A Dclk-mem-n5x.c10 #include "clk-mem-n5x.h"
11 #include <clk-uclass.h>
80 static int socfpga_mem_clk_enable(struct clk *clk) argument
83 struct socfpga_mem_clk_plat *plat = dev_get_plat(clk->dev);
85 clk_mem_basic_init(clk->dev, cm_default_cfg);
130 .name = "mem-clk-n5x",
/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.c19 #include <asm/kona-common/clk.h>
20 #include "clk-core.h"
31 struct clk *c;
79 static int peri_clk_enable(struct clk *c, int enable)
162 static int peri_clk_set_rate(struct clk *c, unsigned long rate)
184 div = ref->clk.rate / rate;
188 new_rate = ref->clk.rate / div;
194 c->parent = &ref->clk;
206 static unsigned long peri_clk_get_rate(struct clk *c)
241 c->parent = &ref->clk;
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/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.c19 #include <asm/kona-common/clk.h>
20 #include "clk-core.h"
31 struct clk *c;
79 static int peri_clk_enable(struct clk *c, int enable)
162 static int peri_clk_set_rate(struct clk *c, unsigned long rate)
184 div = ref->clk.rate / rate;
188 new_rate = ref->clk.rate / div;
194 c->parent = &ref->clk;
206 static unsigned long peri_clk_get_rate(struct clk *c)
241 c->parent = &ref->clk;
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/u-boot/arch/arm/cpu/armv7/ls102xa/
H A Dclock.c19 struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_LS1_CLK_ADDR); local
53 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
61 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
105 unsigned int mxc_get_clock(enum mxc_clock clk) argument
107 switch (clk) {
/u-boot/drivers/clk/renesas/
H A Drenesas-cpg-mssr.h122 bool renesas_clk_is_mod(struct clk *clk);
123 int renesas_clk_get_mod(struct clk *clk, struct cpg_mssr_info *info,
125 int renesas_clk_get_core(struct clk *clk, struct cpg_mssr_info *info,
127 int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
128 struct clk *parent);
129 int renesas_clk_endisable(struct clk *cl
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