#
3e01ed8e |
|
28-Feb-2023 |
Marek Vasut <marek.vasut+renesas@mailbox.org> |
clk: renesas: Update R-Car Gen3 driver Gen4 support Update R-Car Gen4 support in Gen3 clock driver. This patch renames the V3U clock parts to Gen4 and extends them by new PLL2, PLL3, PLL4, PLL6 as well as SDSRC clock which use undocumented bits so far, and RPCSRC clock which uses its own more capable divider table. The Gen4 module standby and reset tables are also updated. This patch makes use of union to alias Gen3 and more extensive Gen4 PLL tables, as the driver cannot ever be instantiated on hardware that would identify itself as both Gen3 and Gen4. The V3U clock driver is updated to match Gen4 clock driver behavior, it is augmented with a more extensive PLL table and a valid MODEMR register offset. This supersedes "clk: renesas: Introduce R-Car Gen4 CPG driver" from Hai Pham as the R-Car Gen3 and Gen4 clock core drivers are extremely similar. That implementation was in turn based on Linux commit 470e3f0d0b15 ("clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver") by Yoshihiro Shimoda . Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> |
#
b092f962 |
|
10-Aug-2020 |
Hai Pham <hai.pham.ud@renesas.com> |
clk: renesas: Add R8A779A0 clock tables Add clock tables for R8A779A0 V3U SoC from Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> -- Marek: - Add .reset_modemr_offset - Sync tables from Linux 5.12 - Rebase on latest u-boot |
#
d413214f |
|
05-Nov-2020 |
Hai Pham <hai.pham.ud@renesas.com> |
clk: renesas: Add register pointers into struct cpg_mssr_info Base on Linux v5.10-rc2, commit 8b652aa8a1fb by Yoshihiro Shimoda To support other register layouts in the future, add register pointers of {control,status,reset,reset_clear}_regs into struct cpg_mssr_info Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
406c93c8 |
|
05-Nov-2020 |
Hai Pham <hai.pham.ud@renesas.com> |
clk: renesas: Introduce enum clk_reg_layout From Linux v5.10-rc2, commit ffbf9cf3f946 by Yoshihiro Shimoda Introduce enum clk_reg_layout to support multiple register layout variants Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
f7f8d473 |
|
21-May-2020 |
Hai Pham <hai.pham.ud@renesas.com> |
clk: renesas: Pass struct cpg_mssr_info to renesas_clk_endisable() CPG IP in some specific Renesas SoCs (i.e. new R8A779A0 V3U SoC) requires a different setting procedure. Make struct cpg_mssr_info accessible to handle the clock setting in that case. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
e9354091 |
|
25-Apr-2021 |
Marek Vasut <marex@denx.de> |
clk: renesas: Make reset controller modemr register offset configurable The MODEMR register offset changed on R8A779A0, make the MODEMR offset configurable. Fill the offset in on all clock drivers. No functional change. Based off "clk: renesas: Make CPG Reset MODEMR offset accessible from struct cpg_mssr_info" by Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
72242e54 |
|
04-Mar-2019 |
Marek Vasut <marex@denx.de> |
clk: renesas: Synchronize Gen3 tables with Linux 5.0 Synchronize R-Car Gen3 clock tables with Linux 5.0, commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
dedb60fb |
|
08-Jan-2018 |
Marek Vasut <marex@denx.de> |
clk: renesas: Add Gen2 clock core Add common clock code for Renesas RCar Gen2 platforms. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
28b8f225 |
|
17-Jan-2018 |
Marek Vasut <marex@denx.de> |
clk: renesas: Add DIV6P1 clock type Add macros for the DIV6P1 clock type, which is used on Gen2 and optionally also on Gen3. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
d2628671 |
|
15-Jan-2018 |
Marek Vasut <marex@denx.de> |
clk: renesas: Split out code shared between Gen2 and Gen3 Pull code which is common for RCar Gen2 and RCar Gen3 into separate source file. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
ff50b323 |
|
14-Jan-2018 |
Marek Vasut <marex@denx.de> |
clk: renesas: Split SMSTPCR and RMSTPCR tables The Gen2 requires setting RMSTPCR before booting, while on Gen3 this is thus far always zero. Split the tables so the RMSTPCR can be set too. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
58f1788f |
|
08-Jan-2018 |
Marek Vasut <marex@denx.de> |
clk: renesas: Pull Gen3 specific bits into separate header Extract the macros specific to Gen3 clock into a separate header. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
7c885563 |
|
16-Jan-2018 |
Marek Vasut <marex@denx.de> |
clk: renesas: Make PLL configurations per-SoC Not all SoCs have the same PLL configuration options, so make those PLL configuraion tables per-SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
f11c9679 |
|
08-Jan-2018 |
Marek Vasut <marex@denx.de> |
clk: renesas: Make clk_ids per-driver Not all drivers use the same IDs, so make those IDs per-driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
f77b5a4c |
|
08-Jan-2018 |
Marek Vasut <marex@denx.de> |
clk: renesas: Split RCar Gen3 driver Split the massive driver into smaller per-SoC drivers and pull the common code into a separate file. This would allow configuring out unnecessary clock drivers once the Kconfig changes are in and also allow adding more clock tables easily. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
b092f962 |
|
10-Aug-2020 |
Hai Pham <hai.pham.ud@renesas.com> |
clk: renesas: Add R8A779A0 clock tables Add clock tables for R8A779A0 V3U SoC from Linux 5.12, commit 9f4ad9e425a1 ("Linux 5.12") Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> -- Marek: - Add .reset_modemr_offset - Sync tables from Linux 5.12 - Rebase on latest u-boot |
#
d413214f |
|
05-Nov-2020 |
Hai Pham <hai.pham.ud@renesas.com> |
clk: renesas: Add register pointers into struct cpg_mssr_info Base on Linux v5.10-rc2, commit 8b652aa8a1fb by Yoshihiro Shimoda To support other register layouts in the future, add register pointers of {control,status,reset,reset_clear}_regs into struct cpg_mssr_info Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
406c93c8 |
|
05-Nov-2020 |
Hai Pham <hai.pham.ud@renesas.com> |
clk: renesas: Introduce enum clk_reg_layout From Linux v5.10-rc2, commit ffbf9cf3f946 by Yoshihiro Shimoda Introduce enum clk_reg_layout to support multiple register layout variants Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
f7f8d473 |
|
21-May-2020 |
Hai Pham <hai.pham.ud@renesas.com> |
clk: renesas: Pass struct cpg_mssr_info to renesas_clk_endisable() CPG IP in some specific Renesas SoCs (i.e. new R8A779A0 V3U SoC) requires a different setting procedure. Make struct cpg_mssr_info accessible to handle the clock setting in that case. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
e9354091 |
|
25-Apr-2021 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Make reset controller modemr register offset configurable The MODEMR register offset changed on R8A779A0, make the MODEMR offset configurable. Fill the offset in on all clock drivers. No functional change. Based off "clk: renesas: Make CPG Reset MODEMR offset accessible from struct cpg_mssr_info" by Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
72242e54 |
|
04-Mar-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Synchronize Gen3 tables with Linux 5.0 Synchronize R-Car Gen3 clock tables with Linux 5.0, commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
dedb60fb |
|
08-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Add Gen2 clock core Add common clock code for Renesas RCar Gen2 platforms. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
28b8f225 |
|
17-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Add DIV6P1 clock type Add macros for the DIV6P1 clock type, which is used on Gen2 and optionally also on Gen3. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
d2628671 |
|
15-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Split out code shared between Gen2 and Gen3 Pull code which is common for RCar Gen2 and RCar Gen3 into separate source file. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
ff50b323 |
|
14-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Split SMSTPCR and RMSTPCR tables The Gen2 requires setting RMSTPCR before booting, while on Gen3 this is thus far always zero. Split the tables so the RMSTPCR can be set too. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
58f1788f |
|
08-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Pull Gen3 specific bits into separate header Extract the macros specific to Gen3 clock into a separate header. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
7c885563 |
|
16-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Make PLL configurations per-SoC Not all SoCs have the same PLL configuration options, so make those PLL configuraion tables per-SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
f11c9679 |
|
08-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Make clk_ids per-driver Not all drivers use the same IDs, so make those IDs per-driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
f77b5a4c |
|
08-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Split RCar Gen3 driver Split the massive driver into smaller per-SoC drivers and pull the common code into a separate file. This would allow configuring out unnecessary clock drivers once the Kconfig changes are in and also allow adding more clock tables easily. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
d413214f |
|
05-Nov-2020 |
Hai Pham <hai.pham.ud@renesas.com> |
clk: renesas: Add register pointers into struct cpg_mssr_info Base on Linux v5.10-rc2, commit 8b652aa8a1fb by Yoshihiro Shimoda To support other register layouts in the future, add register pointers of {control,status,reset,reset_clear}_regs into struct cpg_mssr_info Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
406c93c8 |
|
05-Nov-2020 |
Hai Pham <hai.pham.ud@renesas.com> |
clk: renesas: Introduce enum clk_reg_layout From Linux v5.10-rc2, commit ffbf9cf3f946 by Yoshihiro Shimoda Introduce enum clk_reg_layout to support multiple register layout variants Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
f7f8d473 |
|
21-May-2020 |
Hai Pham <hai.pham.ud@renesas.com> |
clk: renesas: Pass struct cpg_mssr_info to renesas_clk_endisable() CPG IP in some specific Renesas SoCs (i.e. new R8A779A0 V3U SoC) requires a different setting procedure. Make struct cpg_mssr_info accessible to handle the clock setting in that case. Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
e9354091 |
|
25-Apr-2021 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Make reset controller modemr register offset configurable The MODEMR register offset changed on R8A779A0, make the MODEMR offset configurable. Fill the offset in on all clock drivers. No functional change. Based off "clk: renesas: Make CPG Reset MODEMR offset accessible from struct cpg_mssr_info" by Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> |
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
72242e54 |
|
04-Mar-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Synchronize Gen3 tables with Linux 5.0 Synchronize R-Car Gen3 clock tables with Linux 5.0, commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
dedb60fb |
|
08-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Add Gen2 clock core Add common clock code for Renesas RCar Gen2 platforms. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
28b8f225 |
|
17-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Add DIV6P1 clock type Add macros for the DIV6P1 clock type, which is used on Gen2 and optionally also on Gen3. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
d2628671 |
|
15-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Split out code shared between Gen2 and Gen3 Pull code which is common for RCar Gen2 and RCar Gen3 into separate source file. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
ff50b323 |
|
14-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Split SMSTPCR and RMSTPCR tables The Gen2 requires setting RMSTPCR before booting, while on Gen3 this is thus far always zero. Split the tables so the RMSTPCR can be set too. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
58f1788f |
|
08-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Pull Gen3 specific bits into separate header Extract the macros specific to Gen3 clock into a separate header. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
7c885563 |
|
16-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Make PLL configurations per-SoC Not all SoCs have the same PLL configuration options, so make those PLL configuraion tables per-SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
f11c9679 |
|
08-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Make clk_ids per-driver Not all drivers use the same IDs, so make those IDs per-driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
f77b5a4c |
|
08-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Split RCar Gen3 driver Split the massive driver into smaller per-SoC drivers and pull the common code into a separate file. This would allow configuring out unnecessary clock drivers once the Kconfig changes are in and also allow adding more clock tables easily. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
cd93d625 |
|
10-May-2020 |
Simon Glass <sjg@chromium.org> |
common: Drop linux/bitops.h from common header Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org> |
#
72242e54 |
|
04-Mar-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Synchronize Gen3 tables with Linux 5.0 Synchronize R-Car Gen3 clock tables with Linux 5.0, commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
dedb60fb |
|
08-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Add Gen2 clock core Add common clock code for Renesas RCar Gen2 platforms. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
28b8f225 |
|
17-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Add DIV6P1 clock type Add macros for the DIV6P1 clock type, which is used on Gen2 and optionally also on Gen3. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
d2628671 |
|
15-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Split out code shared between Gen2 and Gen3 Pull code which is common for RCar Gen2 and RCar Gen3 into separate source file. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
ff50b323 |
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14-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Split SMSTPCR and RMSTPCR tables The Gen2 requires setting RMSTPCR before booting, while on Gen3 this is thus far always zero. Split the tables so the RMSTPCR can be set too. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
58f1788f |
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08-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Pull Gen3 specific bits into separate header Extract the macros specific to Gen3 clock into a separate header. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
7c885563 |
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16-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Make PLL configurations per-SoC Not all SoCs have the same PLL configuration options, so make those PLL configuraion tables per-SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
f11c9679 |
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08-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Make clk_ids per-driver Not all drivers use the same IDs, so make those IDs per-driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
f77b5a4c |
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08-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Split RCar Gen3 driver Split the massive driver into smaller per-SoC drivers and pull the common code into a separate file. This would allow configuring out unnecessary clock drivers once the Kconfig changes are in and also allow adding more clock tables easily. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
72242e54 |
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04-Mar-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Synchronize Gen3 tables with Linux 5.0 Synchronize R-Car Gen3 clock tables with Linux 5.0, commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 . Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
dedb60fb |
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08-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Add Gen2 clock core Add common clock code for Renesas RCar Gen2 platforms. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
28b8f225 |
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17-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Add DIV6P1 clock type Add macros for the DIV6P1 clock type, which is used on Gen2 and optionally also on Gen3. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
d2628671 |
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15-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Split out code shared between Gen2 and Gen3 Pull code which is common for RCar Gen2 and RCar Gen3 into separate source file. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
ff50b323 |
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14-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Split SMSTPCR and RMSTPCR tables The Gen2 requires setting RMSTPCR before booting, while on Gen3 this is thus far always zero. Split the tables so the RMSTPCR can be set too. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
58f1788f |
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08-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Pull Gen3 specific bits into separate header Extract the macros specific to Gen3 clock into a separate header. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
7c885563 |
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16-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Make PLL configurations per-SoC Not all SoCs have the same PLL configuration options, so make those PLL configuraion tables per-SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
f11c9679 |
|
08-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Make clk_ids per-driver Not all drivers use the same IDs, so make those IDs per-driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
f77b5a4c |
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08-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Split RCar Gen3 driver Split the massive driver into smaller per-SoC drivers and pull the common code into a separate file. This would allow configuring out unnecessary clock drivers once the Kconfig changes are in and also allow adding more clock tables easily. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
dedb60fb |
|
08-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Add Gen2 clock core Add common clock code for Renesas RCar Gen2 platforms. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
#
28b8f225 |
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17-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Add DIV6P1 clock type Add macros for the DIV6P1 clock type, which is used on Gen2 and optionally also on Gen3. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
#
d2628671 |
|
15-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Split out code shared between Gen2 and Gen3 Pull code which is common for RCar Gen2 and RCar Gen3 into separate source file. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
#
ff50b323 |
|
14-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Split SMSTPCR and RMSTPCR tables The Gen2 requires setting RMSTPCR before booting, while on Gen3 this is thus far always zero. Split the tables so the RMSTPCR can be set too. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
#
58f1788f |
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08-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Pull Gen3 specific bits into separate header Extract the macros specific to Gen3 clock into a separate header. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
#
7c885563 |
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16-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Make PLL configurations per-SoC Not all SoCs have the same PLL configuration options, so make those PLL configuraion tables per-SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
#
f11c9679 |
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08-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Make clk_ids per-driver Not all drivers use the same IDs, so make those IDs per-driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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#
f77b5a4c |
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08-Jan-2018 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
clk: renesas: Split RCar Gen3 driver Split the massive driver into smaller per-SoC drivers and pull the common code into a separate file. This would allow configuring out unnecessary clock drivers once the Kconfig changes are in and also allow adding more clock tables easily. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|