Searched refs:bit (Results 201 - 216 of 216) sorted by relevance
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/u-boot/drivers/net/ti/ |
H A D | cpsw.c | 410 static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val) argument 412 u32 tmp, mask = BIT(bit); 436 /* Set a self-clearing bit in a register, and wait for it to clear */
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/u-boot/arch/arm/include/asm/arch-imx8m/ |
H A D | ddr.h | 740 static inline void reg32setbit(unsigned long addr, u32 bit) argument 742 setbits_le32(addr, (1 << bit));
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/u-boot/drivers/pinctrl/renesas/ |
H A D | pfc-r8a77980.c | 2841 int bit = pin & 0x1f; local 2846 return bit; 2850 return bit + 22; 2854 return bit - 10; 2859 return bit + 7;
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H A D | pfc-r8a77995.c | 397 /* The bit numbering in MOD_SEL fields is reversed */ 3103 unsigned int bit; local 3105 reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit); 3109 *puen_bit = bit; 3111 /* NFWE# and NFRE# use different bit positions in PUD2 */ 3122 *pud_bit = bit;
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H A D | sh_pfc.h | 122 * combination of the register field bit values, all wrapped using 142 * possible combination of the register field bit values, all wrapped 192 * - ids: For each register bit (from left to right, i.e. MSB to LSB), one 740 unsigned int *bit);
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H A D | pfc-r8a779g0.c | 3984 int bit = pin & 0x1f; local 3989 return bit; 3993 return bit; 3997 return bit; 4017 return bit;
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H A D | pfc-r8a779h0.c | 3630 int bit = pin & 0x1f; local 3635 return bit; 3639 return bit; 3643 return bit; 3647 return bit;
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H A D | pfc-r8a77965.c | 6075 int bit = -EINVAL; local 6080 bit = pin & 0x1f; 6083 bit = (pin & 0x1f) + 12; 6085 return bit;
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H A D | pfc-r8a77951.c | 5881 int bit = -EINVAL; local 5886 bit = pin & 0x1f; 5889 bit = (pin & 0x1f) + 12; 5891 return bit;
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H A D | pfc-r8a7796.c | 5834 int bit = -EINVAL; local 5839 bit = pin & 0x1f; 5842 bit = (pin & 0x1f) + 12; 5844 return bit;
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/u-boot/drivers/usb/cdns3/ |
H A D | gadget.c | 18 * 2. Software updates TRBs includes data address and Cycle bit 19 * 3. Controller read TRB which includes Cycle bit 90 * cdns3_set_register_bit - set bit in given register. 275 * cycle state bit The 325 * If bit USB_CONF_L1EN is set and device receive Extended Token packet, 327 * If bit USB_CONF_L1DS is set and device receive Extended Token packet, 688 trace_cdns3_wa1(priv_ep, "restore cycle bit"); 883 * bit only for TR size > 2. 957 * Memory barrier - cycle bit must be set before other filds in trb. 1061 * As first step, function checks if cycle bit fo 1425 int bit; local [all...] |
/u-boot/drivers/usb/isp1760/ |
H A D | isp1760-hcd.c | 278 u32 bit = isp1763_hc_portsc1_fields[field]; local 282 writel(port_status | bit, priv->base + ISP1763_HC_PORTSC1); 284 writel(port_status & ~bit, priv->base + ISP1763_HC_PORTSC1); 380 * doesn't quite work because some people have to enforce 32-bit access 444 * and also adjust 16bit access. 455 /* As long there are at least 16-bit to read ... */ 628 * since it contains the enable bit 799 * The RESET_HC bit in the SW_RESET register is supposed to reset the 801 * least on the ISP1761 it seems to behave as the RESET_ALL bit and 924 /* SE bit fo [all...] |
/u-boot/drivers/mmc/ |
H A D | mmc.c | 634 * can set bit 7 (reserved for low voltages), but 1180 * EXT_CSD_HS_CTRL_REL bit is set. The values can be 2353 * EXT_CSD, so ignore any data if this bit is not set, 2413 * Host needs to enable ERASE_GRP_DEF bit if device is 2414 * partitioned. This bit will be lost every time after a reset 2723 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ 2939 * all hosts are capable of 1 bit bus-width and able to use the legacy 3177 u32 bit = autobkops ? BIT(1) : BIT(0); local 3191 if (enable && (ext_csd[EXT_CSD_BKOPS_EN] & bit)) { 3197 enable ? bit [all...] |
/u-boot/arch/arm/dts/ |
H A D | Makefile | 162 armada-xp-crs305-1g-4s-bit.dtb \ 164 armada-xp-crs326-24g-2s-bit.dtb \ 166 armada-xp-crs328-4c-20s-4s-bit.dtb \
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/u-boot/board/gateworks/gw_ventana/ |
H A D | gw_ventana.c | 138 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */ 1259 if (!test_bit(cfg->bit, info->config)) {
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/u-boot/drivers/net/ |
H A D | mvpp2.c | 642 #define MVPP2_BIT_TO_BYTE(bit) ((bit) / 8) 1400 /* Clear entry invalidation bit */ 3319 val |= 1; /* unmask summary bit */
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