1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Driver for the NXP ISP1760 chip 4 * 5 * Copyright 2021 Linaro, Rui Miguel Silva <rui.silva@linaro.org> 6 * 7 */ 8 9#include <hexdump.h> 10#include <common.h> 11#include <asm/cache.h> 12#include <cpu_func.h> 13#include <dm.h> 14#include <dm/device-internal.h> 15#include <dm/device_compat.h> 16#include <linux/bug.h> 17#include <linux/kernel.h> 18#include <linux/list.h> 19#include <linux/usb/usb_urb_compat.h> 20#include <usb.h> 21#include <linux/io.h> 22#include <linux/iopoll.h> 23#include <asm/unaligned.h> 24 25#include "isp1760-core.h" 26#include "isp1760-hcd.h" 27#include "isp1760-regs.h" 28#include "isp1760-uboot.h" 29 30#define ISP1760_LANGUAGE_DESC "\4\3\19\4" 31#define ISP1760_VENDOR_DESC "\16\3U\0-\0B\0o\0o\0t\0" 32#define ISP1760_PRODUCT_NAME_DESC "\52\3I\0S\0P\0-\0 \0H\0o\0s\0t\0 \0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0" 33 34static struct kmem_cache *qtd_cachep; 35static struct kmem_cache *qh_cachep; 36static struct kmem_cache *urb_listitem_cachep; 37 38typedef void (packet_enqueue)(struct usb_hcd *hcd, struct isp1760_qh *qh, 39 struct isp1760_qtd *qtd); 40 41static inline struct isp1760_hcd *hcd_to_priv(struct usb_hcd *hcd) 42{ 43 return hcd->hcd_priv; 44} 45 46#define dw_to_le32(x) (cpu_to_le32((__force u32)x)) 47#define le32_to_dw(x) ((__force __dw)(le32_to_cpu(x))) 48 49/* urb state*/ 50#define DELETE_URB (0x0008) 51#define NO_TRANSFER_ACTIVE (0xffffffff) 52 53/* Philips Proprietary Transfer Descriptor (PTD) */ 54typedef __u32 __bitwise __dw; 55struct ptd { 56 __dw dw0; 57 __dw dw1; 58 __dw dw2; 59 __dw dw3; 60 __dw dw4; 61 __dw dw5; 62 __dw dw6; 63 __dw dw7; 64}; 65 66struct ptd_le32 { 67 __le32 dw0; 68 __le32 dw1; 69 __le32 dw2; 70 __le32 dw3; 71 __le32 dw4; 72 __le32 dw5; 73 __le32 dw6; 74 __le32 dw7; 75}; 76 77#define PTD_OFFSET 0x0400 78#define ISO_PTD_OFFSET 0x0400 79#define INT_PTD_OFFSET 0x0800 80#define ATL_PTD_OFFSET 0x0c00 81#define PAYLOAD_OFFSET 0x1000 82 83#define ISP_BANK_0 0x00 84#define ISP_BANK_1 0x01 85#define ISP_BANK_2 0x02 86#define ISP_BANK_3 0x03 87 88#define TO_DW(x) ((__force __dw)x) 89#define TO_U32(x) ((__force u32)x) 90 91 /* ATL */ 92 /* DW0 */ 93#define DW0_VALID_BIT TO_DW(1) 94#define FROM_DW0_VALID(x) (TO_U32(x) & 0x01) 95#define TO_DW0_LENGTH(x) TO_DW((((u32)x) << 3)) 96#define TO_DW0_MAXPACKET(x) TO_DW((((u32)x) << 18)) 97#define TO_DW0_MULTI(x) TO_DW((((u32)x) << 29)) 98#define TO_DW0_ENDPOINT(x) TO_DW((((u32)x) << 31)) 99/* DW1 */ 100#define TO_DW1_DEVICE_ADDR(x) TO_DW((((u32)x) << 3)) 101#define TO_DW1_PID_TOKEN(x) TO_DW((((u32)x) << 10)) 102#define DW1_TRANS_BULK TO_DW(((u32)2 << 12)) 103#define DW1_TRANS_INT TO_DW(((u32)3 << 12)) 104#define DW1_TRANS_SPLIT TO_DW(((u32)1 << 14)) 105#define DW1_SE_USB_LOSPEED TO_DW(((u32)2 << 16)) 106#define TO_DW1_PORT_NUM(x) TO_DW((((u32)x) << 18)) 107#define TO_DW1_HUB_NUM(x) TO_DW((((u32)x) << 25)) 108/* DW2 */ 109#define TO_DW2_DATA_START_ADDR(x) TO_DW((((u32)x) << 8)) 110#define TO_DW2_RL(x) TO_DW(((x) << 25)) 111#define FROM_DW2_RL(x) ((TO_U32(x) >> 25) & 0xf) 112/* DW3 */ 113#define FROM_DW3_NRBYTESTRANSFERRED(x) TO_U32((x) & 0x3fff) 114#define FROM_DW3_SCS_NRBYTESTRANSFERRED(x) TO_U32((x) & 0x07ff) 115#define TO_DW3_NAKCOUNT(x) TO_DW(((x) << 19)) 116#define FROM_DW3_NAKCOUNT(x) ((TO_U32(x) >> 19) & 0xf) 117#define TO_DW3_CERR(x) TO_DW(((x) << 23)) 118#define FROM_DW3_CERR(x) ((TO_U32(x) >> 23) & 0x3) 119#define TO_DW3_DATA_TOGGLE(x) TO_DW(((x) << 25)) 120#define FROM_DW3_DATA_TOGGLE(x) ((TO_U32(x) >> 25) & 0x1) 121#define TO_DW3_PING(x) TO_DW(((x) << 26)) 122#define FROM_DW3_PING(x) ((TO_U32(x) >> 26) & 0x1) 123#define DW3_ERROR_BIT TO_DW((1 << 28)) 124#define DW3_BABBLE_BIT TO_DW((1 << 29)) 125#define DW3_HALT_BIT TO_DW((1 << 30)) 126#define DW3_ACTIVE_BIT TO_DW((1 << 31)) 127#define FROM_DW3_ACTIVE(x) ((TO_U32(x) >> 31) & 0x01) 128 129#define INT_UNDERRUN BIT(2) 130#define INT_BABBLE BIT(1) 131#define INT_EXACT BIT(0) 132 133#define SETUP_PID (2) 134#define IN_PID (1) 135#define OUT_PID (0) 136 137/* Errata 1 */ 138#define RL_COUNTER (0) 139#define NAK_COUNTER (0) 140#define ERR_COUNTER (3) 141 142struct isp1760_qtd { 143 u8 packet_type; 144 void *data_buffer; 145 u32 payload_addr; 146 147 /* the rest is HCD-private */ 148 struct list_head qtd_list; 149 struct urb *urb; 150 size_t length; 151 size_t actual_length; 152 153 /* 154 * QTD_ENQUEUED: waiting for transfer (inactive) 155 * QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload 156 * QTD_XFER_STARTED: valid ptd has been written to isp176x - only 157 * interrupt handler may touch this qtd! 158 * QTD_XFER_COMPLETE: payload has been transferred successfully 159 * QTD_RETIRE: transfer error/abort qtd 160 */ 161#define QTD_ENQUEUED 0 162#define QTD_PAYLOAD_ALLOC 1 163#define QTD_XFER_STARTED 2 164#define QTD_XFER_COMPLETE 3 165#define QTD_RETIRE 4 166 u32 status; 167}; 168 169/* Queue head, one for each active endpoint */ 170struct isp1760_qh { 171 struct list_head qh_list; 172 struct list_head qtd_list; 173 int epnum; 174 u32 toggle; 175 u32 ping; 176 int slot; 177 int tt_buffer_dirty; /* See USB2.0 spec section 11.17.5 */ 178}; 179 180struct urb_listitem { 181 struct list_head urb_list; 182 struct urb *urb; 183}; 184 185static const u32 isp1763_hc_portsc1_fields[] = { 186 [PORT_OWNER] = BIT(13), 187 [PORT_POWER] = BIT(12), 188 [PORT_LSTATUS] = BIT(10), 189 [PORT_RESET] = BIT(8), 190 [PORT_SUSPEND] = BIT(7), 191 [PORT_RESUME] = BIT(6), 192 [PORT_PE] = BIT(2), 193 [PORT_CSC] = BIT(1), 194 [PORT_CONNECT] = BIT(0), 195}; 196 197static struct descriptor { 198 struct usb_device_descriptor device; 199 struct usb_config_descriptor config; 200 struct usb_interface_descriptor interface; 201 struct usb_endpoint_descriptor endpoint; 202} __packed rh_descriptor = { 203 { 204 /* usb 2.0 root hub device descriptor */ 205 0x12, /* __u8 bLength; */ 206 USB_DT_DEVICE, /* __u8 bDescriptorType; Device */ 207 0x0002, /* __le16 bcdUSB; v2.0 */ 208 209 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */ 210 0x00, /* __u8 bDeviceSubClass; */ 211 0x00, /* __u8 bDeviceProtocol; [ usb 2.0 no TT ] */ 212 0x40, /* __u8 bMaxPacketSize0; 64 Bytes */ 213 214 0x6b1d, /* __le16 idVendor; Linux Foundation 0x1d6b */ 215 0x0200, /* __le16 idProduct; device 0x0002 */ 216 0x0001, /* __le16 bcdDevice */ 217 218 0x03, /* __u8 iManufacturer; */ 219 0x02, /* __u8 iProduct; */ 220 0x01, /* __u8 iSerialNumber; */ 221 0x01 /* __u8 bNumConfigurations; */ 222 }, { 223 /* one configuration */ 224 0x09, /* __u8 bLength; */ 225 USB_DT_CONFIG, /* __u8 bDescriptorType; Configuration */ 226 0x1900, /* __le16 wTotalLength; */ 227 0x01, /* __u8 bNumInterfaces; (1) */ 228 0x01, /* __u8 bConfigurationValue; */ 229 0x00, /* __u8 iConfiguration; */ 230 0xc0, /* __u8 bmAttributes; 231 * Bit 7: must be set, 232 * 6: Self-powered, 233 * 5: Remote wakeup, 234 * 4..0: resvd 235 */ 236 0x00, /* __u8 MaxPower; */ 237 }, { 238 /* one interface */ 239 0x09, /* __u8 if_bLength; */ 240 USB_DT_INTERFACE, /* __u8 if_bDescriptorType; Interface */ 241 0x00, /* __u8 if_bInterfaceNumber; */ 242 0x00, /* __u8 if_bAlternateSetting; */ 243 0x01, /* __u8 if_bNumEndpoints; */ 244 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */ 245 0x00, /* __u8 if_bInterfaceSubClass; */ 246 0x00, /* __u8 if_bInterfaceProtocol; [usb1.1 or single tt] */ 247 0x00, /* __u8 if_iInterface; */ 248 }, { 249 /* one endpoint (status change endpoint) */ 250 0x07, /* __u8 ep_bLength; */ 251 USB_DT_ENDPOINT, /* __u8 ep_bDescriptorType; Endpoint */ 252 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */ 253 0x03, /* __u8 ep_bmAttributes; Interrupt */ 254 /* __le16 ep_wMaxPacketSize; 1 + (MAX_ROOT_PORTS / 8) */ 255 /* see hub.c:hub_configure() for details. */ 256 (USB_MAXCHILDREN + 1 + 7) / 8, 0x00, 257 0x0c /* __u8 ep_bInterval; (256ms -- usb 2.0 spec) */ 258 }, 259}; 260 261/* 262 * Access functions for isp176x registers regmap fields 263 */ 264static u32 isp1760_hcd_read(struct usb_hcd *hcd, u32 field) 265{ 266 struct isp1760_hcd *priv = hcd_to_priv(hcd); 267 268 return isp1760_field_read(priv->fields, field); 269} 270 271/* 272 * We need, in isp1763, to write directly the values to the portsc1 273 * register so it will make the other values to trigger. 274 */ 275static void isp1760_hcd_portsc1_set_clear(struct isp1760_hcd *priv, u32 field, 276 u32 val) 277{ 278 u32 bit = isp1763_hc_portsc1_fields[field]; 279 u32 port_status = readl(priv->base + ISP1763_HC_PORTSC1); 280 281 if (val) 282 writel(port_status | bit, priv->base + ISP1763_HC_PORTSC1); 283 else 284 writel(port_status & ~bit, priv->base + ISP1763_HC_PORTSC1); 285} 286 287static void isp1760_hcd_write(struct usb_hcd *hcd, u32 field, u32 val) 288{ 289 struct isp1760_hcd *priv = hcd_to_priv(hcd); 290 291 if (unlikely(priv->is_isp1763 && 292 (field >= PORT_OWNER && field <= PORT_CONNECT))) 293 return isp1760_hcd_portsc1_set_clear(priv, field, val); 294 295 isp1760_field_write(priv->fields, field, val); 296} 297 298static void isp1760_hcd_set(struct usb_hcd *hcd, u32 field) 299{ 300 isp1760_hcd_write(hcd, field, 0xFFFFFFFF); 301} 302 303static void isp1760_hcd_clear(struct usb_hcd *hcd, u32 field) 304{ 305 isp1760_hcd_write(hcd, field, 0); 306} 307 308static int isp1760_hcd_set_and_wait(struct usb_hcd *hcd, u32 field, 309 u32 timeout_us) 310{ 311 struct isp1760_hcd *priv = hcd_to_priv(hcd); 312 u32 val; 313 314 isp1760_hcd_set(hcd, field); 315 316 return regmap_field_read_poll_timeout(priv->fields[field], val, 317 val, 0, timeout_us); 318} 319 320static int isp1760_hcd_set_and_wait_swap(struct usb_hcd *hcd, u32 field, 321 u32 timeout_us) 322{ 323 struct isp1760_hcd *priv = hcd_to_priv(hcd); 324 u32 val; 325 326 isp1760_hcd_set(hcd, field); 327 328 return regmap_field_read_poll_timeout(priv->fields[field], val, 329 !val, 0, timeout_us); 330} 331 332static int isp1760_hcd_clear_and_wait(struct usb_hcd *hcd, u32 field, 333 u32 timeout_us) 334{ 335 struct isp1760_hcd *priv = hcd_to_priv(hcd); 336 u32 val; 337 338 isp1760_hcd_clear(hcd, field); 339 340 return regmap_field_read_poll_timeout(priv->fields[field], val, 341 !val, 0, timeout_us); 342} 343 344static bool isp1760_hcd_is_set(struct usb_hcd *hcd, u32 field) 345{ 346 return !!isp1760_hcd_read(hcd, field); 347} 348 349static bool isp1760_hcd_ppc_is_set(struct usb_hcd *hcd) 350{ 351 struct isp1760_hcd *priv = hcd_to_priv(hcd); 352 353 if (priv->is_isp1763) 354 return true; 355 356 return isp1760_hcd_is_set(hcd, HCS_PPC); 357} 358 359static u32 isp1760_hcd_n_ports(struct usb_hcd *hcd) 360{ 361 struct isp1760_hcd *priv = hcd_to_priv(hcd); 362 363 if (priv->is_isp1763) 364 return 1; 365 366 return isp1760_hcd_read(hcd, HCS_N_PORTS); 367} 368 369/* 370 * Access functions for isp176x memory (offset >= 0x0400). 371 * 372 * bank_reads8() reads memory locations prefetched by an earlier write to 373 * HC_MEMORY_REG (see isp176x datasheet). Unless you want to do fancy multi- 374 * bank optimizations, you should use the more generic mem_read() below. 375 * 376 * For access to ptd memory, use the specialized ptd_read() and ptd_write() 377 * below. 378 * 379 * These functions copy via MMIO data to/from the device. memcpy_{to|from}io() 380 * doesn't quite work because some people have to enforce 32-bit access 381 */ 382static void bank_reads8(void __iomem *src_base, u32 src_offset, u32 bank_addr, 383 __u32 *dst, u32 bytes) 384{ 385 __u32 __iomem *src; 386 u32 val; 387 __u8 *src_byteptr; 388 __u8 *dst_byteptr; 389 390 src = src_base + (bank_addr | src_offset); 391 392 if (src_offset < PAYLOAD_OFFSET) { 393 while (bytes >= 4) { 394 *dst = readl_relaxed(src); 395 bytes -= 4; 396 src++; 397 dst++; 398 } 399 } else { 400 while (bytes >= 4) { 401 *dst = __raw_readl(src); 402 bytes -= 4; 403 src++; 404 dst++; 405 } 406 } 407 408 if (!bytes) 409 return; 410 411 /* in case we have 3, 2 or 1 by left. The dst buffer may not be fully 412 * allocated. 413 */ 414 if (src_offset < PAYLOAD_OFFSET) 415 val = readl_relaxed(src); 416 else 417 val = __raw_readl(src); 418 419 dst_byteptr = (void *)dst; 420 src_byteptr = (void *)&val; 421 while (bytes > 0) { 422 *dst_byteptr = *src_byteptr; 423 dst_byteptr++; 424 src_byteptr++; 425 bytes--; 426 } 427} 428 429static void isp1760_mem_read(struct usb_hcd *hcd, u32 src_offset, void *dst, 430 u32 bytes) 431{ 432 struct isp1760_hcd *priv = hcd_to_priv(hcd); 433 434 isp1760_hcd_write(hcd, MEM_BANK_SEL, ISP_BANK_0); 435 isp1760_hcd_write(hcd, MEM_START_ADDR, src_offset); 436 ndelay(100); 437 438 bank_reads8(priv->base, src_offset, ISP_BANK_0, dst, bytes); 439} 440 441/* 442 * ISP1763 does not have the banks direct host controller memory access, 443 * needs to use the HC_DATA register. Add data read/write according to this, 444 * and also adjust 16bit access. 445 */ 446static void isp1763_mem_read(struct usb_hcd *hcd, u16 srcaddr, 447 u16 *dstptr, u32 bytes) 448{ 449 struct isp1760_hcd *priv = hcd_to_priv(hcd); 450 451 /* Write the starting device address to the hcd memory register */ 452 isp1760_reg_write(priv->regs, ISP1763_HC_MEMORY, srcaddr); 453 ndelay(100); /* Delay between consecutive access */ 454 455 /* As long there are at least 16-bit to read ... */ 456 while (bytes >= 2) { 457 *dstptr = __raw_readw(priv->base + ISP1763_HC_DATA); 458 bytes -= 2; 459 dstptr++; 460 } 461 462 /* If there are no more bytes to read, return */ 463 if (bytes <= 0) 464 return; 465 466 *((u8 *)dstptr) = (u8)(readw(priv->base + ISP1763_HC_DATA) & 0xFF); 467} 468 469static void mem_read(struct usb_hcd *hcd, u32 src_offset, __u32 *dst, 470 u32 bytes) 471{ 472 struct isp1760_hcd *priv = hcd_to_priv(hcd); 473 474 if (!priv->is_isp1763) 475 return isp1760_mem_read(hcd, src_offset, (u16 *)dst, bytes); 476 477 isp1763_mem_read(hcd, (u16)src_offset, (u16 *)dst, bytes); 478} 479 480static void isp1760_mem_write(void __iomem *dst_base, u32 dst_offset, 481 __u32 const *src, u32 bytes) 482{ 483 __u32 __iomem *dst; 484 485 dst = dst_base + dst_offset; 486 487 if (dst_offset < PAYLOAD_OFFSET) { 488 while (bytes >= 4) { 489 writel_relaxed(*src, dst); 490 bytes -= 4; 491 src++; 492 dst++; 493 } 494 } else { 495 while (bytes >= 4) { 496 __raw_writel(*src, dst); 497 bytes -= 4; 498 src++; 499 dst++; 500 } 501 } 502 503 if (!bytes) 504 return; 505 /* in case we have 3, 2 or 1 bytes left. The buffer is allocated and the 506 * extra bytes should not be read by the HW. 507 */ 508 509 if (dst_offset < PAYLOAD_OFFSET) 510 writel_relaxed(*src, dst); 511 else 512 __raw_writel(*src, dst); 513} 514 515static void isp1763_mem_write(struct usb_hcd *hcd, u16 dstaddr, u16 *src, 516 u32 bytes) 517{ 518 struct isp1760_hcd *priv = hcd_to_priv(hcd); 519 520 /* Write the starting device address to the hcd memory register */ 521 isp1760_reg_write(priv->regs, ISP1763_HC_MEMORY, dstaddr); 522 ndelay(100); /* Delay between consecutive access */ 523 524 while (bytes >= 2) { 525 /* Get and write the data; then adjust the data ptr and len */ 526 __raw_writew(*src, priv->base + ISP1763_HC_DATA); 527 bytes -= 2; 528 src++; 529 } 530 531 /* If there are no more bytes to process, return */ 532 if (bytes <= 0) 533 return; 534 535 /* 536 * The only way to get here is if there is a single byte left, 537 * get it and write it to the data reg; 538 */ 539 writew(*((u8 *)src), priv->base + ISP1763_HC_DATA); 540} 541 542static void mem_write(struct usb_hcd *hcd, u32 dst_offset, __u32 *src, 543 u32 bytes) 544{ 545 struct isp1760_hcd *priv = hcd_to_priv(hcd); 546 547 if (!priv->is_isp1763) 548 return isp1760_mem_write(priv->base, dst_offset, src, bytes); 549 550 isp1763_mem_write(hcd, dst_offset, (u16 *)src, bytes); 551} 552 553/* 554 * Read and write ptds. 'ptd_offset' should be one of ISO_PTD_OFFSET, 555 * INT_PTD_OFFSET, and ATL_PTD_OFFSET. 'slot' should be less than 32. 556 */ 557static void isp1760_ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, 558 struct ptd *ptd) 559{ 560 u16 src_offset = ptd_offset + slot * sizeof(*ptd); 561 struct isp1760_hcd *priv = hcd_to_priv(hcd); 562 563 isp1760_hcd_write(hcd, MEM_BANK_SEL, ISP_BANK_0); 564 isp1760_hcd_write(hcd, MEM_START_ADDR, src_offset); 565 ndelay(90); 566 567 bank_reads8(priv->base, src_offset, ISP_BANK_0, (void *)ptd, 568 sizeof(*ptd)); 569} 570 571static void isp1763_ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, 572 struct ptd *ptd) 573{ 574 u16 src_offset = ptd_offset + slot * sizeof(*ptd); 575 struct ptd_le32 le32_ptd; 576 577 isp1763_mem_read(hcd, src_offset, (u16 *)&le32_ptd, sizeof(le32_ptd)); 578 /* Normalize the data obtained */ 579 ptd->dw0 = le32_to_dw(le32_ptd.dw0); 580 ptd->dw1 = le32_to_dw(le32_ptd.dw1); 581 ptd->dw2 = le32_to_dw(le32_ptd.dw2); 582 ptd->dw3 = le32_to_dw(le32_ptd.dw3); 583 ptd->dw4 = le32_to_dw(le32_ptd.dw4); 584 ptd->dw5 = le32_to_dw(le32_ptd.dw5); 585 ptd->dw6 = le32_to_dw(le32_ptd.dw6); 586 ptd->dw7 = le32_to_dw(le32_ptd.dw7); 587} 588 589static void ptd_read(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, 590 struct ptd *ptd) 591{ 592 struct isp1760_hcd *priv = hcd_to_priv(hcd); 593 594 if (!priv->is_isp1763) 595 return isp1760_ptd_read(hcd, ptd_offset, slot, ptd); 596 597 isp1763_ptd_read(hcd, ptd_offset, slot, ptd); 598} 599 600static void isp1763_ptd_write(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, 601 struct ptd *cpu_ptd) 602{ 603 u16 dst_offset = ptd_offset + slot * sizeof(*cpu_ptd); 604 struct ptd_le32 ptd; 605 606 ptd.dw0 = dw_to_le32(cpu_ptd->dw0); 607 ptd.dw1 = dw_to_le32(cpu_ptd->dw1); 608 ptd.dw2 = dw_to_le32(cpu_ptd->dw2); 609 ptd.dw3 = dw_to_le32(cpu_ptd->dw3); 610 ptd.dw4 = dw_to_le32(cpu_ptd->dw4); 611 ptd.dw5 = dw_to_le32(cpu_ptd->dw5); 612 ptd.dw6 = dw_to_le32(cpu_ptd->dw6); 613 ptd.dw7 = dw_to_le32(cpu_ptd->dw7); 614 615 isp1763_mem_write(hcd, dst_offset, (u16 *)&ptd.dw0, 616 8 * sizeof(ptd.dw0)); 617} 618 619static void isp1760_ptd_write(void __iomem *base, u32 ptd_offset, u32 slot, 620 struct ptd *ptd) 621{ 622 u32 dst_offset = ptd_offset + slot * sizeof(*ptd); 623 624 isp1760_mem_write(base, dst_offset + sizeof(ptd->dw0), 625 (__force u32 *)&ptd->dw1, 7 * sizeof(ptd->dw1)); 626 /* 627 * Make sure dw0 gets written last (after other dw's and after payload) 628 * since it contains the enable bit 629 */ 630 wmb(); 631 isp1760_mem_write(base, dst_offset, (__force u32 *)&ptd->dw0, 632 sizeof(ptd->dw0)); 633} 634 635static void ptd_write(struct usb_hcd *hcd, u32 ptd_offset, u32 slot, 636 struct ptd *ptd) 637{ 638 struct isp1760_hcd *priv = hcd_to_priv(hcd); 639 640 if (!priv->is_isp1763) 641 return isp1760_ptd_write(priv->base, ptd_offset, slot, ptd); 642 643 isp1763_ptd_write(hcd, ptd_offset, slot, ptd); 644} 645 646/* memory management of the 60kb on the chip from 0x1000 to 0xffff */ 647static void init_memory(struct isp1760_hcd *priv) 648{ 649 const struct isp1760_memory_layout *mem = priv->memory_layout; 650 int i, j, curr; 651 u32 payload_addr; 652 653 payload_addr = PAYLOAD_OFFSET; 654 655 for (i = 0, curr = 0; i < ARRAY_SIZE(mem->blocks); i++, curr += j) { 656 for (j = 0; j < mem->blocks[i]; j++) { 657 priv->memory_pool[curr + j].start = payload_addr; 658 priv->memory_pool[curr + j].size = mem->blocks_size[i]; 659 priv->memory_pool[curr + j].free = 1; 660 payload_addr += priv->memory_pool[curr + j].size; 661 } 662 } 663 664 WARN_ON(payload_addr - priv->memory_pool[0].start > 665 mem->payload_area_size); 666} 667 668static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) 669{ 670 struct isp1760_hcd *priv = hcd_to_priv(hcd); 671 const struct isp1760_memory_layout *mem = priv->memory_layout; 672 int i; 673 674 WARN_ON(qtd->payload_addr); 675 676 if (!qtd->length) 677 return; 678 679 for (i = 0; i < mem->payload_blocks; i++) { 680 if (priv->memory_pool[i].size >= qtd->length && 681 priv->memory_pool[i].free) { 682 priv->memory_pool[i].free = 0; 683 qtd->payload_addr = priv->memory_pool[i].start; 684 return; 685 } 686 } 687} 688 689static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd) 690{ 691 struct isp1760_hcd *priv = hcd_to_priv(hcd); 692 const struct isp1760_memory_layout *mem = priv->memory_layout; 693 int i; 694 695 if (!qtd->payload_addr) 696 return; 697 698 for (i = 0; i < mem->payload_blocks; i++) { 699 if (priv->memory_pool[i].start == qtd->payload_addr) { 700 WARN_ON(priv->memory_pool[i].free); 701 priv->memory_pool[i].free = 1; 702 qtd->payload_addr = 0; 703 return; 704 } 705 } 706 707 WARN_ON(1); 708 qtd->payload_addr = 0; 709} 710 711/* reset a non-running (STS_HALT == 1) controller */ 712static int ehci_reset(struct usb_hcd *hcd) 713{ 714 return isp1760_hcd_set_and_wait_swap(hcd, CMD_RESET, 250 * 1000); 715} 716 717static struct isp1760_qh *qh_alloc(gfp_t flags) 718{ 719 struct isp1760_qh *qh; 720 721 qh = kmem_cache_alloc(qh_cachep, flags); 722 if (!qh) 723 return NULL; 724 725 memset(qh, '\0', qh_cachep->sz); 726 INIT_LIST_HEAD(&qh->qh_list); 727 INIT_LIST_HEAD(&qh->qtd_list); 728 qh->slot = -1; 729 730 return qh; 731} 732 733static void qh_free(struct isp1760_qh *qh) 734{ 735 WARN_ON(!list_empty(&qh->qtd_list)); 736 WARN_ON(qh->slot > -1); 737 kmem_cache_free(qh_cachep, qh); 738} 739 740/* one-time init, only for memory state */ 741static int priv_init(struct usb_hcd *hcd) 742{ 743 struct isp1760_hcd *priv = hcd_to_priv(hcd); 744 u32 isoc_cache; 745 u32 isoc_thres; 746 int i; 747 748 for (i = 0; i < QH_END; i++) 749 INIT_LIST_HEAD(&priv->qh_list[i]); 750 751 /* 752 * hw default: 1K periodic list heads, one per frame. 753 * periodic_size can shrink by USBCMD update if hcc_params allows. 754 */ 755 priv->periodic_size = DEFAULT_I_TDPS; 756 757 if (priv->is_isp1763) { 758 priv->i_thresh = 2; 759 return 0; 760 } 761 762 /* controllers may cache some of the periodic schedule ... */ 763 isoc_cache = isp1760_hcd_read(hcd, HCC_ISOC_CACHE); 764 isoc_thres = isp1760_hcd_read(hcd, HCC_ISOC_THRES); 765 766 /* full frame cache */ 767 if (isoc_cache) 768 priv->i_thresh = 8; 769 else /* N microframes cached */ 770 priv->i_thresh = 2 + isoc_thres; 771 772 return 0; 773} 774 775static int isp1760_hc_setup(struct usb_hcd *hcd) 776{ 777 struct isp1760_hcd *priv = hcd_to_priv(hcd); 778 u32 atx_reset; 779 int result; 780 u32 scratch; 781 u32 pattern; 782 783 if (priv->is_isp1763) 784 pattern = 0xcafe; 785 else 786 pattern = 0xdeadcafe; 787 788 isp1760_hcd_write(hcd, HC_SCRATCH, pattern); 789 790 /* Change bus pattern */ 791 isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH); 792 scratch = isp1760_hcd_read(hcd, HC_SCRATCH); 793 if (scratch != pattern) { 794 printf("Scratch test failed. 0x%08x\n", scratch); 795 return -ENODEV; 796 } 797 798 /* 799 * The RESET_HC bit in the SW_RESET register is supposed to reset the 800 * host controller without touching the CPU interface registers, but at 801 * least on the ISP1761 it seems to behave as the RESET_ALL bit and 802 * reset the whole device. We thus can't use it here, so let's reset 803 * the host controller through the EHCI USB Command register. The device 804 * has been reset in core code anyway, so this shouldn't matter. 805 */ 806 isp1760_hcd_clear(hcd, ISO_BUF_FILL); 807 isp1760_hcd_clear(hcd, INT_BUF_FILL); 808 isp1760_hcd_clear(hcd, ATL_BUF_FILL); 809 810 isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP); 811 isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP); 812 isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP); 813 814 result = ehci_reset(hcd); 815 if (result) 816 return result; 817 818 /* Step 11 passed */ 819 820 /* ATL reset */ 821 if (priv->is_isp1763) 822 atx_reset = SW_RESET_RESET_ATX; 823 else 824 atx_reset = ALL_ATX_RESET; 825 826 isp1760_hcd_set(hcd, atx_reset); 827 mdelay(10); 828 isp1760_hcd_clear(hcd, atx_reset); 829 830 if (priv->is_isp1763) { 831 isp1760_hcd_set(hcd, HW_OTG_DISABLE); 832 isp1760_hcd_set(hcd, HW_SW_SEL_HC_DC_CLEAR); 833 isp1760_hcd_set(hcd, HW_HC_2_DIS_CLEAR); 834 isp1760_hcd_set(hcd, HW_DM_PULLDOWN); 835 isp1760_hcd_set(hcd, HW_DP_PULLDOWN); 836 mdelay(10); 837 838 isp1760_hcd_set(hcd, HW_INTF_LOCK); 839 } 840 841 isp1760_hcd_set(hcd, HC_INT_IRQ_ENABLE); 842 isp1760_hcd_set(hcd, HC_ATL_IRQ_ENABLE); 843 844 return priv_init(hcd); 845} 846 847static u32 base_to_chip(u32 base) 848{ 849 return ((base - 0x400) >> 3); 850} 851 852static int last_qtd_of_urb(struct isp1760_qtd *qtd, struct isp1760_qh *qh) 853{ 854 struct urb *urb; 855 856 if (list_is_last(&qtd->qtd_list, &qh->qtd_list)) 857 return 1; 858 859 urb = qtd->urb; 860 qtd = list_entry(qtd->qtd_list.next, typeof(*qtd), qtd_list); 861 862 return (qtd->urb != urb); 863} 864 865/* magic numbers that can affect system performance */ 866#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ 867#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ 868#define EHCI_TUNE_RL_TT 0 869#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ 870#define EHCI_TUNE_MULT_TT 1 871#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ 872 873static void create_ptd_atl(struct isp1760_qh *qh, struct isp1760_qtd *qtd, 874 struct ptd *ptd) 875{ 876 u32 maxpacket; 877 u32 multi; 878 u32 rl = RL_COUNTER; 879 u32 nak = NAK_COUNTER; 880 u8 portnr; 881 u8 hubaddr; 882 883 memset(ptd, 0, sizeof(*ptd)); 884 885 /* according to 3.6.2, max packet len can not be > 0x400 */ 886 maxpacket = usb_maxpacket(qtd->urb->dev, qtd->urb->pipe); 887 multi = 1 + ((maxpacket >> 11) & 0x3); 888 maxpacket &= 0x7ff; 889 890 /* DW0 */ 891 ptd->dw0 = DW0_VALID_BIT; 892 ptd->dw0 |= TO_DW0_LENGTH(qtd->length); 893 ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket); 894 ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe)); 895 896 /* DW1 */ 897 ptd->dw1 = TO_DW((usb_pipeendpoint(qtd->urb->pipe) >> 1)); 898 ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe)); 899 ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type); 900 901 if (usb_pipebulk(qtd->urb->pipe)) 902 ptd->dw1 |= DW1_TRANS_BULK; 903 else if (usb_pipeint(qtd->urb->pipe)) 904 ptd->dw1 |= DW1_TRANS_INT; 905 906 if (qtd->urb->dev->speed != USB_SPEED_HIGH) { 907 /* split transaction */ 908 909 ptd->dw1 |= DW1_TRANS_SPLIT; 910 if (qtd->urb->dev->speed == USB_SPEED_LOW) 911 ptd->dw1 |= DW1_SE_USB_LOSPEED; 912 913 if (!qtd->urb->dev->dev->parent_priv_) { 914 portnr = qtd->urb->dev->portnr; 915 hubaddr = qtd->urb->dev->devnum; 916 } else { 917 usb_find_usb2_hub_address_port(qtd->urb->dev, &hubaddr, 918 &portnr); 919 } 920 921 ptd->dw1 |= TO_DW1_PORT_NUM(portnr); 922 ptd->dw1 |= TO_DW1_HUB_NUM(hubaddr); 923 924 /* SE bit for Split INT transfers */ 925 if (usb_pipeint(qtd->urb->pipe) && 926 qtd->urb->dev->speed == USB_SPEED_LOW) 927 ptd->dw1 |= DW1_SE_USB_LOSPEED; 928 929 rl = 0; 930 nak = 0; 931 } else { 932 ptd->dw0 |= TO_DW0_MULTI(multi); 933 if (usb_pipecontrol(qtd->urb->pipe) || 934 usb_pipebulk(qtd->urb->pipe)) 935 ptd->dw3 |= TO_DW3_PING(qh->ping); 936 } 937 /* DW2 */ 938 ptd->dw2 = 0; 939 ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr)); 940 ptd->dw2 |= TO_DW2_RL(rl); 941 942 /* DW3 */ 943 ptd->dw3 |= TO_DW3_NAKCOUNT(nak); 944 ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle); 945 946 if (usb_pipecontrol(qtd->urb->pipe)) { 947 if (qtd->data_buffer == qtd->urb->setup_packet) 948 ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1); 949 else if (last_qtd_of_urb(qtd, qh)) 950 ptd->dw3 |= TO_DW3_DATA_TOGGLE(1); 951 } 952 953 ptd->dw3 |= DW3_ACTIVE_BIT; 954 /* Cerr */ 955 ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER); 956} 957 958static void transform_add_int(struct isp1760_qh *qh, struct isp1760_qtd *qtd, 959 struct ptd *ptd) 960{ 961 struct usb_host_endpoint *hep = qtd->urb->ep; 962 struct usb_endpoint_descriptor *epd = &hep->desc; 963 u32 usof; 964 u32 period; 965 966 /* 967 * Most of this is guessing. ISP1761 datasheet is quite unclear, and 968 * the algorithm from the original Philips driver code, which was 969 * pretty much used in this driver before as well, is quite horrendous 970 * and, i believe, incorrect. The code below follows the datasheet and 971 * USB2.0 spec as far as I can tell, and plug/unplug seems to be much 972 * more reliable this way (fingers crossed...). 973 */ 974 975 if (qtd->urb->dev->speed == USB_SPEED_HIGH) { 976 /* urb->interval is in units of microframes (1/8 ms) */ 977 period = epd->bInterval >> 3; 978 979 if (epd->bInterval > 4) 980 usof = 0x01; /* One bit set => interval 1 ms * uFrame-match */ 981 else if (epd->bInterval > 2) 982 usof = 0x22; /* Two bits set => interval 1/2 ms */ 983 else if (epd->bInterval > 1) 984 usof = 0x55; /* Four bits set => interval 1/4 ms */ 985 else 986 usof = 0xff; /* All bits set => interval 1/8 ms */ 987 } else { 988 /* urb->interval is in units of frames (1 ms) */ 989 period = epd->bInterval; 990 /* Execute Start Split on any of the four first uFrames */ 991 usof = 0x0f; 992 993 /* 994 * First 8 bits in dw5 is uSCS and "specifies which uSOF the 995 * complete split needs to be sent. Valid only for IN." Also, 996 * "All bits can be set to one for every transfer." (p 82, 997 * ISP1761 data sheet.) 0x1c is from Philips driver. Where did 998 * that number come from? 0xff seems to work fine... 999 */ 1000 /* Execute Complete Split on any uFrame */ 1001 ptd->dw5 = TO_DW(0xff); 1002 } 1003 1004 /* Ensure equal or shorter period than requested */ 1005 period = period >> 1; 1006 /* Mask off too large values and lowest unused 3 bits */ 1007 period &= 0xf8; 1008 1009 ptd->dw2 |= TO_DW(period); 1010 ptd->dw4 = TO_DW(usof); 1011} 1012 1013static void create_ptd_int(struct isp1760_qh *qh, struct isp1760_qtd *qtd, 1014 struct ptd *ptd) 1015{ 1016 create_ptd_atl(qh, qtd, ptd); 1017 transform_add_int(qh, qtd, ptd); 1018} 1019 1020static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb) 1021{ 1022 if (usb_pipein(urb->pipe) && usb_pipetype(urb->pipe) != PIPE_CONTROL) { 1023 void *ptr; 1024 1025 for (ptr = urb->transfer_buffer; 1026 ptr < urb->transfer_buffer + urb->transfer_buffer_length; 1027 ptr += PAGE_SIZE) 1028 flush_dcache_range((unsigned long)ptr, 1029 (unsigned long)ptr + PAGE_SIZE); 1030 } 1031 1032 /* complete() can reenter this HCD */ 1033 usb_hcd_unlink_urb_from_ep(hcd, urb); 1034 usb_hcd_giveback_urb(hcd, urb, urb->status); 1035} 1036 1037static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb, 1038 u8 packet_type) 1039{ 1040 struct isp1760_qtd *qtd; 1041 1042 qtd = kmem_cache_alloc(qtd_cachep, flags); 1043 if (!qtd) 1044 return NULL; 1045 1046 memset(qtd, '\0', sizeof(*qtd)); 1047 INIT_LIST_HEAD(&qtd->qtd_list); 1048 qtd->urb = urb; 1049 qtd->packet_type = packet_type; 1050 qtd->status = QTD_ENQUEUED; 1051 qtd->actual_length = 0; 1052 1053 return qtd; 1054} 1055 1056static void qtd_free(struct isp1760_qtd *qtd) 1057{ 1058 WARN_ON(qtd->payload_addr); 1059 kmem_cache_free(qtd_cachep, qtd); 1060} 1061 1062static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot, 1063 struct isp1760_slotinfo *slots, 1064 struct isp1760_qtd *qtd, struct isp1760_qh *qh, 1065 struct ptd *ptd) 1066{ 1067 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1068 const struct isp1760_memory_layout *mem = priv->memory_layout; 1069 int skip_map; 1070 1071 WARN_ON((slot < 0) || (slot > mem->slot_num - 1)); 1072 WARN_ON(qtd->length && !qtd->payload_addr); 1073 WARN_ON(slots[slot].qtd); 1074 WARN_ON(slots[slot].qh); 1075 WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC); 1076 1077 if (priv->is_isp1763) 1078 ndelay(100); 1079 1080 /* Make sure done map has not triggered from some unlinked transfer */ 1081 if (ptd_offset == ATL_PTD_OFFSET) { 1082 skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP); 1083 isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, 1084 skip_map | (1 << slot)); 1085 priv->atl_done_map |= isp1760_hcd_read(hcd, HC_ATL_PTD_DONEMAP); 1086 priv->atl_done_map &= ~(1 << slot); 1087 } else { 1088 skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP); 1089 isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, 1090 skip_map | (1 << slot)); 1091 priv->int_done_map |= isp1760_hcd_read(hcd, HC_INT_PTD_DONEMAP); 1092 priv->int_done_map &= ~(1 << slot); 1093 } 1094 1095 skip_map &= ~(1 << slot); 1096 qh->slot = slot; 1097 qtd->status = QTD_XFER_STARTED; 1098 slots[slot].qtd = qtd; 1099 slots[slot].qh = qh; 1100 1101 ptd_write(hcd, ptd_offset, slot, ptd); 1102 1103 if (ptd_offset == ATL_PTD_OFFSET) 1104 isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, skip_map); 1105 else 1106 isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, skip_map); 1107} 1108 1109static int is_short_bulk(struct isp1760_qtd *qtd) 1110{ 1111 return (usb_pipebulk(qtd->urb->pipe) && 1112 (qtd->actual_length < qtd->length)); 1113} 1114 1115static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh, 1116 struct list_head *urb_list) 1117{ 1118 struct isp1760_qtd *qtd, *qtd_next; 1119 struct urb_listitem *urb_listitem; 1120 int last_qtd; 1121 1122 list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) { 1123 if (qtd->status < QTD_XFER_COMPLETE) 1124 break; 1125 1126 last_qtd = last_qtd_of_urb(qtd, qh); 1127 1128 if (!last_qtd && qtd->status == QTD_RETIRE) 1129 qtd_next->status = QTD_RETIRE; 1130 1131 if (qtd->status == QTD_XFER_COMPLETE) { 1132 if (qtd->actual_length) { 1133 switch (qtd->packet_type) { 1134 case IN_PID: 1135 mem_read(hcd, qtd->payload_addr, 1136 qtd->data_buffer, 1137 qtd->actual_length); 1138 fallthrough; 1139 case OUT_PID: 1140 qtd->urb->actual_length += 1141 qtd->actual_length; 1142 fallthrough; 1143 case SETUP_PID: 1144 break; 1145 } 1146 } 1147 1148 if (is_short_bulk(qtd)) { 1149 if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK) 1150 qtd->urb->status = -EREMOTEIO; 1151 if (!last_qtd) 1152 qtd_next->status = QTD_RETIRE; 1153 } 1154 } 1155 1156 if (qtd->payload_addr) 1157 free_mem(hcd, qtd); 1158 1159 if (last_qtd) { 1160 if (qtd->status == QTD_RETIRE && 1161 qtd->urb->status == -EINPROGRESS) 1162 qtd->urb->status = -EPIPE; 1163 1164 /* Defer calling of urb_done() since it releases lock */ 1165 urb_listitem = kmem_cache_alloc(urb_listitem_cachep, 1166 GFP_ATOMIC); 1167 if (unlikely(!urb_listitem)) 1168 break; /* Try again on next call */ 1169 urb_listitem->urb = qtd->urb; 1170 list_add_tail(&urb_listitem->urb_list, urb_list); 1171 } 1172 1173 list_del(&qtd->qtd_list); 1174 qtd_free(qtd); 1175 } 1176} 1177 1178#define ENQUEUE_DEPTH 2 1179static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh) 1180{ 1181 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1182 const struct isp1760_memory_layout *mem = priv->memory_layout; 1183 int slot_num = mem->slot_num; 1184 int ptd_offset; 1185 struct isp1760_slotinfo *slots; 1186 int curr_slot, free_slot; 1187 int n; 1188 struct ptd ptd; 1189 struct isp1760_qtd *qtd; 1190 1191 if (unlikely(list_empty(&qh->qtd_list))) 1192 return; 1193 1194 /* Make sure this endpoint's TT buffer is clean before queueing ptds */ 1195 if (qh->tt_buffer_dirty) 1196 return; 1197 1198 if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd, 1199 qtd_list)->urb->pipe)) { 1200 ptd_offset = INT_PTD_OFFSET; 1201 slots = priv->int_slots; 1202 } else { 1203 ptd_offset = ATL_PTD_OFFSET; 1204 slots = priv->atl_slots; 1205 } 1206 1207 free_slot = -1; 1208 for (curr_slot = 0; curr_slot < slot_num; curr_slot++) { 1209 if (free_slot == -1 && !slots[curr_slot].qtd) 1210 free_slot = curr_slot; 1211 if (slots[curr_slot].qh == qh) 1212 break; 1213 } 1214 1215 n = 0; 1216 list_for_each_entry(qtd, &qh->qtd_list, qtd_list) { 1217 if (qtd->status == QTD_ENQUEUED) { 1218 WARN_ON(qtd->payload_addr); 1219 alloc_mem(hcd, qtd); 1220 if (qtd->length && !qtd->payload_addr) 1221 break; 1222 1223 if (qtd->length && (qtd->packet_type == SETUP_PID || 1224 qtd->packet_type == OUT_PID)) { 1225 mem_write(hcd, qtd->payload_addr, 1226 qtd->data_buffer, qtd->length); 1227 } 1228 1229 qtd->status = QTD_PAYLOAD_ALLOC; 1230 } 1231 1232 if (qtd->status == QTD_PAYLOAD_ALLOC) { 1233 /* Start xfer for this endpoint if not already done */ 1234 if ((curr_slot > slot_num - 1) && (free_slot > -1)) { 1235 if (usb_pipeint(qtd->urb->pipe)) 1236 create_ptd_int(qh, qtd, &ptd); 1237 else 1238 create_ptd_atl(qh, qtd, &ptd); 1239 1240 start_bus_transfer(hcd, ptd_offset, free_slot, 1241 slots, qtd, qh, &ptd); 1242 curr_slot = free_slot; 1243 } 1244 1245 n++; 1246 if (n >= ENQUEUE_DEPTH) 1247 break; 1248 } 1249 } 1250} 1251 1252static void schedule_ptds(struct usb_hcd *hcd) 1253{ 1254 struct isp1760_hcd *priv; 1255 struct isp1760_qh *qh, *qh_next; 1256 struct list_head *ep_queue; 1257 LIST_HEAD(urb_list); 1258 struct urb_listitem *urb_listitem, *urb_listitem_next; 1259 int i; 1260 1261 if (!hcd) { 1262 WARN_ON(1); 1263 return; 1264 } 1265 1266 priv = hcd_to_priv(hcd); 1267 1268 /* 1269 * check finished/retired xfers, transfer payloads, call urb_done() 1270 */ 1271 for (i = 0; i < QH_END; i++) { 1272 ep_queue = &priv->qh_list[i]; 1273 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) 1274 collect_qtds(hcd, qh, &urb_list); 1275 } 1276 1277 list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list, 1278 urb_list) { 1279 isp1760_urb_done(hcd, urb_listitem->urb); 1280 kmem_cache_free(urb_listitem_cachep, urb_listitem); 1281 } 1282 1283 /* 1284 * Schedule packets for transfer. 1285 * 1286 * According to USB2.0 specification: 1287 * 1288 * 1st prio: interrupt xfers, up to 80 % of bandwidth 1289 * 2nd prio: control xfers 1290 * 3rd prio: bulk xfers 1291 * 1292 * ... but let's use a simpler scheme here (mostly because ISP1761 doc 1293 * is very unclear on how to prioritize traffic): 1294 * 1295 * 1) Enqueue any queued control transfers, as long as payload chip mem 1296 * and PTD ATL slots are available. 1297 * 2) Enqueue any queued INT transfers, as long as payload chip mem 1298 * and PTD INT slots are available. 1299 * 3) Enqueue any queued bulk transfers, as long as payload chip mem 1300 * and PTD ATL slots are available. 1301 * 1302 * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between 1303 * conservation of chip mem and performance. 1304 * 1305 * I'm sure this scheme could be improved upon! 1306 */ 1307 for (i = 0; i < QH_END; i++) { 1308 ep_queue = &priv->qh_list[i]; 1309 list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) 1310 enqueue_qtds(hcd, qh); 1311 } 1312} 1313 1314#define PTD_STATE_QTD_DONE 1 1315#define PTD_STATE_QTD_RELOAD 2 1316#define PTD_STATE_URB_RETIRE 3 1317 1318static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd, 1319 struct urb *urb) 1320{ 1321 u32 dw4; 1322 int i; 1323 1324 dw4 = TO_U32(ptd->dw4); 1325 dw4 >>= 8; 1326 1327 /* 1328 * FIXME: ISP1761 datasheet does not say what to do with these. Do we 1329 * need to handle these errors? Is it done in hardware? 1330 */ 1331 if (ptd->dw3 & DW3_HALT_BIT) { 1332 urb->status = -EPROTO; /* Default unknown error */ 1333 1334 for (i = 0; i < 8; i++) { 1335 switch (dw4 & 0x7) { 1336 case INT_UNDERRUN: 1337 printf("underrun during uFrame %d\n", i); 1338 urb->status = -ECOMM; /* Could not write data */ 1339 break; 1340 case INT_EXACT: 1341 printf("transaction error uFrame %d\n", i); 1342 /* timeout, bad CRC, PID error etc. */ 1343 urb->status = -EPROTO; 1344 break; 1345 case INT_BABBLE: 1346 printf("babble error during uFrame %d\n", i); 1347 urb->status = -EOVERFLOW; 1348 break; 1349 } 1350 dw4 >>= 3; 1351 } 1352 1353 return PTD_STATE_URB_RETIRE; 1354 } 1355 1356 return PTD_STATE_QTD_DONE; 1357} 1358 1359static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd, 1360 struct urb *urb) 1361{ 1362 WARN_ON(!ptd); 1363 if (ptd->dw3 & DW3_HALT_BIT) { 1364 if (ptd->dw3 & DW3_BABBLE_BIT) 1365 urb->status = -EOVERFLOW; 1366 else if (FROM_DW3_CERR(ptd->dw3)) 1367 urb->status = -EPIPE; /* Stall */ 1368 else 1369 urb->status = -EPROTO; /* Unknown */ 1370 1371 /* 1372 * useful debug 1373 * printf("%s: ptd error:\n" 1374 * " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n" 1375 * " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n", 1376 * __func__, 1377 * ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3, 1378 * ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7); 1379 */ 1380 1381 return PTD_STATE_URB_RETIRE; 1382 } 1383 1384 /* Transfer Error, *but* active and no HALT -> reload */ 1385 if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) 1386 return PTD_STATE_QTD_RELOAD; 1387 1388 /* 1389 * NAKs are handled in HW by the chip. Usually if the 1390 * device is not able to send data fast enough. 1391 * This happens mostly on slower hardware. 1392 */ 1393 if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) 1394 return PTD_STATE_QTD_RELOAD; 1395 1396 return PTD_STATE_QTD_DONE; 1397} 1398 1399static void handle_done_ptds(struct usb_hcd *hcd) 1400{ 1401 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1402 struct isp1760_slotinfo *slots; 1403 struct isp1760_qtd *qtd; 1404 struct isp1760_qh *qh; 1405 struct ptd ptd; 1406 u32 ptd_offset; 1407 int modified; 1408 int skip_map; 1409 int state; 1410 int slot; 1411 1412 skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP); 1413 priv->int_done_map &= ~skip_map; 1414 skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP); 1415 priv->atl_done_map &= ~skip_map; 1416 1417 modified = priv->int_done_map || priv->atl_done_map; 1418 1419 while (priv->int_done_map || priv->atl_done_map) { 1420 if (priv->int_done_map) { 1421 /* INT ptd */ 1422 slot = __ffs(priv->int_done_map); 1423 priv->int_done_map &= ~(1 << slot); 1424 slots = priv->int_slots; 1425 /* 1426 * This should not trigger, and could be removed if 1427 * noone have any problems with it triggering: 1428 */ 1429 if (!slots[slot].qh) { 1430 WARN_ON(1); 1431 continue; 1432 } 1433 ptd_offset = INT_PTD_OFFSET; 1434 ptd_read(hcd, INT_PTD_OFFSET, slot, &ptd); 1435 state = check_int_transfer(hcd, &ptd, 1436 slots[slot].qtd->urb); 1437 } else { 1438 /* ATL ptd */ 1439 slot = __ffs(priv->atl_done_map); 1440 priv->atl_done_map &= ~(1 << slot); 1441 slots = priv->atl_slots; 1442 /* 1443 * This should not trigger, and could be removed if 1444 * noone have any problems with it triggering: 1445 */ 1446 if (!slots[slot].qh) { 1447 WARN_ON(1); 1448 continue; 1449 } 1450 ptd_offset = ATL_PTD_OFFSET; 1451 ptd_read(hcd, ATL_PTD_OFFSET, slot, &ptd); 1452 state = check_atl_transfer(hcd, &ptd, 1453 slots[slot].qtd->urb); 1454 } 1455 1456 qtd = slots[slot].qtd; 1457 slots[slot].qtd = NULL; 1458 qh = slots[slot].qh; 1459 slots[slot].qh = NULL; 1460 qh->slot = -1; 1461 1462 WARN_ON(qtd->status != QTD_XFER_STARTED); 1463 1464 switch (state) { 1465 case PTD_STATE_QTD_DONE: 1466 if (usb_pipeint(qtd->urb->pipe) && 1467 qtd->urb->dev->speed != USB_SPEED_HIGH) 1468 qtd->actual_length = 1469 FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3); 1470 else 1471 qtd->actual_length = 1472 FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3); 1473 1474 qtd->status = QTD_XFER_COMPLETE; 1475 1476 if (list_is_last(&qtd->qtd_list, &qh->qtd_list) || 1477 is_short_bulk(qtd)) 1478 qtd = NULL; 1479 else 1480 qtd = list_entry(qtd->qtd_list.next, 1481 typeof(*qtd), qtd_list); 1482 1483 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); 1484 qh->ping = FROM_DW3_PING(ptd.dw3); 1485 1486 break; 1487 1488 case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */ 1489 qtd->status = QTD_PAYLOAD_ALLOC; 1490 ptd.dw0 |= DW0_VALID_BIT; 1491 /* RL counter = ERR counter */ 1492 ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf); 1493 ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2)); 1494 ptd.dw3 &= ~TO_DW3_CERR(3); 1495 ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER); 1496 1497 qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3); 1498 qh->ping = FROM_DW3_PING(ptd.dw3); 1499 break; 1500 1501 case PTD_STATE_URB_RETIRE: 1502 qtd->status = QTD_RETIRE; 1503 qtd = NULL; 1504 qh->toggle = 0; 1505 qh->ping = 0; 1506 break; 1507 1508 default: 1509 WARN_ON(1); 1510 continue; 1511 } 1512 1513 if (qtd && qtd->status == QTD_PAYLOAD_ALLOC) { 1514 if (slots == priv->int_slots) { 1515 if (state == PTD_STATE_QTD_RELOAD) 1516 dev_err(priv->dev, 1517 "PTD_STATE_QTD_RELOAD on interrupt packet\n"); 1518 if (state != PTD_STATE_QTD_RELOAD) 1519 create_ptd_int(qh, qtd, &ptd); 1520 } else { 1521 if (state != PTD_STATE_QTD_RELOAD) 1522 create_ptd_atl(qh, qtd, &ptd); 1523 } 1524 1525 start_bus_transfer(hcd, ptd_offset, slot, slots, qtd, 1526 qh, &ptd); 1527 } 1528 } 1529 1530 if (modified) 1531 schedule_ptds(hcd); 1532} 1533 1534static irqreturn_t isp1760_irq(int irq, void *__hci) 1535{ 1536 struct usb_hcd *hcd = __hci; 1537 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1538 irqreturn_t irqret = IRQ_NONE; 1539 u32 int_reg; 1540 u32 imask; 1541 1542 imask = isp1760_hcd_read(hcd, HC_INTERRUPT); 1543 if (unlikely(!imask)) 1544 return irqret; 1545 1546 int_reg = priv->is_isp1763 ? ISP1763_HC_INTERRUPT : 1547 ISP176x_HC_INTERRUPT; 1548 isp1760_reg_write(priv->regs, int_reg, imask); 1549 1550 priv->int_done_map |= isp1760_hcd_read(hcd, HC_INT_PTD_DONEMAP); 1551 priv->atl_done_map |= isp1760_hcd_read(hcd, HC_ATL_PTD_DONEMAP); 1552 1553 handle_done_ptds(hcd); 1554 1555 irqret = IRQ_HANDLED; 1556 1557 return irqret; 1558} 1559 1560static int isp1763_run(struct usb_hcd *hcd) 1561{ 1562 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1563 int retval; 1564 u32 chipid_h; 1565 u32 chipid_l; 1566 u32 chip_rev; 1567 u32 ptd_atl_int; 1568 u32 ptd_iso; 1569 1570 chipid_h = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH); 1571 chipid_l = isp1760_hcd_read(hcd, HC_CHIP_ID_LOW); 1572 chip_rev = isp1760_hcd_read(hcd, HC_CHIP_REV); 1573 printf("USB ISP %02x%02x HW rev. %d started\n", chipid_h, 1574 chipid_l, chip_rev); 1575 1576 isp1760_hcd_clear(hcd, ISO_BUF_FILL); 1577 isp1760_hcd_clear(hcd, INT_BUF_FILL); 1578 isp1760_hcd_clear(hcd, ATL_BUF_FILL); 1579 1580 isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP); 1581 isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP); 1582 isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP); 1583 ndelay(100); 1584 isp1760_hcd_clear(hcd, HC_ATL_PTD_DONEMAP); 1585 isp1760_hcd_clear(hcd, HC_INT_PTD_DONEMAP); 1586 isp1760_hcd_clear(hcd, HC_ISO_PTD_DONEMAP); 1587 1588 isp1760_hcd_set(hcd, HW_OTG_DISABLE); 1589 isp1760_reg_write(priv->regs, ISP1763_HC_OTG_CTRL_CLEAR, BIT(7)); 1590 isp1760_reg_write(priv->regs, ISP1763_HC_OTG_CTRL_CLEAR, BIT(15)); 1591 mdelay(10); 1592 1593 isp1760_hcd_set(hcd, HC_INT_IRQ_ENABLE); 1594 isp1760_hcd_set(hcd, HC_ATL_IRQ_ENABLE); 1595 1596 isp1760_hcd_set(hcd, HW_GLOBAL_INTR_EN); 1597 1598 isp1760_hcd_clear(hcd, HC_ATL_IRQ_MASK_AND); 1599 isp1760_hcd_clear(hcd, HC_INT_IRQ_MASK_AND); 1600 isp1760_hcd_clear(hcd, HC_ISO_IRQ_MASK_AND); 1601 1602 isp1760_hcd_set(hcd, HC_ATL_IRQ_MASK_OR); 1603 isp1760_hcd_set(hcd, HC_INT_IRQ_MASK_OR); 1604 isp1760_hcd_set(hcd, HC_ISO_IRQ_MASK_OR); 1605 1606 ptd_atl_int = 0x8000; 1607 ptd_iso = 0x0001; 1608 1609 isp1760_hcd_write(hcd, HC_ATL_PTD_LASTPTD, ptd_atl_int); 1610 isp1760_hcd_write(hcd, HC_INT_PTD_LASTPTD, ptd_atl_int); 1611 isp1760_hcd_write(hcd, HC_ISO_PTD_LASTPTD, ptd_iso); 1612 1613 isp1760_hcd_set(hcd, ATL_BUF_FILL); 1614 isp1760_hcd_set(hcd, INT_BUF_FILL); 1615 1616 isp1760_hcd_clear(hcd, CMD_LRESET); 1617 isp1760_hcd_clear(hcd, CMD_RESET); 1618 1619 retval = isp1760_hcd_set_and_wait(hcd, CMD_RUN, 250 * 1000); 1620 if (retval) 1621 return retval; 1622 1623 down_write(&ehci_cf_port_reset_rwsem); 1624 retval = isp1760_hcd_set_and_wait(hcd, FLAG_CF, 250 * 1000); 1625 up_write(&ehci_cf_port_reset_rwsem); 1626 if (retval) 1627 return retval; 1628 1629 return 0; 1630} 1631 1632static int isp1760_run(struct usb_hcd *hcd) 1633{ 1634 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1635 int retval; 1636 u32 chipid_h; 1637 u32 chipid_l; 1638 u32 chip_rev; 1639 u32 ptd_atl_int; 1640 u32 ptd_iso; 1641 1642 /* 1643 * ISP1763 have some differences in the setup and order to enable 1644 * the ports, disable otg, setup buffers, and ATL, INT, ISO status. 1645 * So, just handle it a separate sequence. 1646 */ 1647 if (priv->is_isp1763) 1648 return isp1763_run(hcd); 1649 1650 /* Set PTD interrupt AND & OR maps */ 1651 isp1760_hcd_clear(hcd, HC_ATL_IRQ_MASK_AND); 1652 isp1760_hcd_clear(hcd, HC_INT_IRQ_MASK_AND); 1653 isp1760_hcd_clear(hcd, HC_ISO_IRQ_MASK_AND); 1654 1655 isp1760_hcd_set(hcd, HC_ATL_IRQ_MASK_OR); 1656 isp1760_hcd_set(hcd, HC_INT_IRQ_MASK_OR); 1657 isp1760_hcd_set(hcd, HC_ISO_IRQ_MASK_OR); 1658 1659 /* step 23 passed */ 1660 1661 isp1760_hcd_set(hcd, HW_GLOBAL_INTR_EN); 1662 1663 isp1760_hcd_clear(hcd, CMD_LRESET); 1664 isp1760_hcd_clear(hcd, CMD_RESET); 1665 1666 retval = isp1760_hcd_set_and_wait(hcd, CMD_RUN, 250 * 1000); 1667 if (retval) 1668 return retval; 1669 1670 /* 1671 * XXX 1672 * Spec says to write FLAG_CF as last config action, priv code grabs 1673 * the semaphore while doing so. 1674 */ 1675 down_write(&ehci_cf_port_reset_rwsem); 1676 1677 retval = isp1760_hcd_set_and_wait(hcd, FLAG_CF, 250 * 1000); 1678 up_write(&ehci_cf_port_reset_rwsem); 1679 if (retval) 1680 return retval; 1681 1682 chipid_h = isp1760_hcd_read(hcd, HC_CHIP_ID_HIGH); 1683 chipid_l = isp1760_hcd_read(hcd, HC_CHIP_ID_LOW); 1684 chip_rev = isp1760_hcd_read(hcd, HC_CHIP_REV); 1685 dev_info(priv->dev, "USB ISP %02x%02x HW rev. %d started\n", 1686 chipid_h, chipid_l, chip_rev); 1687 1688 /* PTD Register Init Part 2, Step 28 */ 1689 1690 /* Setup registers controlling PTD checking */ 1691 ptd_atl_int = 0x80000000; 1692 ptd_iso = 0x00000001; 1693 1694 isp1760_hcd_write(hcd, HC_ATL_PTD_LASTPTD, ptd_atl_int); 1695 isp1760_hcd_write(hcd, HC_INT_PTD_LASTPTD, ptd_atl_int); 1696 isp1760_hcd_write(hcd, HC_ISO_PTD_LASTPTD, ptd_iso); 1697 1698 isp1760_hcd_set(hcd, HC_ATL_PTD_SKIPMAP); 1699 isp1760_hcd_set(hcd, HC_INT_PTD_SKIPMAP); 1700 isp1760_hcd_set(hcd, HC_ISO_PTD_SKIPMAP); 1701 1702 isp1760_hcd_set(hcd, ATL_BUF_FILL); 1703 isp1760_hcd_set(hcd, INT_BUF_FILL); 1704 1705 /* GRR this is run-once init(), being done every time the HC starts. 1706 * So long as they're part of class devices, we can't do it init() 1707 * since the class device isn't created that early. 1708 */ 1709 return 0; 1710} 1711 1712static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len) 1713{ 1714 qtd->data_buffer = databuffer; 1715 1716 qtd->length = len; 1717 1718 return qtd->length; 1719} 1720 1721static void qtd_list_free(struct list_head *qtd_list) 1722{ 1723 struct isp1760_qtd *qtd, *qtd_next; 1724 1725 list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) { 1726 list_del(&qtd->qtd_list); 1727 qtd_free(qtd); 1728 } 1729} 1730 1731/* 1732 * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize. 1733 * Also calculate the PID type (SETUP/IN/OUT) for each packet. 1734 */ 1735#define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) 1736static void packetize_urb(struct usb_hcd *hcd, struct urb *urb, 1737 struct list_head *head, gfp_t flags) 1738{ 1739 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1740 const struct isp1760_memory_layout *mem = priv->memory_layout; 1741 struct isp1760_qtd *qtd; 1742 void *buf; 1743 int len, maxpacketsize; 1744 u8 packet_type; 1745 1746 /* 1747 * URBs map to sequences of QTDs: one logical transaction 1748 */ 1749 1750 if (!urb->transfer_buffer && urb->transfer_buffer_length) { 1751 /* XXX This looks like usb storage / SCSI bug */ 1752 dev_err(priv->dev, "buf is null, dma is %08lx len is %d\n", 1753 (unsigned long)urb->transfer_dma, 1754 urb->transfer_buffer_length); 1755 WARN_ON(1); 1756 } 1757 1758 if (usb_pipein(urb->pipe)) 1759 packet_type = IN_PID; 1760 else 1761 packet_type = OUT_PID; 1762 1763 if (usb_pipecontrol(urb->pipe)) { 1764 qtd = qtd_alloc(flags, urb, SETUP_PID); 1765 if (!qtd) 1766 goto cleanup; 1767 qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest)); 1768 list_add_tail(&qtd->qtd_list, head); 1769 1770 /* for zero length DATA stages, STATUS is always IN */ 1771 if (urb->transfer_buffer_length == 0) 1772 packet_type = IN_PID; 1773 } 1774 1775 maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe)); 1776 1777 /* 1778 * buffer gets wrapped in one or more qtds; 1779 * last one may be "short" (including zero len) 1780 * and may serve as a control status ack 1781 */ 1782 buf = urb->transfer_buffer; 1783 len = urb->transfer_buffer_length; 1784 1785 for (;;) { 1786 int this_qtd_len; 1787 1788 qtd = qtd_alloc(flags, urb, packet_type); 1789 if (!qtd) 1790 goto cleanup; 1791 1792 if (len > mem->blocks_size[ISP176x_BLOCK_NUM - 1]) 1793 this_qtd_len = mem->blocks_size[ISP176x_BLOCK_NUM - 1]; 1794 else 1795 this_qtd_len = len; 1796 1797 this_qtd_len = qtd_fill(qtd, buf, this_qtd_len); 1798 list_add_tail(&qtd->qtd_list, head); 1799 1800 len -= this_qtd_len; 1801 buf += this_qtd_len; 1802 1803 if (len <= 0) 1804 break; 1805 } 1806 1807 /* 1808 * control requests may need a terminating data "status" ack; 1809 * bulk ones may need a terminating short packet (zero length). 1810 */ 1811 if (urb->transfer_buffer_length != 0) { 1812 int one_more = 0; 1813 1814 if (usb_pipecontrol(urb->pipe)) { 1815 one_more = 1; 1816 if (packet_type == IN_PID) 1817 packet_type = OUT_PID; 1818 else 1819 packet_type = IN_PID; 1820 } else if (usb_pipebulk(urb->pipe) && maxpacketsize && 1821 (urb->transfer_flags & URB_ZERO_PACKET) && 1822 !(urb->transfer_buffer_length % maxpacketsize)) { 1823 one_more = 1; 1824 } 1825 if (one_more) { 1826 qtd = qtd_alloc(flags, urb, packet_type); 1827 if (!qtd) 1828 goto cleanup; 1829 1830 /* never any data in such packets */ 1831 qtd_fill(qtd, NULL, 0); 1832 list_add_tail(&qtd->qtd_list, head); 1833 } 1834 } 1835 1836 return; 1837 1838cleanup: 1839 qtd_list_free(head); 1840} 1841 1842static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, 1843 gfp_t mem_flags) 1844{ 1845 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1846 struct isp1760_qh *qh = NULL; 1847 struct list_head *ep_queue; 1848 LIST_HEAD(new_qtds); 1849 int qh_in_queue; 1850 int retval; 1851 int epnum; 1852 1853 switch (usb_pipetype(urb->pipe)) { 1854 case PIPE_CONTROL: 1855 ep_queue = &priv->qh_list[QH_CONTROL]; 1856 break; 1857 case PIPE_BULK: 1858 ep_queue = &priv->qh_list[QH_BULK]; 1859 break; 1860 case PIPE_INTERRUPT: 1861 ep_queue = &priv->qh_list[QH_INTERRUPT]; 1862 break; 1863 case PIPE_ISOCHRONOUS: 1864 printf("isochronous USB packets not yet supported\n"); 1865 return -EPIPE; 1866 default: 1867 printf("unknown pipe type\n"); 1868 return -EPIPE; 1869 } 1870 1871 if (usb_pipein(urb->pipe)) 1872 urb->actual_length = 0; 1873 1874 packetize_urb(hcd, urb, &new_qtds, mem_flags); 1875 if (list_empty(&new_qtds)) 1876 return -ENOMEM; 1877 1878 retval = usb_hcd_link_urb_to_ep(hcd, urb); 1879 if (retval) { 1880 qtd_list_free(&new_qtds); 1881 goto out; 1882 } 1883 1884 epnum = usb_pipeendpoint(urb->pipe); 1885 1886 qh_in_queue = 0; 1887 list_for_each_entry(qh, ep_queue, qh_list) { 1888 if (qh->epnum == epnum) { 1889 qh_in_queue = 1; 1890 break; 1891 } 1892 } 1893 1894 if (!qh_in_queue) { 1895 qh = qh_alloc(GFP_ATOMIC); 1896 if (!qh) { 1897 retval = -ENOMEM; 1898 usb_hcd_unlink_urb_from_ep(hcd, urb); 1899 qtd_list_free(&new_qtds); 1900 goto out; 1901 } 1902 1903 qh->epnum = epnum; 1904 list_add_tail(&qh->qh_list, ep_queue); 1905 urb->ep->hcpriv = qh; 1906 } 1907 1908 list_splice_tail(&new_qtds, &qh->qtd_list); 1909 schedule_ptds(hcd); 1910 1911out: 1912 return retval; 1913} 1914 1915static void kill_transfer(struct usb_hcd *hcd, struct urb *urb, 1916 struct isp1760_qh *qh) 1917{ 1918 struct isp1760_hcd *priv = hcd_to_priv(hcd); 1919 int skip_map; 1920 1921 WARN_ON(qh->slot == -1); 1922 1923 /* 1924 * We need to forcefully reclaim the slot since some transfers never 1925 * return, e.g. interrupt transfers and NAKed bulk transfers. 1926 */ 1927 if (usb_pipecontrol(urb->pipe) || usb_pipebulk(urb->pipe)) { 1928 if (qh->slot != -1) { 1929 skip_map = isp1760_hcd_read(hcd, HC_ATL_PTD_SKIPMAP); 1930 skip_map |= (1 << qh->slot); 1931 isp1760_hcd_write(hcd, HC_ATL_PTD_SKIPMAP, skip_map); 1932 ndelay(100); 1933 } 1934 priv->atl_slots[qh->slot].qh = NULL; 1935 priv->atl_slots[qh->slot].qtd = NULL; 1936 } else { 1937 if (qh->slot != -1) { 1938 skip_map = isp1760_hcd_read(hcd, HC_INT_PTD_SKIPMAP); 1939 skip_map |= (1 << qh->slot); 1940 isp1760_hcd_write(hcd, HC_INT_PTD_SKIPMAP, skip_map); 1941 } 1942 priv->int_slots[qh->slot].qh = NULL; 1943 priv->int_slots[qh->slot].qtd = NULL; 1944 } 1945 1946 qh->slot = -1; 1947} 1948 1949/* 1950 * Retire the qtds beginning at 'qtd' and belonging all to the same urb, killing 1951 * any active transfer belonging to the urb in the process. 1952 */ 1953static void dequeue_urb_from_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh, 1954 struct isp1760_qtd *qtd) 1955{ 1956 struct urb *urb; 1957 int urb_was_running; 1958 1959 urb = qtd->urb; 1960 urb_was_running = 0; 1961 list_for_each_entry_from(qtd, &qh->qtd_list, qtd_list) { 1962 if (qtd->urb != urb) 1963 break; 1964 1965 if (qtd->status >= QTD_XFER_STARTED) 1966 urb_was_running = 1; 1967 if (last_qtd_of_urb(qtd, qh) && 1968 qtd->status >= QTD_XFER_COMPLETE) 1969 urb_was_running = 0; 1970 1971 if (qtd->status == QTD_XFER_STARTED) 1972 kill_transfer(hcd, urb, qh); 1973 qtd->status = QTD_RETIRE; 1974 } 1975} 1976 1977int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) 1978{ 1979 struct isp1760_qtd *qtd; 1980 struct isp1760_qh *qh; 1981 int retval = 0; 1982 1983 retval = usb_hcd_check_unlink_urb(hcd, urb, status); 1984 if (retval) 1985 goto out; 1986 1987 qh = urb->ep->hcpriv; 1988 if (!qh) { 1989 retval = -EINVAL; 1990 goto out; 1991 } 1992 1993 list_for_each_entry(qtd, &qh->qtd_list, qtd_list) 1994 if (qtd->urb == urb) { 1995 dequeue_urb_from_qtd(hcd, qh, qtd); 1996 list_move(&qtd->qtd_list, &qh->qtd_list); 1997 break; 1998 } 1999 2000 urb->status = status; 2001 schedule_ptds(hcd); 2002 2003out: 2004 return retval; 2005} 2006 2007static void isp1760_hub_descriptor(struct isp1760_hcd *priv, 2008 struct usb_hub_descriptor *desc) 2009{ 2010 int ports; 2011 u16 temp; 2012 2013 ports = isp1760_hcd_n_ports(priv->hcd); 2014 2015 desc->bDescriptorType = USB_DT_HUB; 2016 /* priv 1.0, 2.3.9 says 20ms max */ 2017 desc->bPwrOn2PwrGood = 10; 2018 desc->bHubContrCurrent = 0; 2019 2020 desc->bNbrPorts = ports; 2021 temp = 1 + (ports / 8); 2022 desc->bLength = 7 + 2 * temp; 2023 2024 /* ports removable, and usb 1.0 legacy PortPwrCtrlMask */ 2025 memset(&desc->u.hs.DeviceRemovable[0], 0, temp); 2026 memset(&desc->u.hs.DeviceRemovable[temp], 0xff, temp); 2027 2028 /* per-port overcurrent reporting */ 2029 temp = HUB_CHAR_INDV_PORT_OCPM; 2030 if (isp1760_hcd_ppc_is_set(priv->hcd)) 2031 /* per-port power control */ 2032 temp |= HUB_CHAR_INDV_PORT_LPSM; 2033 else 2034 /* no power switching */ 2035 temp |= HUB_CHAR_NO_LPSM; 2036 desc->wHubCharacteristics = cpu_to_le16(temp); 2037} 2038 2039#define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E) 2040 2041static void check_reset_complete(struct usb_hcd *hcd, int index) 2042{ 2043 if (!(isp1760_hcd_is_set(hcd, PORT_CONNECT))) 2044 return; 2045 2046 /* if reset finished and it's still not enabled -- handoff */ 2047 if (!isp1760_hcd_is_set(hcd, PORT_PE)) { 2048 printf("port %d full speed --> companion\n", index + 1); 2049 2050 isp1760_hcd_set(hcd, PORT_OWNER); 2051 2052 isp1760_hcd_clear(hcd, PORT_CSC); 2053 } else { 2054 printf("port %d high speed\n", index + 1); 2055 } 2056} 2057 2058static int isp1760_hub_control(struct usb_hcd *hcd, struct usb_device *dev, 2059 unsigned long pipe, void *buffer, int length, 2060 struct devrequest *setup) 2061{ 2062 struct isp1760_hcd *priv = hcd_to_priv(hcd); 2063 u16 typeReq, wValue, wIndex; 2064 char *buf = buffer; 2065 void *src = NULL; 2066 int src_len = 0; 2067 int retval = 0; 2068 u32 status; 2069 int ports; 2070 2071 if (!setup) 2072 return -EINVAL; 2073 2074 ports = isp1760_hcd_n_ports(hcd); 2075 2076 typeReq = setup->request | (setup->requesttype << 8); 2077 wValue = le16_to_cpu(setup->value); 2078 wIndex = le16_to_cpu(setup->index); 2079 2080 /* 2081 * FIXME: support SetPortFeatures USB_PORT_FEAT_INDICATOR. 2082 * HCS_INDICATOR may say we can change LEDs to off/amber/green. 2083 * (track current state ourselves) ... blink for diagnostics, 2084 * power, "this is the one", etc. EHCI spec supports this. 2085 */ 2086 2087 switch (typeReq) { 2088 case DeviceOutRequest | USB_REQ_SET_ADDRESS: 2089 break; 2090 case DeviceOutRequest | USB_REQ_SET_CONFIGURATION: 2091 /* Nothing to do */ 2092 break; 2093 case DeviceRequest | USB_REQ_GET_DESCRIPTOR: 2094 switch (wValue & 0xff00) { 2095 case USB_DT_DEVICE << 8: 2096 src = &rh_descriptor.device; 2097 src_len = 0x12; 2098 break; 2099 case USB_DT_CONFIG << 8: 2100 src = &rh_descriptor.config; 2101 src_len = 0x09; 2102 break; 2103 case USB_DT_STRING << 8: 2104 switch (wValue & 0xff) { 2105 case 0: /* Language */ 2106 src = ISP1760_LANGUAGE_DESC; 2107 src_len = 4; 2108 break; 2109 case 1: /* Vendor String */ 2110 src = ISP1760_VENDOR_DESC; 2111 src_len = 14; 2112 break; 2113 case 2: /* Product Name */ 2114 src = ISP1760_PRODUCT_NAME_DESC; 2115 src_len = 42; 2116 break; 2117 default: 2118 goto error; 2119 } 2120 break; 2121 } 2122 break; 2123 case ClearHubFeature: 2124 switch (wValue) { 2125 case C_HUB_LOCAL_POWER: 2126 case C_HUB_OVER_CURRENT: 2127 /* no hub-wide feature/status flags */ 2128 break; 2129 default: 2130 goto error; 2131 } 2132 break; 2133 case ClearPortFeature: 2134 if (!wIndex || wIndex > ports) 2135 goto error; 2136 wIndex--; 2137 2138 /* 2139 * Even if OWNER is set, so the port is owned by the 2140 * companion controller, hub_wq needs to be able to clear 2141 * the port-change status bits (especially 2142 * USB_PORT_STAT_C_CONNECTION). 2143 */ 2144 2145 switch (wValue) { 2146 case USB_PORT_FEAT_ENABLE: 2147 isp1760_hcd_clear(hcd, PORT_PE); 2148 break; 2149 case USB_PORT_FEAT_C_ENABLE: 2150 /* XXX error? */ 2151 break; 2152 case USB_PORT_FEAT_SUSPEND: 2153 if (isp1760_hcd_is_set(hcd, PORT_RESET)) 2154 goto error; 2155 2156 if (isp1760_hcd_is_set(hcd, PORT_SUSPEND)) { 2157 if (!isp1760_hcd_is_set(hcd, PORT_PE)) 2158 goto error; 2159 /* resume signaling for 20 msec */ 2160 isp1760_hcd_clear(hcd, PORT_CSC); 2161 isp1760_hcd_set(hcd, PORT_RESUME); 2162 2163 priv->reset_done = get_timer(0) + 40; 2164 } 2165 break; 2166 case USB_PORT_FEAT_C_SUSPEND: 2167 /* we auto-clear this feature */ 2168 break; 2169 case USB_PORT_FEAT_POWER: 2170 if (isp1760_hcd_ppc_is_set(hcd)) 2171 isp1760_hcd_clear(hcd, PORT_POWER); 2172 break; 2173 case USB_PORT_FEAT_C_CONNECTION: 2174 isp1760_hcd_set(hcd, PORT_CSC); 2175 break; 2176 case USB_PORT_FEAT_C_OVER_CURRENT: 2177 /* XXX error ?*/ 2178 break; 2179 case USB_PORT_FEAT_C_RESET: 2180 /* GetPortStatus clears reset */ 2181 break; 2182 default: 2183 goto error; 2184 } 2185 isp1760_hcd_read(hcd, CMD_RUN); 2186 break; 2187 case GetHubDescriptor: 2188 isp1760_hub_descriptor(priv, (struct usb_hub_descriptor *)buf); 2189 break; 2190 case GetHubStatus: 2191 /* no hub-wide feature/status flags */ 2192 memset(buf, 0, 4); 2193 break; 2194 case GetPortStatus: 2195 if (!wIndex || wIndex > ports) 2196 goto error; 2197 wIndex--; 2198 status = 0; 2199 2200 /* wPortChange bits */ 2201 if (isp1760_hcd_is_set(hcd, PORT_CSC)) 2202 status |= USB_PORT_STAT_C_CONNECTION << 16; 2203 2204 /* whoever resumes must GetPortStatus to complete it!! */ 2205 if (isp1760_hcd_is_set(hcd, PORT_RESUME)) { 2206 status |= USB_PORT_STAT_C_SUSPEND << 16; 2207 2208 if (!priv->reset_done) { 2209 priv->reset_done = get_timer(0) + 20; 2210 } else if (get_timer(0) > priv->reset_done) { 2211 /* stop resume signaling */ 2212 isp1760_hcd_clear(hcd, PORT_CSC); 2213 2214 retval = isp1760_hcd_clear_and_wait(hcd, 2215 PORT_RESUME, 2216 2000); 2217 if (retval != 0) { 2218 printf("port %d resume error %d\n", 2219 wIndex + 1, retval); 2220 goto error; 2221 } 2222 } 2223 } 2224 2225 /* whoever resets must GetPortStatus to complete it!! */ 2226 if (isp1760_hcd_is_set(hcd, PORT_RESET) && 2227 get_timer(0) > priv->reset_done) { 2228 status |= USB_PORT_STAT_C_RESET << 16; 2229 priv->reset_done = 0; 2230 2231 /* force reset to complete */ 2232 /* REVISIT: some hardware needs 550+ usec to clear 2233 * this bit; seems too long to spin routinely... 2234 */ 2235 retval = isp1760_hcd_clear_and_wait(hcd, PORT_RESET, 2236 750); 2237 if (retval != 0) { 2238 printf("port %d reset error %d\n", wIndex + 1, 2239 retval); 2240 goto error; 2241 } 2242 2243 /* see what we found out */ 2244 check_reset_complete(hcd, wIndex); 2245 } 2246 /* 2247 * Even if OWNER is set, there's no harm letting hub_wq 2248 * see the wPortStatus values (they should all be 0 except 2249 * for PORT_POWER anyway). 2250 */ 2251 2252 if (isp1760_hcd_is_set(hcd, PORT_OWNER)) 2253 printf("PORT_OWNER is set\n"); 2254 2255 if (isp1760_hcd_is_set(hcd, PORT_CONNECT)) { 2256 status |= USB_PORT_STAT_CONNECTION; 2257 2258 /* status may be from integrated TT */ 2259 status |= USB_PORT_STAT_HIGH_SPEED; 2260 } 2261 if (isp1760_hcd_is_set(hcd, PORT_PE)) 2262 status |= USB_PORT_STAT_ENABLE; 2263 if (isp1760_hcd_is_set(hcd, PORT_SUSPEND) && 2264 isp1760_hcd_is_set(hcd, PORT_RESUME)) 2265 status |= USB_PORT_STAT_SUSPEND; 2266 if (isp1760_hcd_is_set(hcd, PORT_RESET)) 2267 status |= USB_PORT_STAT_RESET; 2268 if (isp1760_hcd_is_set(hcd, PORT_POWER)) 2269 status |= USB_PORT_STAT_POWER; 2270 2271 put_unaligned(cpu_to_le32(status), (__le32 *)buf); 2272 break; 2273 case SetHubFeature: 2274 switch (wValue) { 2275 case C_HUB_LOCAL_POWER: 2276 case C_HUB_OVER_CURRENT: 2277 /* no hub-wide feature/status flags */ 2278 break; 2279 default: 2280 goto error; 2281 } 2282 break; 2283 case SetPortFeature: 2284 wIndex &= 0xff; 2285 if (!wIndex || wIndex > ports) 2286 goto error; 2287 wIndex--; 2288 2289 if (isp1760_hcd_is_set(hcd, PORT_OWNER)) 2290 break; 2291 2292 switch (wValue) { 2293 case USB_PORT_FEAT_ENABLE: 2294 isp1760_hcd_set(hcd, PORT_PE); 2295 break; 2296 2297 case USB_PORT_FEAT_SUSPEND: 2298 if (!isp1760_hcd_is_set(hcd, PORT_PE) || 2299 isp1760_hcd_is_set(hcd, PORT_RESET)) 2300 goto error; 2301 2302 isp1760_hcd_set(hcd, PORT_SUSPEND); 2303 break; 2304 case USB_PORT_FEAT_POWER: 2305 if (isp1760_hcd_ppc_is_set(hcd)) 2306 isp1760_hcd_set(hcd, PORT_POWER); 2307 break; 2308 case USB_PORT_FEAT_RESET: 2309 if (isp1760_hcd_is_set(hcd, PORT_RESUME)) 2310 goto error; 2311 /* line status bits may report this as low speed, 2312 * which can be fine if this root hub has a 2313 * transaction translator built in. 2314 */ 2315 if ((isp1760_hcd_is_set(hcd, PORT_CONNECT) && 2316 !isp1760_hcd_is_set(hcd, PORT_PE)) && 2317 (isp1760_hcd_read(hcd, PORT_LSTATUS) == 1)) { 2318 isp1760_hcd_set(hcd, PORT_OWNER); 2319 } else { 2320 isp1760_hcd_set(hcd, PORT_RESET); 2321 isp1760_hcd_clear(hcd, PORT_PE); 2322 2323 priv->reset_done = get_timer(0) + 50; 2324 } 2325 break; 2326 default: 2327 goto error; 2328 } 2329 break; 2330 2331 default: 2332 printf("root: unknown request: 0x%0x\n", typeReq); 2333 goto error; 2334 } 2335 2336 if (src_len) { 2337 length = min(src_len, length); 2338 2339 if (src && length > 0) 2340 memcpy(buffer, src, length); 2341 else 2342 printf("zero copy USB descriptor\n"); 2343 } 2344 2345 dev->act_len = length; 2346 dev->status = 0; 2347 2348 return 0; 2349 2350error: 2351 /* "stall" on error */ 2352 dev->act_len = 0; 2353 dev->status = USB_ST_STALLED; 2354 return -EPIPE; 2355} 2356 2357int __init isp1760_init_kmem_once(void) 2358{ 2359 urb_listitem_cachep = kmem_cache_create("isp1760_urb_listitem", 2360 sizeof(struct urb_listitem), 0, 2361 SLAB_TEMPORARY | 2362 SLAB_MEM_SPREAD, NULL); 2363 2364 if (!urb_listitem_cachep) 2365 return -ENOMEM; 2366 2367 qtd_cachep = kmem_cache_create("isp1760_qtd", 2368 sizeof(struct isp1760_qtd), 0, 2369 SLAB_TEMPORARY | SLAB_MEM_SPREAD, NULL); 2370 2371 if (!qtd_cachep) 2372 goto destroy_urb_listitem; 2373 2374 qh_cachep = kmem_cache_create("isp1760_qh", sizeof(struct isp1760_qh), 2375 0, SLAB_TEMPORARY | SLAB_MEM_SPREAD, 2376 NULL); 2377 2378 if (!qh_cachep) 2379 goto destroy_qtd; 2380 2381 return 0; 2382 2383destroy_qtd: 2384 kmem_cache_destroy(qtd_cachep); 2385 2386destroy_urb_listitem: 2387 kmem_cache_destroy(urb_listitem_cachep); 2388 2389 return -ENOMEM; 2390} 2391 2392void isp1760_deinit_kmem_cache(void) 2393{ 2394 kmem_cache_destroy(qtd_cachep); 2395 kmem_cache_destroy(qh_cachep); 2396 kmem_cache_destroy(urb_listitem_cachep); 2397} 2398 2399int isp1760_hcd_lowlevel_init(struct isp1760_hcd *priv) 2400{ 2401 int ret; 2402 2403 ret = isp1760_hc_setup(priv->hcd); 2404 if (ret < 0) 2405 return ret; 2406 2407 ret = isp1760_run(priv->hcd); 2408 if (ret < 0) 2409 return ret; 2410 2411 return 0; 2412} 2413 2414static const struct usb_urb_ops isp1760_urb_ops = { 2415 .urb_enqueue = isp1760_urb_enqueue, 2416 .urb_dequeue = isp1760_urb_dequeue, 2417 .hub_control = isp1760_hub_control, 2418 .isr = isp1760_irq, 2419}; 2420 2421int isp1760_hcd_register(struct isp1760_hcd *priv, struct resource *mem, 2422 int irq, unsigned long irqflags, 2423 struct udevice *dev) 2424{ 2425 const struct isp1760_memory_layout *mem_layout = priv->memory_layout; 2426 struct isp1760_host_data *host = dev_get_priv(dev); 2427 struct usb_hcd *hcd = &host->hcd; 2428 int ret; 2429 2430 priv->hcd = hcd; 2431 2432 hcd->hcd_priv = priv; 2433 2434 priv->hcd = hcd; 2435 2436 hcd->urb_ops = &isp1760_urb_ops; 2437 2438 priv->atl_slots = kcalloc(mem_layout->slot_num, 2439 sizeof(struct isp1760_slotinfo), GFP_KERNEL); 2440 if (!priv->atl_slots) 2441 return -ENOMEM; 2442 2443 priv->int_slots = kcalloc(mem_layout->slot_num, 2444 sizeof(struct isp1760_slotinfo), GFP_KERNEL); 2445 if (!priv->int_slots) { 2446 ret = -ENOMEM; 2447 goto free_atl_slots; 2448 } 2449 2450 host->host_speed = USB_SPEED_HIGH; 2451 2452 init_memory(priv); 2453 2454 return 0; 2455 2456free_atl_slots: 2457 kfree(priv->atl_slots); 2458 2459 return ret; 2460} 2461 2462void isp1760_hcd_unregister(struct isp1760_hcd *priv) 2463{ 2464 struct isp1760_qh *qh, *qh_next; 2465 int i; 2466 2467 for (i = 0; i < QH_END; i++) 2468 list_for_each_entry_safe(qh, qh_next, &priv->qh_list[i], 2469 qh_list) { 2470 qtd_list_free(&qh->qtd_list); 2471 list_del(&qh->qh_list); 2472 qh_free(qh); 2473 } 2474 2475 kfree(priv->atl_slots); 2476 kfree(priv->int_slots); 2477} 2478