1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * CPSW Ethernet Switch Driver 4 * 5 * Copyright (C) 2010-2018 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <common.h> 9#include <command.h> 10#include <cpu_func.h> 11#include <log.h> 12#include <net.h> 13#include <miiphy.h> 14#include <malloc.h> 15#include <net.h> 16#include <netdev.h> 17#include <cpsw.h> 18#include <dm/device_compat.h> 19#include <linux/bitops.h> 20#include <linux/compiler.h> 21#include <linux/errno.h> 22#include <asm/gpio.h> 23#include <asm/io.h> 24#include <phy.h> 25#include <asm/arch/cpu.h> 26#include <dm.h> 27#include <linux/printk.h> 28 29#include "cpsw_mdio.h" 30 31#define BITMASK(bits) (BIT(bits) - 1) 32#define NUM_DESCS (PKTBUFSRX * 2) 33#define PKT_MIN 60 34#define PKT_MAX (1500 + 14 + 4 + 4) 35#define CLEAR_BIT 1 36#define GIGABITEN BIT(7) 37#define FULLDUPLEXEN BIT(0) 38#define MIIEN BIT(15) 39#define CTL_EXT_EN BIT(18) 40/* DMA Registers */ 41#define CPDMA_TXCONTROL 0x004 42#define CPDMA_RXCONTROL 0x014 43#define CPDMA_SOFTRESET 0x01c 44#define CPDMA_RXFREE 0x0e0 45#define CPDMA_TXHDP_VER1 0x100 46#define CPDMA_TXHDP_VER2 0x200 47#define CPDMA_RXHDP_VER1 0x120 48#define CPDMA_RXHDP_VER2 0x220 49#define CPDMA_TXCP_VER1 0x140 50#define CPDMA_TXCP_VER2 0x240 51#define CPDMA_RXCP_VER1 0x160 52#define CPDMA_RXCP_VER2 0x260 53 54/* Descriptor mode bits */ 55#define CPDMA_DESC_SOP BIT(31) 56#define CPDMA_DESC_EOP BIT(30) 57#define CPDMA_DESC_OWNER BIT(29) 58#define CPDMA_DESC_EOQ BIT(28) 59 60/* 61 * This timeout definition is a worst-case ultra defensive measure against 62 * unexpected controller lock ups. Ideally, we should never ever hit this 63 * scenario in practice. 64 */ 65#define CPDMA_TIMEOUT 100 /* msecs */ 66 67struct cpsw_regs { 68 u32 id_ver; 69 u32 control; 70 u32 soft_reset; 71 u32 stat_port_en; 72 u32 ptype; 73}; 74 75struct cpsw_slave_regs { 76 u32 max_blks; 77 u32 blk_cnt; 78 u32 flow_thresh; 79 u32 port_vlan; 80 u32 tx_pri_map; 81#ifdef CONFIG_AM33XX 82 u32 gap_thresh; 83#endif 84 u32 sa_lo; 85 u32 sa_hi; 86}; 87 88struct cpsw_host_regs { 89 u32 max_blks; 90 u32 blk_cnt; 91 u32 flow_thresh; 92 u32 port_vlan; 93 u32 tx_pri_map; 94 u32 cpdma_tx_pri_map; 95 u32 cpdma_rx_chan_map; 96}; 97 98struct cpsw_sliver_regs { 99 u32 id_ver; 100 u32 mac_control; 101 u32 mac_status; 102 u32 soft_reset; 103 u32 rx_maxlen; 104 u32 __reserved_0; 105 u32 rx_pause; 106 u32 tx_pause; 107 u32 __reserved_1; 108 u32 rx_pri_map; 109}; 110 111#define ALE_ENTRY_BITS 68 112#define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32) 113 114/* ALE Registers */ 115#define ALE_CONTROL 0x08 116#define ALE_UNKNOWNVLAN 0x18 117#define ALE_TABLE_CONTROL 0x20 118#define ALE_TABLE 0x34 119#define ALE_PORTCTL 0x40 120 121#define ALE_TABLE_WRITE BIT(31) 122 123#define ALE_TYPE_FREE 0 124#define ALE_TYPE_ADDR 1 125#define ALE_TYPE_VLAN 2 126#define ALE_TYPE_VLAN_ADDR 3 127 128#define ALE_UCAST_PERSISTANT 0 129#define ALE_UCAST_UNTOUCHED 1 130#define ALE_UCAST_OUI 2 131#define ALE_UCAST_TOUCHED 3 132 133#define ALE_MCAST_FWD 0 134#define ALE_MCAST_BLOCK_LEARN_FWD 1 135#define ALE_MCAST_FWD_LEARN 2 136#define ALE_MCAST_FWD_2 3 137 138enum cpsw_ale_port_state { 139 ALE_PORT_STATE_DISABLE = 0x00, 140 ALE_PORT_STATE_BLOCK = 0x01, 141 ALE_PORT_STATE_LEARN = 0x02, 142 ALE_PORT_STATE_FORWARD = 0x03, 143}; 144 145/* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */ 146#define ALE_SECURE 1 147#define ALE_BLOCKED 2 148 149struct cpsw_slave { 150 struct cpsw_slave_regs *regs; 151 struct cpsw_sliver_regs *sliver; 152 int slave_num; 153 u32 mac_control; 154 struct cpsw_slave_data *data; 155}; 156 157struct cpdma_desc { 158 /* hardware fields */ 159 u32 hw_next; 160 u32 hw_buffer; 161 u32 hw_len; 162 u32 hw_mode; 163 /* software fields */ 164 u32 sw_buffer; 165 u32 sw_len; 166}; 167 168struct cpdma_chan { 169 struct cpdma_desc *head, *tail; 170 void *hdp, *cp, *rxfree; 171}; 172 173/* AM33xx SoC specific definitions for the CONTROL port */ 174#define AM33XX_GMII_SEL_MODE_MII 0 175#define AM33XX_GMII_SEL_MODE_RMII 1 176#define AM33XX_GMII_SEL_MODE_RGMII 2 177 178#define AM33XX_GMII_SEL_RGMII1_IDMODE BIT(4) 179#define AM33XX_GMII_SEL_RGMII2_IDMODE BIT(5) 180#define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6) 181#define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7) 182 183#define GMII_SEL_MODE_MASK 0x3 184 185#define desc_write(desc, fld, val) __raw_writel((u32)(val), &(desc)->fld) 186#define desc_read(desc, fld) __raw_readl(&(desc)->fld) 187#define desc_read_ptr(desc, fld) ((void *)__raw_readl(&(desc)->fld)) 188 189#define chan_write(chan, fld, val) __raw_writel((u32)(val), (chan)->fld) 190#define chan_read(chan, fld) __raw_readl((chan)->fld) 191#define chan_read_ptr(chan, fld) ((void *)__raw_readl((chan)->fld)) 192 193#define for_active_slave(slave, priv) \ 194 slave = (priv)->slaves + ((priv)->data)->active_slave; if (slave) 195#define for_each_slave(slave, priv) \ 196 for (slave = (priv)->slaves; slave != (priv)->slaves + \ 197 ((priv)->data)->slaves; slave++) 198 199struct cpsw_priv { 200 struct udevice *dev; 201 struct cpsw_platform_data *data; 202 int host_port; 203 204 struct cpsw_regs *regs; 205 void *dma_regs; 206 struct cpsw_host_regs *host_port_regs; 207 void *ale_regs; 208 209 struct cpdma_desc *descs; 210 struct cpdma_desc *desc_free; 211 struct cpdma_chan rx_chan, tx_chan; 212 213 struct cpsw_slave *slaves; 214 struct phy_device *phydev; 215 struct mii_dev *bus; 216 217 u32 phy_mask; 218}; 219 220static inline int cpsw_ale_get_field(u32 *ale_entry, u32 start, u32 bits) 221{ 222 int idx; 223 224 idx = start / 32; 225 start -= idx * 32; 226 idx = 2 - idx; /* flip */ 227 return (ale_entry[idx] >> start) & BITMASK(bits); 228} 229 230static inline void cpsw_ale_set_field(u32 *ale_entry, u32 start, u32 bits, 231 u32 value) 232{ 233 int idx; 234 235 value &= BITMASK(bits); 236 idx = start / 32; 237 start -= idx * 32; 238 idx = 2 - idx; /* flip */ 239 ale_entry[idx] &= ~(BITMASK(bits) << start); 240 ale_entry[idx] |= (value << start); 241} 242 243#define DEFINE_ALE_FIELD(name, start, bits) \ 244static inline int __maybe_unused cpsw_ale_get_##name(u32 *ale_entry) \ 245{ \ 246 return cpsw_ale_get_field(ale_entry, start, bits); \ 247} \ 248static inline void __maybe_unused cpsw_ale_set_##name(u32 *ale_entry, u32 value) \ 249{ \ 250 cpsw_ale_set_field(ale_entry, start, bits, value); \ 251} 252 253DEFINE_ALE_FIELD(entry_type, 60, 2) 254DEFINE_ALE_FIELD(mcast_state, 62, 2) 255DEFINE_ALE_FIELD(port_mask, 66, 3) 256DEFINE_ALE_FIELD(ucast_type, 62, 2) 257DEFINE_ALE_FIELD(port_num, 66, 2) 258DEFINE_ALE_FIELD(blocked, 65, 1) 259DEFINE_ALE_FIELD(secure, 64, 1) 260DEFINE_ALE_FIELD(mcast, 40, 1) 261 262/* The MAC address field in the ALE entry cannot be macroized as above */ 263static inline void cpsw_ale_get_addr(u32 *ale_entry, u8 *addr) 264{ 265 int i; 266 267 for (i = 0; i < 6; i++) 268 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8); 269} 270 271static inline void cpsw_ale_set_addr(u32 *ale_entry, const u8 *addr) 272{ 273 int i; 274 275 for (i = 0; i < 6; i++) 276 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]); 277} 278 279static int cpsw_ale_read(struct cpsw_priv *priv, int idx, u32 *ale_entry) 280{ 281 int i; 282 283 __raw_writel(idx, priv->ale_regs + ALE_TABLE_CONTROL); 284 285 for (i = 0; i < ALE_ENTRY_WORDS; i++) 286 ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i); 287 288 return idx; 289} 290 291static int cpsw_ale_write(struct cpsw_priv *priv, int idx, u32 *ale_entry) 292{ 293 int i; 294 295 for (i = 0; i < ALE_ENTRY_WORDS; i++) 296 __raw_writel(ale_entry[i], priv->ale_regs + ALE_TABLE + 4 * i); 297 298 __raw_writel(idx | ALE_TABLE_WRITE, priv->ale_regs + ALE_TABLE_CONTROL); 299 300 return idx; 301} 302 303static int cpsw_ale_match_addr(struct cpsw_priv *priv, const u8 *addr) 304{ 305 u32 ale_entry[ALE_ENTRY_WORDS]; 306 int type, idx; 307 308 for (idx = 0; idx < priv->data->ale_entries; idx++) { 309 u8 entry_addr[6]; 310 311 cpsw_ale_read(priv, idx, ale_entry); 312 type = cpsw_ale_get_entry_type(ale_entry); 313 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR) 314 continue; 315 cpsw_ale_get_addr(ale_entry, entry_addr); 316 if (memcmp(entry_addr, addr, 6) == 0) 317 return idx; 318 } 319 return -ENOENT; 320} 321 322static int cpsw_ale_match_free(struct cpsw_priv *priv) 323{ 324 u32 ale_entry[ALE_ENTRY_WORDS]; 325 int type, idx; 326 327 for (idx = 0; idx < priv->data->ale_entries; idx++) { 328 cpsw_ale_read(priv, idx, ale_entry); 329 type = cpsw_ale_get_entry_type(ale_entry); 330 if (type == ALE_TYPE_FREE) 331 return idx; 332 } 333 return -ENOENT; 334} 335 336static int cpsw_ale_find_ageable(struct cpsw_priv *priv) 337{ 338 u32 ale_entry[ALE_ENTRY_WORDS]; 339 int type, idx; 340 341 for (idx = 0; idx < priv->data->ale_entries; idx++) { 342 cpsw_ale_read(priv, idx, ale_entry); 343 type = cpsw_ale_get_entry_type(ale_entry); 344 if (type != ALE_TYPE_ADDR && type != ALE_TYPE_VLAN_ADDR) 345 continue; 346 if (cpsw_ale_get_mcast(ale_entry)) 347 continue; 348 type = cpsw_ale_get_ucast_type(ale_entry); 349 if (type != ALE_UCAST_PERSISTANT && 350 type != ALE_UCAST_OUI) 351 return idx; 352 } 353 return -ENOENT; 354} 355 356static int cpsw_ale_add_ucast(struct cpsw_priv *priv, const u8 *addr, 357 int port, int flags) 358{ 359 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 360 int idx; 361 362 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR); 363 cpsw_ale_set_addr(ale_entry, addr); 364 cpsw_ale_set_ucast_type(ale_entry, ALE_UCAST_PERSISTANT); 365 cpsw_ale_set_secure(ale_entry, (flags & ALE_SECURE) ? 1 : 0); 366 cpsw_ale_set_blocked(ale_entry, (flags & ALE_BLOCKED) ? 1 : 0); 367 cpsw_ale_set_port_num(ale_entry, port); 368 369 idx = cpsw_ale_match_addr(priv, addr); 370 if (idx < 0) 371 idx = cpsw_ale_match_free(priv); 372 if (idx < 0) 373 idx = cpsw_ale_find_ageable(priv); 374 if (idx < 0) 375 return -ENOMEM; 376 377 cpsw_ale_write(priv, idx, ale_entry); 378 return 0; 379} 380 381static int cpsw_ale_add_mcast(struct cpsw_priv *priv, const u8 *addr, 382 int port_mask) 383{ 384 u32 ale_entry[ALE_ENTRY_WORDS] = {0, 0, 0}; 385 int idx, mask; 386 387 idx = cpsw_ale_match_addr(priv, addr); 388 if (idx >= 0) 389 cpsw_ale_read(priv, idx, ale_entry); 390 391 cpsw_ale_set_entry_type(ale_entry, ALE_TYPE_ADDR); 392 cpsw_ale_set_addr(ale_entry, addr); 393 cpsw_ale_set_mcast_state(ale_entry, ALE_MCAST_FWD_2); 394 395 mask = cpsw_ale_get_port_mask(ale_entry); 396 port_mask |= mask; 397 cpsw_ale_set_port_mask(ale_entry, port_mask); 398 399 if (idx < 0) 400 idx = cpsw_ale_match_free(priv); 401 if (idx < 0) 402 idx = cpsw_ale_find_ageable(priv); 403 if (idx < 0) 404 return -ENOMEM; 405 406 cpsw_ale_write(priv, idx, ale_entry); 407 return 0; 408} 409 410static inline void cpsw_ale_control(struct cpsw_priv *priv, int bit, int val) 411{ 412 u32 tmp, mask = BIT(bit); 413 414 tmp = __raw_readl(priv->ale_regs + ALE_CONTROL); 415 tmp &= ~mask; 416 tmp |= val ? mask : 0; 417 __raw_writel(tmp, priv->ale_regs + ALE_CONTROL); 418} 419 420#define cpsw_ale_enable(priv, val) cpsw_ale_control(priv, 31, val) 421#define cpsw_ale_clear(priv, val) cpsw_ale_control(priv, 30, val) 422#define cpsw_ale_vlan_aware(priv, val) cpsw_ale_control(priv, 2, val) 423 424static inline void cpsw_ale_port_state(struct cpsw_priv *priv, int port, 425 int val) 426{ 427 int offset = ALE_PORTCTL + 4 * port; 428 u32 tmp, mask = 0x3; 429 430 tmp = __raw_readl(priv->ale_regs + offset); 431 tmp &= ~mask; 432 tmp |= val & mask; 433 __raw_writel(tmp, priv->ale_regs + offset); 434} 435 436/* Set a self-clearing bit in a register, and wait for it to clear */ 437static inline void setbit_and_wait_for_clear32(void *addr) 438{ 439 __raw_writel(CLEAR_BIT, addr); 440 while (__raw_readl(addr) & CLEAR_BIT) 441 ; 442} 443 444#define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 445 ((mac)[2] << 16) | ((mac)[3] << 24)) 446#define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 447 448static void cpsw_set_slave_mac(struct cpsw_slave *slave, 449 struct cpsw_priv *priv) 450{ 451 struct eth_pdata *pdata = dev_get_plat(priv->dev); 452 453 writel(mac_hi(pdata->enetaddr), &slave->regs->sa_hi); 454 writel(mac_lo(pdata->enetaddr), &slave->regs->sa_lo); 455} 456 457static int cpsw_slave_update_link(struct cpsw_slave *slave, 458 struct cpsw_priv *priv, int *link) 459{ 460 struct phy_device *phy; 461 u32 mac_control = 0; 462 int ret = -ENODEV; 463 464 phy = priv->phydev; 465 if (!phy) 466 goto out; 467 468 ret = phy_startup(phy); 469 if (ret) 470 goto out; 471 472 if (link) 473 *link = phy->link; 474 475 if (phy->link) { /* link up */ 476 mac_control = priv->data->mac_control; 477 if (phy->speed == 1000) 478 mac_control |= GIGABITEN; 479 if (phy->duplex == DUPLEX_FULL) 480 mac_control |= FULLDUPLEXEN; 481 if (phy->speed == 100) 482 mac_control |= MIIEN; 483 if (phy->speed == 10 && phy_interface_is_rgmii(phy)) 484 mac_control |= CTL_EXT_EN; 485 } 486 487 if (mac_control == slave->mac_control) 488 goto out; 489 490 if (mac_control) { 491 printf("link up on port %d, speed %d, %s duplex\n", 492 slave->slave_num, phy->speed, 493 (phy->duplex == DUPLEX_FULL) ? "full" : "half"); 494 } else { 495 printf("link down on port %d\n", slave->slave_num); 496 } 497 498 __raw_writel(mac_control, &slave->sliver->mac_control); 499 slave->mac_control = mac_control; 500 501out: 502 return ret; 503} 504 505static int cpsw_update_link(struct cpsw_priv *priv) 506{ 507 int ret = -ENODEV; 508 struct cpsw_slave *slave; 509 510 for_active_slave(slave, priv) 511 ret = cpsw_slave_update_link(slave, priv, NULL); 512 513 return ret; 514} 515 516static inline u32 cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) 517{ 518 if (priv->host_port == 0) 519 return slave_num + 1; 520 else 521 return slave_num; 522} 523 524static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv) 525{ 526 u32 slave_port; 527 528 setbit_and_wait_for_clear32(&slave->sliver->soft_reset); 529 530 /* setup priority mapping */ 531 __raw_writel(0x76543210, &slave->sliver->rx_pri_map); 532 __raw_writel(0x33221100, &slave->regs->tx_pri_map); 533 534 /* setup max packet size, and mac address */ 535 __raw_writel(PKT_MAX, &slave->sliver->rx_maxlen); 536 cpsw_set_slave_mac(slave, priv); 537 538 slave->mac_control = 0; /* no link yet */ 539 540 /* enable forwarding */ 541 slave_port = cpsw_get_slave_port(priv, slave->slave_num); 542 cpsw_ale_port_state(priv, slave_port, ALE_PORT_STATE_FORWARD); 543 544 cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << slave_port); 545 546 priv->phy_mask |= 1 << slave->data->phy_addr; 547} 548 549static struct cpdma_desc *cpdma_desc_alloc(struct cpsw_priv *priv) 550{ 551 struct cpdma_desc *desc = priv->desc_free; 552 553 if (desc) 554 priv->desc_free = desc_read_ptr(desc, hw_next); 555 return desc; 556} 557 558static void cpdma_desc_free(struct cpsw_priv *priv, struct cpdma_desc *desc) 559{ 560 if (desc) { 561 desc_write(desc, hw_next, priv->desc_free); 562 priv->desc_free = desc; 563 } 564} 565 566static int cpdma_submit(struct cpsw_priv *priv, struct cpdma_chan *chan, 567 void *buffer, int len) 568{ 569 struct cpdma_desc *desc, *prev; 570 u32 mode; 571 572 desc = cpdma_desc_alloc(priv); 573 if (!desc) 574 return -ENOMEM; 575 576 if (len < PKT_MIN) 577 len = PKT_MIN; 578 579 mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP; 580 581 desc_write(desc, hw_next, 0); 582 desc_write(desc, hw_buffer, buffer); 583 desc_write(desc, hw_len, len); 584 desc_write(desc, hw_mode, mode | len); 585 desc_write(desc, sw_buffer, buffer); 586 desc_write(desc, sw_len, len); 587 588 if (!chan->head) { 589 /* simple case - first packet enqueued */ 590 chan->head = desc; 591 chan->tail = desc; 592 chan_write(chan, hdp, desc); 593 goto done; 594 } 595 596 /* not the first packet - enqueue at the tail */ 597 prev = chan->tail; 598 desc_write(prev, hw_next, desc); 599 chan->tail = desc; 600 601 /* next check if EOQ has been triggered already */ 602 if (desc_read(prev, hw_mode) & CPDMA_DESC_EOQ) 603 chan_write(chan, hdp, desc); 604 605done: 606 if (chan->rxfree) 607 chan_write(chan, rxfree, 1); 608 return 0; 609} 610 611static int cpdma_process(struct cpsw_priv *priv, struct cpdma_chan *chan, 612 void **buffer, int *len) 613{ 614 struct cpdma_desc *desc = chan->head; 615 u32 status; 616 617 if (!desc) 618 return -ENOENT; 619 620 status = desc_read(desc, hw_mode); 621 622 if (len) 623 *len = status & 0x7ff; 624 625 if (buffer) 626 *buffer = desc_read_ptr(desc, sw_buffer); 627 628 if (status & CPDMA_DESC_OWNER) { 629 if (chan_read(chan, hdp) == 0) { 630 if (desc_read(desc, hw_mode) & CPDMA_DESC_OWNER) 631 chan_write(chan, hdp, desc); 632 } 633 634 return -EBUSY; 635 } 636 637 chan->head = desc_read_ptr(desc, hw_next); 638 chan_write(chan, cp, desc); 639 640 cpdma_desc_free(priv, desc); 641 return 0; 642} 643 644static int _cpsw_init(struct cpsw_priv *priv, u8 *enetaddr) 645{ 646 struct cpsw_slave *slave; 647 int i, ret; 648 649 /* soft reset the controller and initialize priv */ 650 setbit_and_wait_for_clear32(&priv->regs->soft_reset); 651 652 /* initialize and reset the address lookup engine */ 653 cpsw_ale_enable(priv, 1); 654 cpsw_ale_clear(priv, 1); 655 cpsw_ale_vlan_aware(priv, 0); /* vlan unaware mode */ 656 657 /* setup host port priority mapping */ 658 __raw_writel(0x76543210, &priv->host_port_regs->cpdma_tx_pri_map); 659 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); 660 661 /* disable priority elevation and enable statistics on all ports */ 662 __raw_writel(0, &priv->regs->ptype); 663 664 /* enable statistics collection only on the host port */ 665 __raw_writel(BIT(priv->host_port), &priv->regs->stat_port_en); 666 __raw_writel(0x7, &priv->regs->stat_port_en); 667 668 cpsw_ale_port_state(priv, priv->host_port, ALE_PORT_STATE_FORWARD); 669 670 cpsw_ale_add_ucast(priv, enetaddr, priv->host_port, ALE_SECURE); 671 cpsw_ale_add_mcast(priv, net_bcast_ethaddr, 1 << priv->host_port); 672 673 for_active_slave(slave, priv) 674 cpsw_slave_init(slave, priv); 675 676 ret = cpsw_update_link(priv); 677 if (ret) 678 goto out; 679 680 /* init descriptor pool */ 681 for (i = 0; i < NUM_DESCS; i++) { 682 desc_write(&priv->descs[i], hw_next, 683 (i == (NUM_DESCS - 1)) ? 0 : &priv->descs[i+1]); 684 } 685 priv->desc_free = &priv->descs[0]; 686 687 /* initialize channels */ 688 if (priv->data->version == CPSW_CTRL_VERSION_2) { 689 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan)); 690 priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER2; 691 priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER2; 692 priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE; 693 694 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan)); 695 priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER2; 696 priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER2; 697 } else { 698 memset(&priv->rx_chan, 0, sizeof(struct cpdma_chan)); 699 priv->rx_chan.hdp = priv->dma_regs + CPDMA_RXHDP_VER1; 700 priv->rx_chan.cp = priv->dma_regs + CPDMA_RXCP_VER1; 701 priv->rx_chan.rxfree = priv->dma_regs + CPDMA_RXFREE; 702 703 memset(&priv->tx_chan, 0, sizeof(struct cpdma_chan)); 704 priv->tx_chan.hdp = priv->dma_regs + CPDMA_TXHDP_VER1; 705 priv->tx_chan.cp = priv->dma_regs + CPDMA_TXCP_VER1; 706 } 707 708 /* clear dma state */ 709 setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET); 710 711 if (priv->data->version == CPSW_CTRL_VERSION_2) { 712 for (i = 0; i < priv->data->channels; i++) { 713 __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER2 + 4 714 * i); 715 __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 716 * i); 717 __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER2 + 4 718 * i); 719 __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER2 + 4 720 * i); 721 __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER2 + 4 722 * i); 723 } 724 } else { 725 for (i = 0; i < priv->data->channels; i++) { 726 __raw_writel(0, priv->dma_regs + CPDMA_RXHDP_VER1 + 4 727 * i); 728 __raw_writel(0, priv->dma_regs + CPDMA_RXFREE + 4 729 * i); 730 __raw_writel(0, priv->dma_regs + CPDMA_RXCP_VER1 + 4 731 * i); 732 __raw_writel(0, priv->dma_regs + CPDMA_TXHDP_VER1 + 4 733 * i); 734 __raw_writel(0, priv->dma_regs + CPDMA_TXCP_VER1 + 4 735 * i); 736 737 } 738 } 739 740 __raw_writel(1, priv->dma_regs + CPDMA_TXCONTROL); 741 __raw_writel(1, priv->dma_regs + CPDMA_RXCONTROL); 742 743 /* submit rx descs */ 744 for (i = 0; i < PKTBUFSRX; i++) { 745 ret = cpdma_submit(priv, &priv->rx_chan, net_rx_packets[i], 746 PKTSIZE); 747 if (ret < 0) { 748 printf("error %d submitting rx desc\n", ret); 749 break; 750 } 751 } 752 753out: 754 return ret; 755} 756 757static int cpsw_reap_completed_packets(struct cpsw_priv *priv) 758{ 759 int timeout = CPDMA_TIMEOUT; 760 761 /* reap completed packets */ 762 while (timeout-- && 763 (cpdma_process(priv, &priv->tx_chan, NULL, NULL) >= 0)) 764 ; 765 766 return timeout; 767} 768 769static void _cpsw_halt(struct cpsw_priv *priv) 770{ 771 cpsw_reap_completed_packets(priv); 772 773 writel(0, priv->dma_regs + CPDMA_TXCONTROL); 774 writel(0, priv->dma_regs + CPDMA_RXCONTROL); 775 776 /* soft reset the controller and initialize priv */ 777 setbit_and_wait_for_clear32(&priv->regs->soft_reset); 778 779 /* clear dma state */ 780 setbit_and_wait_for_clear32(priv->dma_regs + CPDMA_SOFTRESET); 781 782} 783 784static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length) 785{ 786 int timeout; 787 788 flush_dcache_range((unsigned long)packet, 789 (unsigned long)packet + ALIGN(length, PKTALIGN)); 790 791 timeout = cpsw_reap_completed_packets(priv); 792 if (timeout == -1) { 793 printf("cpdma_process timeout\n"); 794 return -ETIMEDOUT; 795 } 796 797 return cpdma_submit(priv, &priv->tx_chan, packet, length); 798} 799 800static int _cpsw_recv(struct cpsw_priv *priv, uchar **pkt) 801{ 802 void *buffer; 803 int len; 804 int ret; 805 806 ret = cpdma_process(priv, &priv->rx_chan, &buffer, &len); 807 if (ret < 0) 808 return ret; 809 810 invalidate_dcache_range((unsigned long)buffer, 811 (unsigned long)buffer + PKTSIZE_ALIGN); 812 *pkt = buffer; 813 814 return len; 815} 816 817static void cpsw_slave_setup(struct cpsw_slave *slave, int slave_num, 818 struct cpsw_priv *priv) 819{ 820 void *regs = priv->regs; 821 struct cpsw_slave_data *data = priv->data->slave_data + slave_num; 822 slave->slave_num = slave_num; 823 slave->data = data; 824 slave->regs = regs + data->slave_reg_ofs; 825 slave->sliver = regs + data->sliver_reg_ofs; 826} 827 828static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave) 829{ 830 struct phy_device *phydev; 831 u32 supported = PHY_GBIT_FEATURES; 832 int ret; 833 834 phydev = phy_connect(priv->bus, 835 slave->data->phy_addr, 836 priv->dev, 837 slave->data->phy_if); 838 839 if (!phydev) 840 return -1; 841 842 phydev->supported &= supported; 843 if (slave->data->max_speed) { 844 ret = phy_set_supported(phydev, slave->data->max_speed); 845 if (ret) 846 return ret; 847 dev_dbg(priv->dev, "Port %u speed forced to %uMbit\n", 848 slave->slave_num + 1, slave->data->max_speed); 849 } 850 phydev->advertising = phydev->supported; 851 852 if (ofnode_valid(slave->data->phy_of_handle)) 853 phydev->node = slave->data->phy_of_handle; 854 855 priv->phydev = phydev; 856 phy_config(phydev); 857 858 return 1; 859} 860 861static void cpsw_phy_addr_update(struct cpsw_priv *priv) 862{ 863 struct cpsw_platform_data *data = priv->data; 864 u16 alive = cpsw_mdio_get_alive(priv->bus); 865 int active = data->active_slave; 866 int new_addr = ffs(alive) - 1; 867 868 /* 869 * If there is only one phy alive and its address does not match 870 * that of active slave, then phy address can safely be updated. 871 */ 872 if (hweight16(alive) == 1 && 873 data->slave_data[active].phy_addr != new_addr) { 874 printf("Updated phy address for CPSW#%d, old: %d, new: %d\n", 875 active, data->slave_data[active].phy_addr, new_addr); 876 data->slave_data[active].phy_addr = new_addr; 877 } 878} 879 880int _cpsw_register(struct cpsw_priv *priv) 881{ 882 struct cpsw_slave *slave; 883 struct cpsw_platform_data *data = priv->data; 884 void *regs = (void *)data->cpsw_base; 885 886 priv->slaves = malloc(sizeof(struct cpsw_slave) * data->slaves); 887 if (!priv->slaves) { 888 return -ENOMEM; 889 } 890 891 priv->host_port = data->host_port_num; 892 priv->regs = regs; 893 priv->host_port_regs = regs + data->host_port_reg_ofs; 894 priv->dma_regs = regs + data->cpdma_reg_ofs; 895 priv->ale_regs = regs + data->ale_reg_ofs; 896 priv->descs = (void *)regs + data->bd_ram_ofs; 897 898 int idx = 0; 899 900 for_each_slave(slave, priv) { 901 cpsw_slave_setup(slave, idx, priv); 902 idx = idx + 1; 903 } 904 905 priv->bus = cpsw_mdio_init(priv->dev->name, data->mdio_base, 0, 0, 906 false); 907 if (!priv->bus) 908 return -EFAULT; 909 910 cpsw_phy_addr_update(priv); 911 912 for_active_slave(slave, priv) 913 cpsw_phy_init(priv, slave); 914 915 return 0; 916} 917 918static int cpsw_eth_start(struct udevice *dev) 919{ 920 struct eth_pdata *pdata = dev_get_plat(dev); 921 struct cpsw_priv *priv = dev_get_priv(dev); 922 923 return _cpsw_init(priv, pdata->enetaddr); 924} 925 926static int cpsw_eth_send(struct udevice *dev, void *packet, int length) 927{ 928 struct cpsw_priv *priv = dev_get_priv(dev); 929 930 return _cpsw_send(priv, packet, length); 931} 932 933static int cpsw_eth_recv(struct udevice *dev, int flags, uchar **packetp) 934{ 935 struct cpsw_priv *priv = dev_get_priv(dev); 936 937 return _cpsw_recv(priv, packetp); 938} 939 940static int cpsw_eth_free_pkt(struct udevice *dev, uchar *packet, 941 int length) 942{ 943 struct cpsw_priv *priv = dev_get_priv(dev); 944 945 return cpdma_submit(priv, &priv->rx_chan, packet, PKTSIZE); 946} 947 948static void cpsw_eth_stop(struct udevice *dev) 949{ 950 struct cpsw_priv *priv = dev_get_priv(dev); 951 952 return _cpsw_halt(priv); 953} 954 955static const struct eth_ops cpsw_eth_ops = { 956 .start = cpsw_eth_start, 957 .send = cpsw_eth_send, 958 .recv = cpsw_eth_recv, 959 .free_pkt = cpsw_eth_free_pkt, 960 .stop = cpsw_eth_stop, 961}; 962 963static void cpsw_gmii_sel_am3352(struct cpsw_priv *priv, 964 phy_interface_t phy_mode) 965{ 966 u32 reg; 967 u32 mask; 968 u32 mode = 0; 969 bool rgmii_id = false; 970 int slave = priv->data->active_slave; 971 972 reg = readl(priv->data->gmii_sel); 973 974 switch (phy_mode) { 975 case PHY_INTERFACE_MODE_RMII: 976 mode = AM33XX_GMII_SEL_MODE_RMII; 977 break; 978 979 case PHY_INTERFACE_MODE_RGMII: 980 case PHY_INTERFACE_MODE_RGMII_RXID: 981 mode = AM33XX_GMII_SEL_MODE_RGMII; 982 break; 983 case PHY_INTERFACE_MODE_RGMII_ID: 984 case PHY_INTERFACE_MODE_RGMII_TXID: 985 mode = AM33XX_GMII_SEL_MODE_RGMII; 986 rgmii_id = true; 987 break; 988 989 case PHY_INTERFACE_MODE_MII: 990 default: 991 mode = AM33XX_GMII_SEL_MODE_MII; 992 break; 993 }; 994 995 mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6); 996 mode <<= slave * 2; 997 998 if (priv->data->rmii_clock_external) { 999 if (slave == 0) 1000 mode |= AM33XX_GMII_SEL_RMII1_IO_CLK_EN; 1001 else 1002 mode |= AM33XX_GMII_SEL_RMII2_IO_CLK_EN; 1003 } 1004 1005 if (rgmii_id) { 1006 if (slave == 0) 1007 mode |= AM33XX_GMII_SEL_RGMII1_IDMODE; 1008 else 1009 mode |= AM33XX_GMII_SEL_RGMII2_IDMODE; 1010 } 1011 1012 reg &= ~mask; 1013 reg |= mode; 1014 1015 writel(reg, priv->data->gmii_sel); 1016} 1017 1018static void cpsw_gmii_sel_dra7xx(struct cpsw_priv *priv, 1019 phy_interface_t phy_mode) 1020{ 1021 u32 reg; 1022 u32 mask; 1023 u32 mode = 0; 1024 int slave = priv->data->active_slave; 1025 1026 reg = readl(priv->data->gmii_sel); 1027 1028 switch (phy_mode) { 1029 case PHY_INTERFACE_MODE_RMII: 1030 mode = AM33XX_GMII_SEL_MODE_RMII; 1031 break; 1032 1033 case PHY_INTERFACE_MODE_RGMII: 1034 case PHY_INTERFACE_MODE_RGMII_ID: 1035 case PHY_INTERFACE_MODE_RGMII_RXID: 1036 case PHY_INTERFACE_MODE_RGMII_TXID: 1037 mode = AM33XX_GMII_SEL_MODE_RGMII; 1038 break; 1039 1040 case PHY_INTERFACE_MODE_MII: 1041 default: 1042 mode = AM33XX_GMII_SEL_MODE_MII; 1043 break; 1044 }; 1045 1046 switch (slave) { 1047 case 0: 1048 mask = GMII_SEL_MODE_MASK; 1049 break; 1050 case 1: 1051 mask = GMII_SEL_MODE_MASK << 4; 1052 mode <<= 4; 1053 break; 1054 default: 1055 dev_err(priv->dev, "invalid slave number...\n"); 1056 return; 1057 } 1058 1059 if (priv->data->rmii_clock_external) 1060 dev_err(priv->dev, "RMII External clock is not supported\n"); 1061 1062 reg &= ~mask; 1063 reg |= mode; 1064 1065 writel(reg, priv->data->gmii_sel); 1066} 1067 1068static void cpsw_phy_sel(struct cpsw_priv *priv, const char *compat, 1069 phy_interface_t phy_mode) 1070{ 1071 if (!strcmp(compat, "ti,am3352-cpsw-phy-sel")) 1072 cpsw_gmii_sel_am3352(priv, phy_mode); 1073 if (!strcmp(compat, "ti,am43xx-cpsw-phy-sel")) 1074 cpsw_gmii_sel_am3352(priv, phy_mode); 1075 else if (!strcmp(compat, "ti,dra7xx-cpsw-phy-sel")) 1076 cpsw_gmii_sel_dra7xx(priv, phy_mode); 1077} 1078 1079static int cpsw_eth_probe(struct udevice *dev) 1080{ 1081 struct cpsw_priv *priv = dev_get_priv(dev); 1082 struct eth_pdata *pdata = dev_get_plat(dev); 1083 1084 priv->dev = dev; 1085 priv->data = pdata->priv_pdata; 1086 ti_cm_get_macid(dev, priv->data, pdata->enetaddr); 1087 /* Select phy interface in control module */ 1088 cpsw_phy_sel(priv, priv->data->phy_sel_compat, 1089 pdata->phy_interface); 1090 1091 return _cpsw_register(priv); 1092} 1093 1094#if CONFIG_IS_ENABLED(OF_CONTROL) 1095static void cpsw_eth_of_parse_slave(struct cpsw_platform_data *data, 1096 int slave_index, ofnode subnode) 1097{ 1098 struct ofnode_phandle_args out_args; 1099 struct cpsw_slave_data *slave_data; 1100 u32 phy_id[2]; 1101 int ret; 1102 1103 slave_data = &data->slave_data[slave_index]; 1104 1105 slave_data->phy_if = ofnode_read_phy_mode(subnode); 1106 1107 ret = ofnode_parse_phandle_with_args(subnode, "phy-handle", 1108 NULL, 0, 0, &out_args); 1109 if (!ret) { 1110 slave_data->phy_of_handle = out_args.node; 1111 1112 ret = ofnode_read_s32(slave_data->phy_of_handle, "reg", 1113 &slave_data->phy_addr); 1114 if (ret) 1115 printf("error: phy addr not found in dt\n"); 1116 } else { 1117 ret = ofnode_read_u32_array(subnode, "phy_id", phy_id, 2); 1118 if (ret) 1119 printf("error: phy_id read failed\n"); 1120 } 1121 1122 slave_data->max_speed = ofnode_read_s32_default(subnode, 1123 "max-speed", 0); 1124} 1125 1126static int cpsw_eth_of_to_plat(struct udevice *dev) 1127{ 1128 struct eth_pdata *pdata = dev_get_plat(dev); 1129 struct cpsw_platform_data *data; 1130 struct gpio_desc *mode_gpios; 1131 int slave_index = 0; 1132 int num_mode_gpios; 1133 ofnode subnode; 1134 int ret; 1135 1136 data = calloc(1, sizeof(struct cpsw_platform_data)); 1137 if (!data) 1138 return -ENOMEM; 1139 1140 pdata->priv_pdata = data; 1141 pdata->iobase = dev_read_addr(dev); 1142 data->version = CPSW_CTRL_VERSION_2; 1143 data->bd_ram_ofs = CPSW_BD_OFFSET; 1144 data->ale_reg_ofs = CPSW_ALE_OFFSET; 1145 data->cpdma_reg_ofs = CPSW_CPDMA_OFFSET; 1146 data->mdio_div = CPSW_MDIO_DIV; 1147 data->host_port_reg_ofs = CPSW_HOST_PORT_OFFSET, 1148 1149 pdata->phy_interface = -1; 1150 1151 data->cpsw_base = pdata->iobase; 1152 1153 ret = dev_read_s32(dev, "cpdma_channels", &data->channels); 1154 if (ret) { 1155 printf("error: cpdma_channels not found in dt\n"); 1156 return ret; 1157 } 1158 1159 ret = dev_read_s32(dev, "slaves", &data->slaves); 1160 if (ret) { 1161 printf("error: slaves not found in dt\n"); 1162 return ret; 1163 } 1164 data->slave_data = malloc(sizeof(struct cpsw_slave_data) * 1165 data->slaves); 1166 1167 ret = dev_read_s32(dev, "ale_entries", &data->ale_entries); 1168 if (ret) { 1169 printf("error: ale_entries not found in dt\n"); 1170 return ret; 1171 } 1172 1173 ret = dev_read_u32(dev, "bd_ram_size", &data->bd_ram_ofs); 1174 if (ret) { 1175 printf("error: bd_ram_size not found in dt\n"); 1176 return ret; 1177 } 1178 1179 ret = dev_read_u32(dev, "mac_control", &data->mac_control); 1180 if (ret) { 1181 printf("error: ale_entries not found in dt\n"); 1182 return ret; 1183 } 1184 1185 num_mode_gpios = gpio_get_list_count(dev, "mode-gpios"); 1186 if (num_mode_gpios > 0) { 1187 mode_gpios = malloc(sizeof(struct gpio_desc) * 1188 num_mode_gpios); 1189 gpio_request_list_by_name(dev, "mode-gpios", mode_gpios, 1190 num_mode_gpios, GPIOD_IS_OUT); 1191 free(mode_gpios); 1192 } 1193 1194 data->active_slave = dev_read_u32_default(dev, "active_slave", 0); 1195 1196 ofnode_for_each_subnode(subnode, dev_ofnode(dev)) { 1197 const char *name; 1198 1199 name = ofnode_get_name(subnode); 1200 if (!strncmp(name, "mdio", 4)) { 1201 data->mdio_base = ofnode_get_addr(subnode); 1202 if (data->mdio_base == FDT_ADDR_T_NONE) { 1203 pr_err("Not able to get MDIO address space\n"); 1204 return -ENOENT; 1205 } 1206 } 1207 1208 if (!strncmp(name, "slave", 5)) { 1209 if (slave_index >= data->slaves) 1210 continue; 1211 1212 cpsw_eth_of_parse_slave(data, slave_index, subnode); 1213 slave_index++; 1214 } 1215 1216 if (!strncmp(name, "cpsw-phy-sel", 12)) { 1217 data->gmii_sel = ofnode_get_addr(subnode); 1218 1219 if (data->gmii_sel == FDT_ADDR_T_NONE) { 1220 pr_err("Not able to get gmii_sel reg address\n"); 1221 return -ENOENT; 1222 } 1223 1224 if (ofnode_read_bool(subnode, "rmii-clock-ext")) 1225 data->rmii_clock_external = true; 1226 1227 data->phy_sel_compat = ofnode_read_string(subnode, 1228 "compatible"); 1229 if (!data->phy_sel_compat) { 1230 pr_err("Not able to get gmii_sel compatible\n"); 1231 return -ENOENT; 1232 } 1233 } 1234 } 1235 1236 data->slave_data[0].slave_reg_ofs = CPSW_SLAVE0_OFFSET; 1237 data->slave_data[0].sliver_reg_ofs = CPSW_SLIVER0_OFFSET; 1238 1239 if (data->slaves == 2) { 1240 data->slave_data[1].slave_reg_ofs = CPSW_SLAVE1_OFFSET; 1241 data->slave_data[1].sliver_reg_ofs = CPSW_SLIVER1_OFFSET; 1242 } 1243 1244 ret = ti_cm_get_macid_addr(dev, data->active_slave, data); 1245 if (ret < 0) { 1246 pr_err("cpsw read efuse mac failed\n"); 1247 return ret; 1248 } 1249 1250 pdata->phy_interface = data->slave_data[data->active_slave].phy_if; 1251 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA) 1252 return -EINVAL; 1253 1254 return 0; 1255} 1256 1257static const struct udevice_id cpsw_eth_ids[] = { 1258 { .compatible = "ti,cpsw" }, 1259 { .compatible = "ti,am335x-cpsw" }, 1260 { } 1261}; 1262#endif 1263 1264int cpsw_get_slave_phy_addr(struct udevice *dev, int slave) 1265{ 1266 struct cpsw_priv *priv = dev_get_priv(dev); 1267 struct cpsw_platform_data *data = priv->data; 1268 1269 return data->slave_data[slave].phy_addr; 1270} 1271 1272U_BOOT_DRIVER(eth_cpsw) = { 1273 .name = "eth_cpsw", 1274 .id = UCLASS_ETH, 1275#if CONFIG_IS_ENABLED(OF_CONTROL) 1276 .of_match = cpsw_eth_ids, 1277 .of_to_plat = cpsw_eth_of_to_plat, 1278 .plat_auto = sizeof(struct eth_pdata), 1279#endif 1280 .probe = cpsw_eth_probe, 1281 .ops = &cpsw_eth_ops, 1282 .priv_auto = sizeof(struct cpsw_priv), 1283 .flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_PRE_RELOC, 1284}; 1285