Searched refs:x128 (Results 51 - 75 of 134) sorted by relevance

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/netbsd-current/external/gpl3/gdb.old/dist/gas/testsuite/gas/mips/
H A Dunaligned-branch-r6-6.d119 [0-9a-f]+ <[^>]*> c8000000 bc 00001128 <foo\+0x128>
H A Dvr5400.d82 0+0128 <stuff\+0x128> mulsl\.ob \$f0,\$f2
H A Dunaligned-branch-micromips-3.d140 [0-9a-f]+ <[^>]*> b462 0000 bne v0,v1,00001128 <foo\+0x128>
/netbsd-current/external/gpl3/gdb.old/dist/ld/testsuite/ld-sh/
H A Dtlsbin-1.d156 40111e: 03 a0 bra 401128 <fn2\+0x128>
H A Dtlspic-1.d153 [0-9a-f]+: 03 d4 mov\.l [0-9a-f]+ <fn1\+0x128>,r4 ! 1c .*
/netbsd-current/external/gpl3/gdb.old/dist/gas/testsuite/gas/tic6x/
H A Dinsns16-s-unit-pcrel.d75 [0-9a-f]+[02468ace] <[^>]*> e52a[ \t]+\[a0\] bnop \.S1 [0-9a-f]{8} <[^+]*\+0x128>,5
/netbsd-current/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/
H A Dimx8mn-pinfunc.h362 #define MX8MN_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0
363 #define MX8MN_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0
364 #define MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x128 0x390 0x5E0 0x2 0x0
365 #define MX8MN_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0
366 #define MX8MN_IOMUXC_NAND_DATA07_CORESIGHT_TRACE11 0x128 0x390 0x000 0x6 0x0
H A Dimx8mp-pinfunc.h395 #define MX8MP_IOMUXC_NAND_WP_B__NAND_WP_B 0x128 0x388 0x000 0x0 0x0
396 #define MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x128 0x388 0x60C 0x2 0x1
397 #define MX8MP_IOMUXC_NAND_WP_B__I2C4_SCL 0x128 0x388 0x5BC 0x4 0x3
398 #define MX8MP_IOMUXC_NAND_WP_B__GPIO3_IO18 0x128 0x388 0x000 0x5 0x0
399 #define MX8MP_IOMUXC_NAND_WP_B__CORESIGHT_EVENTO 0x128 0x388 0x000 0x6 0x0
H A Dimx8mm-pinfunc.h238 #define MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0
239 #define MX8MM_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0
240 #define MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x128 0x390 0x000 0x2 0x0
241 #define MX8MM_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0
242 #define MX8MM_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0
H A Dimx8mq-pinfunc.h237 #define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x128 0x390 0x000 0x0 0x0
238 #define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x128 0x390 0x000 0x1 0x0
239 #define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x128 0x390 0x000 0x5 0x0
240 #define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9 0x128 0x390 0x000 0x7 0x0
/netbsd-current/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
H A Dimx6sl-pinfunc.h399 #define MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x128 0x418 0x704 0x0 0x1
400 #define MX6SL_PAD_FEC_CRS_DV__SD4_DATA1 0x128 0x418 0x860 0x1 0x1
401 #define MX6SL_PAD_FEC_CRS_DV__AUD6_TXC 0x128 0x418 0x624 0x2 0x0
402 #define MX6SL_PAD_FEC_CRS_DV__ECSPI4_MISO 0x128 0x418 0x6d4 0x3 0x1
403 #define MX6SL_PAD_FEC_CRS_DV__GPT_COMPARE2 0x128 0x418 0x000 0x4 0x0
404 #define MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x128 0x418 0x000 0x5 0x0
405 #define MX6SL_PAD_FEC_CRS_DV__ARM_TRACE31 0x128 0x418 0x000 0x6 0x0
H A Dimx6dl-pinfunc.h306 #define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x128 0x4f8 0x000 0x0 0x0
307 #define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x128 0x4f8 0x000 0x1 0x0
308 #define MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0x128 0x4f8 0x8a4 0x2 0x0
309 #define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x128 0x4f8 0x000 0x5 0x0
310 #define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x128 0x4f8 0x000 0x7 0x0
311 #define MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x128 0x4f8 0x000 0x8 0x0
H A Dimx6q-pinfunc.h336 #define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x128 0x43c 0x000 0x0 0x0
337 #define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x128 0x43c 0x000 0x1 0x0
338 #define MX6QDL_PAD_EIM_DA5__IPU2_CSI1_DATA04 0x128 0x43c 0x000 0x2 0x0
339 #define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x128 0x43c 0x000 0x5 0x0
340 #define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x128 0x43c 0x000 0x7 0x0
H A Dimx50-pinfunc.h349 #define MX50_PAD_SD2_CD__ESDHC2_CD 0x128 0x3d4 0x740 0x0 0x1
350 #define MX50_PAD_SD2_CD__GPIO5_17 0x128 0x3d4 0x000 0x1 0x0
351 #define MX50_PAD_SD2_CD__AUDMUX_AUD4_TXC 0x128 0x3d4 0x6d4 0x2 0x0
352 #define MX50_PAD_SD2_CD__EIM_WEIM_D_5 0x128 0x3d4 0x800 0x4 0x0
353 #define MX50_PAD_SD2_CD__CCM_REF_EN_B 0x128 0x3d4 0x000 0x7 0x0
/netbsd-current/sys/arch/arm/nvidia/
H A Dtegra124_carreg.h178 #define CAR_CLKSRC_I2C5_REG 0x128
H A Dtegra210_carreg.h206 #define CAR_CLKSRC_I2C5_REG 0x128
/netbsd-current/sys/dev/ic/
H A Dbwivar.h263 #define BWI_FW_VERSION3_REVMAX 0x128
/netbsd-current/sys/arch/mips/cavium/dev/
H A Docteon_powreg.h155 #define POW_WQ_INT_CNT5_OFFSET UINT64_C(0x128)
/netbsd-current/sys/external/gpl2/dts/dist/include/dt-bindings/input/
H A Dlinux-event-codes.h375 #define BTN_BASE3 0x128
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
H A Dfiji_ppsmc.h217 #define PPSMC_MSG_MCLKDPM_Config ((uint16_t) 0x128)
H A Dsmu7_ppsmc.h214 #define PPSMC_MSG_MCLKDPM_Config ((uint16_t) 0x128)
H A Dtonga_ppsmc.h241 #define PPSMC_MSG_MCLKDPM_Config ((uint16_t) 0x128)
/netbsd-current/external/gpl3/gdb.old/dist/gas/testsuite/gas/arm/
H A Dthumb2_vpool.d84 00000128 <thumb2_ldr\+0x128> eddf cb01 vldr d28, \[pc, #4\] ; 00000130 <thumb2_ldr\+0x130>
H A Dthumb2_vpool_be.d85 00000128 <thumb2_ldr\+0x128> eddf cb01 vldr d28, \[pc, #4\] ; 00000130 <thumb2_ldr\+0x130>
/netbsd-current/sys/arch/arm/imx/
H A Dimx23_pinctrlreg.h307 #define HW_PINCTRL_MUXSEL2_CLR 0x128

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