1/* $NetBSD: tegra124_carreg.h,v 1.7 2019/03/09 19:41:26 jakllsch Exp $ */ 2 3/*- 4 * Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29#ifndef _ARM_TEGRA124_CARREG_H 30#define _ARM_TEGRA124_CARREG_H 31 32#define TEGRA124_REF_FREQ 12000000 33 34#define CAR_RST_SOURCE_REG 0x00 35#define CAR_RST_SOURCE_WDT_EN __BIT(5) 36#define CAR_RST_SOURCE_WDT_SEL __BIT(4) 37#define CAR_RST_SOURCE_WDT_SYS_RST_EN __BIT(2) 38#define CAR_RST_SOURCE_WDT_COP_RST_EN __BIT(1) 39#define CAR_RST_SOURCE_WDT_CPU_RST_EN __BIT(0) 40 41#define CAR_CLK_OUT_ENB_L_REG 0x10 42#define CAR_CLK_OUT_ENB_H_REG 0x14 43#define CAR_CLK_OUT_ENB_U_REG 0x18 44 45#define CAR_PLL_LFSR_REG 0x54 46#define CAR_PLL_LFSR_RND __BITS(15,0) 47 48#define CAR_PLLP_BASE_REG 0xa0 49#define CAR_PLLP_BASE_BYPASS __BIT(31) 50#define CAR_PLLP_BASE_ENABLE __BIT(30) 51#define CAR_PLLP_BASE_REF_DIS __BIT(29) 52#define CAR_PLLP_BASE_OVERRIDE __BIT(28) 53#define CAR_PLLP_BASE_LOCK __BIT(27) 54#define CAR_PLLP_BASE_DIVP __BITS(22,20) 55#define CAR_PLLP_BASE_DIVN __BITS(17,8) 56#define CAR_PLLP_BASE_DIVM __BITS(4,0) 57 58#define CAR_PLLP_OUTA_REG 0xa4 59#define CAR_PLLP_OUTA_OUT2_RATIO __BITS(31,24) 60#define CAR_PLLP_OUTA_OUT2_OVRRIDE __BIT(18) 61#define CAR_PLLP_OUTA_OUT2_CLKEN __BIT(17) 62#define CAR_PLLP_OUTA_OUT2_RSTN __BIT(16) 63#define CAR_PLLP_OUTA_OUT1_RATIO __BITS(15,8) 64#define CAR_PLLP_OUTA_OUT1_OVRRIDE __BIT(2) 65#define CAR_PLLP_OUTA_OUT1_CLKEN __BIT(1) 66#define CAR_PLLP_OUTA_OUT1_RSTN __BIT(0) 67#define CAR_PLLP_OUTB_REG 0xa8 68#define CAR_PLLP_OUTB_OUT4_RATIO __BITS(31,24) 69#define CAR_PLLP_OUTB_OUT4_OVRRIDE __BIT(18) 70#define CAR_PLLP_OUTB_OUT4_CLKEN __BIT(17) 71#define CAR_PLLP_OUTB_OUT4_RSTN __BIT(16) 72#define CAR_PLLP_OUTB_OUT3_RATIO __BITS(15,8) 73#define CAR_PLLP_OUTB_OUT3_OVRRIDE __BIT(2) 74#define CAR_PLLP_OUTB_OUT3_CLKEN __BIT(1) 75#define CAR_PLLP_OUTB_OUT3_RSTN __BIT(0) 76#define CAR_PLLP_OUTC_REG 0x67c 77#define CAR_PLLP_OUTC_OUT5_RATIO __BITS(31,24) 78#define CAR_PLLP_OUTC_OUT5_OVERRIDE __BIT(18) 79#define CAR_PLLP_OUTC_OUT5_CLKEN __BIT(17) 80#define CAR_PLLP_OUTC_OUT5_RSTN __BIT(16) 81#define CAR_PLLP_MISC_REG 0xac 82 83#define CAR_PLLC_BASE_REG 0x80 84#define CAR_PLLC_BASE_ENABLE __BIT(30) 85#define CAR_PLLC_BASE_REF_DIS __BIT(29) 86#define CAR_PLLC_BASE_LOCK_OVERRIDE __BIT(28) 87#define CAR_PLLC_BASE_LOCK __BIT(27) 88#define CAR_PLLC_BASE_DIVP __BITS(23,20) 89#define CAR_PLLC_BASE_DIVN __BITS(15,8) 90#define CAR_PLLC_BASE_DIVM __BITS(7,0) 91 92#define CAR_PLLU_BASE_REG 0xc0 93#define CAR_PLLU_BASE_BYPASS __BIT(31) 94#define CAR_PLLU_BASE_ENABLE __BIT(30) 95#define CAR_PLLU_BASE_REF_DIS __BIT(29) 96#define CAR_PLLU_BASE_LOCK __BIT(27) 97#define CAR_PLLU_BASE_CLKENABLE_48M __BIT(25) 98#define CAR_PLLU_BASE_OVERRIDE __BIT(24) 99#define CAR_PLLU_BASE_CLKENABLE_ICUSB __BIT(23) 100#define CAR_PLLU_BASE_CLKENABLE_HSIC __BIT(22) 101#define CAR_PLLU_BASE_CLKENABLE_USB __BIT(21) 102#define CAR_PLLU_BASE_VCO_FREQ __BIT(20) 103#define CAR_PLLU_BASE_DIVN __BITS(17,8) 104#define CAR_PLLU_BASE_DIVM __BITS(4,0) 105 106#define CAR_PLLD_BASE_REG 0xd0 107#define CAR_PLLD_BASE_BYPASS __BIT(31) 108#define CAR_PLLD_BASE_ENABLE __BIT(30) 109#define CAR_PLLD_BASE_REF_DIS __BIT(29) 110#define CAR_PLLD_BASE_LOCK __BIT(27) 111#define CAR_PLLD_BASE_CLKENABLE_CSI __BIT(26) 112#define CAR_PLLD_BASE_DSIA_CLK_SRC __BIT(25) 113#define CAR_PLLD_BASE_CSI_CLK_SRC __BIT(23) 114#define CAR_PLLD_BASE_DIVP __BITS(22,20) 115#define CAR_PLLD_BASE_DIVN __BITS(18,8) 116#define CAR_PLLD_BASE_DIVM __BITS(4,0) 117 118#define CAR_PLLD_MISC_REG 0xdc 119 120#define CAR_PLLX_BASE_REG 0xe0 121#define CAR_PLLX_BASE_BYPASS __BIT(31) 122#define CAR_PLLX_BASE_ENABLE __BIT(30) 123#define CAR_PLLX_BASE_REF_DIS __BIT(29) 124#define CAR_PLLX_BASE_LOCK __BIT(27) 125#define CAR_PLLX_BASE_DIVP __BITS(23,20) 126#define CAR_PLLX_BASE_DIVN __BITS(15,8) 127#define CAR_PLLX_BASE_DIVM __BITS(7,0) 128 129#define CAR_PLLX_MISC_REG 0xe4 130#define CAR_PLLX_MISC_FO_LP_DISABLE __BIT(29) 131#define CAR_PLLX_MISC_FO_G_DISABLE __BIT(28) 132#define CAR_PLLX_MISC_PTS __BITS(23,22) 133#define CAR_PLLX_MISC_LOCK_ENABLE __BIT(18) 134 135#define CAR_PLLE_BASE_REG 0xe8 136#define CAR_PLLE_BASE_ENABLE __BIT(30) 137#define CAR_PLLE_BASE_LOCK_OVERRIDE __BIT(29) 138#define CAR_PLLE_BASE_FDIV48 __BIT(28) 139#define CAR_PLLE_BASE_DIVP_CML __BITS(27,24) 140#define CAR_PLLE_BASE_EXT_SETUP_23_16 __BITS(23,16) 141#define CAR_PLLE_BASE_DIVN __BITS(15,8) 142#define CAR_PLLE_BASE_DIVM __BITS(7,0) 143 144#define CAR_PLLE_MISC_REG 0xec 145#define CAR_PLLE_MISC_IDDQ_SWCTL __BIT(14) 146#define CAR_PLLE_MISC_IDDQ_OVERRIDE __BIT(13) 147#define CAR_PLLE_MISC_LOCK __BIT(11) 148#define CAR_PLLE_MISC_LOCK_ENABLE __BIT(9) 149 150#define CAR_PLLD2_BASE_REG 0x4b8 151#define CAR_PLLD2_BASE_BYPASS __BIT(31) 152#define CAR_PLLD2_BASE_ENABLE __BIT(30) 153#define CAR_PLLD2_BASE_REF_DIS __BIT(29) 154#define CAR_PLLD2_BASE_FREQLOCK __BIT(28) 155#define CAR_PLLD2_BASE_LOCK __BIT(27) 156#define CAR_PLLD2_BASE_REF_SRC_SEL __BITS(26,25) 157#define CAR_PLLD2_BASE_REF_SRC_SEL_PLL_D 0 158#define CAR_PLLD2_BASE_REF_SRC_SEL_PLL_D2 1 159#define CAR_PLLD2_BASE_LOCK_OVERRIDE __BIT(24) 160#define CAR_PLLD2_BASE_DIVP __BITS(23,20) 161#define CAR_PLLD2_BASE_IDDQ __BIT(19) 162#define CAR_PLLD2_BASE_PTS __BIT(16) 163#define CAR_PLLD2_BASE_DIVN __BITS(15,8) 164#define CAR_PLLD2_BASE_DIVM __BITS(7,0) 165 166#define CAR_PLLD2_MISC_REG 0x4bc 167#define CAR_PLLD2_MISC_EN_FSTLCK __BIT(31) 168#define CAR_PLLD2_MISC_LOCK_ENABLE __BIT(30) 169#define CAR_PLLD2_MISC_MON_TEST_OUT __BITS(29,27) 170#define CAR_PLLD2_MISC_KCP __BITS(26,25) 171#define CAR_PLLD2_MISC_KVCO __BIT(24) 172#define CAR_PLLD2_MISC_SETUP __BITS(23,0) 173 174#define CAR_CLKSRC_I2C1_REG 0x124 175#define CAR_CLKSRC_I2C2_REG 0x198 176#define CAR_CLKSRC_I2C3_REG 0x1b8 177#define CAR_CLKSRC_I2C4_REG 0x3c4 178#define CAR_CLKSRC_I2C5_REG 0x128 179#define CAR_CLKSRC_I2C6_REG 0x65c 180 181#define CAR_CLKSRC_I2C_SRC __BITS(31,29) 182#define CAR_CLKSRC_I2C_SRC_PLLP_OUT0 0 183#define CAR_CLKSRC_I2C_SRC_PLLC2_OUT0 1 184#define CAR_CLKSRC_I2C_SRC_PLLC_OUT0 2 185#define CAR_CLKSRC_I2C_SRC_PLLC3_OUT0 3 186#define CAR_CLKSRC_I2C_SRC_PLLM_OUT0 4 187#define CAR_CLKSRC_I2C_SRC_CLK_M 6 188#define CAR_CLKSRC_I2C_DIV __BITS(15,0) 189 190#define CAR_CLKSRC_SPI1_REG 0x134 191#define CAR_CLKSRC_SPI2_REG 0x118 192#define CAR_CLKSRC_SPI3_REG 0x11c 193#define CAR_CLKSRC_SPI4_REG 0x1b4 194#define CAR_CLKSRC_SPI5_REG 0x3c8 195#define CAR_CLKSRC_SPI6_REG 0x3cc 196 197#define CAR_CLKSRC_SPI_SRC __BITS(31,29) 198#define CAR_CLKSRC_SPI_SRC_PLLP_OUT0 0 199#define CAR_CLKSRC_SPI_SRC_PLLC2_OUT0 1 200#define CAR_CLKSRC_SPI_SRC_PLLC_OUT0 2 201#define CAR_CLKSRC_SPI_SRC_PLLC3_OUT0 3 202#define CAR_CLKSRC_SPI_SRC_PLLM_OUT0 4 203#define CAR_CLKSRC_SPI_SRC_CLK_M 6 204#define CAR_CLKSRC_SPI_DIV __BITS(7,0) 205 206#define CAR_CLKSRC_UARTA_REG 0x178 207#define CAR_CLKSRC_UARTB_REG 0x17c 208#define CAR_CLKSRC_UARTC_REG 0x1a0 209#define CAR_CLKSRC_UARTD_REG 0x1c0 210 211#define CAR_CLKSRC_UART_SRC __BITS(31,29) 212#define CAR_CLKSRC_UART_SRC_PLLP_OUT0 0 213#define CAR_CLKSRC_UART_SRC_PLLC2_OUT0 1 214#define CAR_CLKSRC_UART_SRC_PLLC_OUT0 2 215#define CAR_CLKSRC_UART_SRC_PLLC3_OUT0 3 216#define CAR_CLKSRC_UART_SRC_PLLM_OUT0 4 217#define CAR_CLKSRC_UART_SRC_CLK_M 6 218#define CAR_CLKSRC_UART_DIV_ENB __BIT(24) 219#define CAR_CLKSRC_UART_DIV __BITS(15,0) 220 221#define CAR_CLKSRC_SDMMC1_REG 0x150 222#define CAR_CLKSRC_SDMMC2_REG 0x154 223#define CAR_CLKSRC_SDMMC4_REG 0x164 224#define CAR_CLKSRC_SDMMC3_REG 0x1bc 225 226#define CAR_CLKSRC_SDMMC_SRC __BITS(31,29) 227#define CAR_CLKSRC_SDMMC_SRC_PLLP_OUT0 0 228#define CAR_CLKSRC_SDMMC_SRC_PLLC2_OUT0 1 229#define CAR_CLKSRC_SDMMC_SRC_PLLC_OUT0 2 230#define CAR_CLKSRC_SDMMC_SRC_PLLC3_OUT0 3 231#define CAR_CLKSRC_SDMMC_SRC_PLLM_OUT0 4 232#define CAR_CLKSRC_SDMMC_SRC_PLLE_OUT0 5 233#define CAR_CLKSRC_SDMMC_SRC_CLK_M 6 234#define CAR_CLKSRC_SDMMC_DIV __BITS(7,0) 235 236#define CAR_CLKSRC_HDMI_REG 0x18c 237#define CAR_CLKSRC_HDMI_SRC __BITS(31,29) 238#define CAR_CLKSRC_HDMI_SRC_PLLP_OUT0 0 239#define CAR_CLKSRC_HDMI_SRC_PLLM_OUT0 1 240#define CAR_CLKSRC_HDMI_SRC_PLLD_OUT0 2 241#define CAR_CLKSRC_HDMI_SRC_PLLA_OUT0 3 242#define CAR_CLKSRC_HDMI_SRC_PLLC_OUT0 4 243#define CAR_CLKSRC_HDMI_SRC_PLLD2_OUT0 5 244#define CAR_CLKSRC_HDMI_SRC_CLK_M 6 245#define CAR_CLKSRC_HDMI_DIV __BITS(7,0) 246 247#define CAR_CLKSRC_DISP1_REG 0x138 248#define CAR_CLKSRC_DISP2_REG 0x13c 249#define CAR_CLKSRC_DISP_SRC __BITS(31,29) 250#define CAR_CLKSRC_DISP_SRC_PLLP_OUT0 0 251#define CAR_CLKSRC_DISP_SRC_PLLM_OUT0 1 252#define CAR_CLKSRC_DISP_SRC_PLLD_OUT0 2 253#define CAR_CLKSRC_DISP_SRC_PLLA_OUT0 3 254#define CAR_CLKSRC_DISP_SRC_PLLC_OUT0 4 255#define CAR_CLKSRC_DISP_SRC_PLLD2_OUT0 5 256#define CAR_CLKSRC_DISP_SRC_CLK_M 6 257 258#define CAR_CLKSRC_HOST1X_REG 0x180 259#define CAR_CLKSRC_HOST1X_SRC __BITS(31,29) 260#define CAR_CLKSRC_HOST1X_SRC_PLLM_OUT0 0 261#define CAR_CLKSRC_HOST1X_SRC_PLLC2_OUT0 1 262#define CAR_CLKSRC_HOST1X_SRC_PLLC_OUT0 2 263#define CAR_CLKSRC_HOST1X_SRC_PLLC3_OUT0 3 264#define CAR_CLKSRC_HOST1X_SRC_PLLP_OUT0 4 265#define CAR_CLKSRC_HOST1X_SRC_PLLA_OUT0 6 266#define CAR_CLKSRC_HOST1X_IDLE_DIVISOR __BITS(15,8) 267#define CAR_CLKSRC_HOST1X_CLK_DIVISOR __BITS(7,0) 268 269#define CAR_RST_DEV_L_SET_REG 0x300 270#define CAR_RST_DEV_L_CLR_REG 0x304 271#define CAR_RST_DEV_H_SET_REG 0x308 272#define CAR_RST_DEV_H_CLR_REG 0x30c 273#define CAR_RST_DEV_U_SET_REG 0x310 274#define CAR_RST_DEV_U_CLR_REG 0x314 275#define CAR_RST_DEV_V_SET_REG 0x430 276#define CAR_RST_DEV_V_CLR_REG 0x434 277#define CAR_RST_DEV_W_SET_REG 0x438 278#define CAR_RST_DEV_W_CLR_REG 0x43c 279#define CAR_RST_DEV_X_SET_REG 0x290 280#define CAR_RST_DEV_X_CLR_REG 0x294 281 282#define CAR_CLK_ENB_L_SET_REG 0x320 283#define CAR_CLK_ENB_L_CLR_REG 0x324 284#define CAR_CLK_ENB_H_SET_REG 0x328 285#define CAR_CLK_ENB_H_CLR_REG 0x32c 286#define CAR_CLK_ENB_U_SET_REG 0x330 287#define CAR_CLK_ENB_U_CLR_REG 0x334 288#define CAR_CLK_ENB_V_SET_REG 0x440 289#define CAR_CLK_ENB_V_CLR_REG 0x444 290#define CAR_CLK_ENB_W_SET_REG 0x448 291#define CAR_CLK_ENB_W_CLR_REG 0x44c 292#define CAR_CLK_ENB_X_SET_REG 0x284 293#define CAR_CLK_ENB_X_CLR_REG 0x288 294 295#define CAR_DEV_L_CACHE2 __BIT(31) 296#define CAR_DEV_L_I2S0 __BIT(30) 297#define CAR_DEV_L_VCP __BIT(29) 298#define CAR_DEV_L_HOST1X __BIT(28) 299#define CAR_DEV_L_DISP1 __BIT(27) 300#define CAR_DEV_L_DISP2 __BIT(26) 301#define CAR_DEV_L_ISP __BIT(23) 302#define CAR_DEV_L_USBD __BIT(22) 303#define CAR_DEV_L_VI __BIT(20) 304#define CAR_DEV_L_I2S2 __BIT(18) 305#define CAR_DEV_L_PWM __BIT(17) 306#define CAR_DEV_L_SDMMC4 __BIT(15) 307#define CAR_DEV_L_SDMMC1 __BIT(14) 308#define CAR_DEV_L_I2C1 __BIT(12) 309#define CAR_DEV_L_I2S1 __BIT(11) 310#define CAR_DEV_L_SPDIF __BIT(10) 311#define CAR_DEV_L_SDMMC2 __BIT(9) 312#define CAR_DEV_L_GPIO __BIT(8) 313#define CAR_DEV_L_UARTB __BIT(7) 314#define CAR_DEV_L_UARTA __BIT(6) 315#define CAR_DEV_L_TMR __BIT(5 316#define CAR_DEV_L_RTC __BIT(4) 317#define CAR_DEV_L_ISPB __BIT(3) 318#define CAR_DEV_L_CPU __BIT(0) 319 320#define CAR_DEV_U_XUSB_DEV __BIT(31) 321#define CAR_DEV_U_DEV1_OUT __BIT(30) 322#define CAR_DEV_U_DEV2_OUT __BIT(29) 323#define CAR_DEV_U_SUS_OUT __BIT(28) 324#define CAR_DEV_U_MSENC __BIT(27) 325#define CAR_DEV_U_XUSB_HOST __BIT(25) 326#define CAR_DEV_U_CRAM2 __BIT(24) 327#define CAR_DEV_U_IRAMD __BIT(23) 328#define CAR_DEV_U_IRAMC __BIT(22) 329#define CAR_DEV_U_IRAMB __BIT(21) 330#define CAR_DEV_U_IRAMA __BIT(20) 331#define CAR_DEV_U_TSEC __BIT(19) 332#define CAR_DEV_U_DSIB __BIT(18) 333#define CAR_DEV_U_I2C_SLOW __BIT(17) 334#define CAR_DEV_U_DTV __BIT(15) 335#define CAR_DEV_U_SOC_THERM __BIT(14) 336#define CAR_DEV_U_TRACECLKIN __BIT(13) 337#define CAR_DEV_U_AVPUCQ __BIT(11) 338#define CAR_DEV_U_CSITE __BIT(9) 339#define CAR_DEV_U_AFI __BIT(8) 340#define CAR_DEV_U_OWR __BIT(7) 341#define CAR_DEV_U_PCIE __BIT(6) 342#define CAR_DEV_U_SDMMC3 __BIT(5) 343#define CAR_DEV_U_SPI4 __BIT(4) 344#define CAR_DEV_U_I2C3 __BIT(3) 345#define CAR_DEV_U_UARTD __BIT(1) 346 347#define CAR_DEV_H_BSEV __BIT(31) 348#define CAR_DEV_H_BSEA __BIT(30) 349#define CAR_DEV_H_VDE __BIT(29) 350#define CAR_DEV_H_USB3 __BIT(27) 351#define CAR_DEV_H_USB2 __BIT(26) 352#define CAR_DEV_H_EMC __BIT(25) 353#define CAR_DEV_H_MIPI_CAL __BIT(24) 354#define CAR_DEV_H_UARTC __BIT(23) 355#define CAR_DEV_H_I2C2 __BIT(22) 356#define CAR_DEV_H_CSI __BIT(20) 357#define CAR_DEV_H_HDMI __BIT(19) 358#define CAR_DEV_H_HSI __BIT(18) 359#define CAR_DEV_H_DSI __BIT(16) 360#define CAR_DEV_H_I2C5 __BIT(15) 361#define CAR_DEV_H_SPI3 __BIT(14) 362#define CAR_DEV_H_SPI2 __BIT(12) 363#define CAR_DEV_H_JTAG2TBC __BIT(11) 364#define CAR_DEV_H_SNOR __BIT(10) 365#define CAR_DEV_H_SPI1 __BIT(9) 366#define CAR_DEV_H_KFUSE __BIT(8) 367#define CAR_DEV_H_FUSE __BIT(7) 368#define CAR_DEV_H_PMC __BIT(6) 369#define CAR_DEV_H_STAT_MON __BIT(5) 370#define CAR_DEV_H_KBC __BIT(4) 371#define CAR_DEV_H_APBDMA __BIT(2) 372#define CAR_DEV_H_AHBDMA __BIT(1) 373#define CAR_DEV_H_MEM __BIT(0) 374 375#define CAR_DEV_V_HDA __BIT(29) 376#define CAR_DEV_V_SATA __BIT(28) 377#define CAR_DEV_V_SATA_OOB __BIT(27) 378#define CAR_DEV_V_ACTMON __BIT(23) 379#define CAR_DEV_V_ATOMICS __BIT(16) 380#define CAR_DEV_V_HDA2CODEC_2X __BIT(15) 381#define CAR_DEV_V_DAM2 __BIT(14) 382#define CAR_DEV_V_DAM1 __BIT(13) 383#define CAR_DEV_V_DAM0 __BIT(12) 384#define CAR_DEV_V_APBIF __BIT(11) 385#define CAR_DEV_V_AUDIO __BIT(10) 386#define CAR_DEV_V_SPI6 __BIT(9) 387#define CAR_DEV_V_SPI5 __BIT(8) 388#define CAR_DEV_V_I2C4 __BIT(7) 389#define CAR_DEV_V_I2S4 __BIT(6) 390#define CAR_DEV_V_I2S3 __BIT(5) 391#define CAR_DEV_V_TSENSOR __BIT(4) 392#define CAR_DEV_V_MSELECT __BIT(3) 393#define CAR_DEV_V_CPULP __BIT(1) 394#define CAR_DEV_V_CPUG __BIT(0) 395 396#define CAR_DEV_W_XUSB_SS __BIT(28) 397#define CAR_DEV_W_DVFS __BIT(27) 398#define CAR_DEV_W_ADX0 __BIT(26) 399#define CAR_DEV_W_AMX0 __BIT(25) 400#define CAR_DEV_W_ENTROPY __BIT(21) 401#define CAR_DEV_W_XUSB __BIT(15) 402#define CAR_DEV_W_XUSB_PADCTL __BIT(14) 403#define CAR_DEV_W_CEC __BIT(8) 404#define CAR_DEV_W_SATACOLD __BIT(1) 405#define CAR_DEV_W_HDA2HDMICODEC __BIT(0) 406 407#define CAR_DEV_X_AMX1 __BIT(25) 408#define CAR_DEV_X_GPU __BIT(24) 409#define CAR_DEV_X_SOR0 __BIT(22) 410#define CAR_DEV_X_DPAUX __BIT(21) 411#define CAR_DEV_X_ADX1 __BIT(20) 412#define CAR_DEV_X_VIC __BIT(18) 413#define CAR_DEV_X_CLK72MHZ __BIT(17) 414#define CAR_DEV_X_HDMI_AUDIO __BIT(16) 415#define CAR_DEV_X_EMC_DLL __BIT(14) 416#define CAR_DEV_X_VIM2_CLK __BIT(11) 417#define CAR_DEV_X_I2C6 __BIT(6) 418#define CAR_DEV_X_CAM_MCLK2 __BIT(5) 419#define CAR_DEV_X_CAM_MCLK __BIT(4) 420#define CAR_DEV_X_SPARE __BIT(0) 421 422#define CAR_CCLKG_BURST_POLICY_REG 0x368 423#define CAR_CCLKG_BURST_POLICY_CPU_STATE __BITS(31,28) 424#define CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE 1 425#define CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN 2 426#define CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE __BITS(3,0) 427#define CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM 0 428#define CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ 8 429 430#define CAR_CLKSRC_MSELECT_REG 0x3b4 431#define CAR_CLKSRC_MSELECT_SRC __BITS(31,29) 432#define CAR_CLKSRC_MSELECT_DIV __BITS(7,0) 433 434#define CAR_CLKSRC_TSENSOR_REG 0x3b8 435#define CAR_CLKSRC_TSENSOR_SRC __BITS(31,29) 436#define CAR_CLKSRC_TSENSOR_SRC_CLK_M 4 437#define CAR_CLKSRC_TSENSOR_DIV __BITS(7,0) 438 439#define CAR_CLKSRC_HDA2CODEC_2X_REG 0x3e4 440#define CAR_CLKSRC_HDA2CODEC_2X_SRC __BITS(31,29) 441#define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLP_OUT0 0 442#define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLC2_OUT0 1 443#define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLC_OUT0 2 444#define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLC3_OUT0 3 445#define CAR_CLKSRC_HDA2CODEC_2X_SRC_PLLM_OUT0 4 446#define CAR_CLKSRC_HDA2CODEC_2X_SRC_CLKM 6 447#define CAR_CLKSRC_HDA2CODEC_2X_DIV __BITS(7,0) 448 449#define CAR_CLKSRC_SATA_OOB_REG 0x420 450#define CAR_CLKSRC_SATA_OOB_SRC __BITS(31,29) 451#define CAR_CLKSRC_SATA_OOB_SRC_PLLP_OUT0 0 452#define CAR_CLKSRC_SATA_OOB_SRC_PLLC_OUT0 2 453#define CAR_CLKSRC_SATA_OOB_SRC_PLLM_OUT0 4 454#define CAR_CLKSRC_SATA_OOB_SRC_CLKM 6 455#define CAR_CLKSRC_SATA_OOB_DIV __BITS(7,0) 456 457#define CAR_CLKSRC_SATA_REG 0x424 458#define CAR_CLKSRC_SATA_SRC __BITS(31,29) 459#define CAR_CLKSRC_SATA_SRC_PLLP_OUT0 0 460#define CAR_CLKSRC_SATA_SRC_PLLC_OUT0 2 461#define CAR_CLKSRC_SATA_SRC_PLLM_OUT0 4 462#define CAR_CLKSRC_SATA_SRC_CLKM 6 463#define CAR_CLKSRC_SATA_AUX_CLK_ENB __BIT(24) 464#define CAR_CLKSRC_SATA_DIV __BITS(7,0) 465 466#define CAR_CLKSRC_HDA_REG 0x428 467#define CAR_CLKSRC_HDA_SRC __BITS(31,29) 468#define CAR_CLKSRC_HDA_SRC_PLLP_OUT0 0 469#define CAR_CLKSRC_HDA_SRC_PLLC2_OUT0 1 470#define CAR_CLKSRC_HDA_SRC_PLLC_OUT0 2 471#define CAR_CLKSRC_HDA_SRC_PLLC3_OUT0 3 472#define CAR_CLKSRC_HDA_SRC_PLLM_OUT0 4 473#define CAR_CLKSRC_HDA_SRC_CLKM 6 474#define CAR_CLKSRC_HDA_DIV __BITS(7,0) 475 476#define CAR_UTMIP_PLL_CFG0_REG 0x480 477 478#define CAR_UTMIP_PLL_CFG1_REG 0x484 479#define CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT __BITS(31,27) 480#define CAR_UTMIP_PLL_CFG1_PLLU_POWERUP __BIT(17) 481#define CAR_UTMIP_PLL_CFG1_PLLU_POWERDOWN __BIT(16) 482#define CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERUP __BIT(15) 483#define CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN __BIT(14) 484#define CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT __BITS(11,0) 485 486#define CAR_UTMIP_PLL_CFG2_REG 0x488 487#define CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT __BITS(23,18) 488#define CAR_UTMIP_PLL_CFG2_STABLE_COUNT __BITS(17,6) 489#define CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERUP __BIT(5) 490#define CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN __BIT(4) 491#define CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERUP __BIT(3) 492#define CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN __BIT(2) 493#define CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERUP __BIT(1) 494#define CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN __BIT(0) 495 496#define CAR_PLLE_AUX_REG 0x48c 497#define CAR_PLLE_AUX_SS_SEQ_INCLUDE __BIT(31) 498#define CAR_PLLE_AUX_REF_SEL_PLLREFE __BIT(28) 499#define CAR_PLLE_AUX_SEQ_STATE __BITS(27,26) 500#define CAR_PLLE_AUX_SEQ_START_STATE __BIT(25) 501#define CAR_PLLE_AUX_SEQ_ENABLE __BIT(24) 502#define CAR_PLLE_AUX_SS_DLY __BITS(23,16) 503#define CAR_PLLE_AUX_LOCK_DLY __BITS(15,8) 504#define CAR_PLLE_AUX_FAST_PT __BIT(7) 505#define CAR_PLLE_AUX_SS_SWCTL __BIT(6) 506#define CAR_PLLE_AUX_CONFIG_SWCTL __BIT(5) 507#define CAR_PLLE_AUX_ENABLE_SWCTL __BIT(4) 508#define CAR_PLLE_AUX_USE_LOCKDET __BIT(3) 509#define CAR_PLLE_AUX_REF_SRC __BIT(2) 510#define CAR_PLLE_AUX_CML1_OEN __BIT(1) 511#define CAR_PLLE_AUX_CML0_OEN __BIT(0) 512 513#define CAR_SATA_PLL_CFG0_REG 0x490 514#define CAR_SATA_PLL_CFG0_SEQ_STATE __BITS(27,26) 515#define CAR_SATA_PLL_CFG0_SEQ_START_STATE __BIT(25) 516#define CAR_SATA_PLL_CFG0_SEQ_ENABLE __BIT(24) 517#define CAR_SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE __BIT(7) 518#define CAR_SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE __BIT(6) 519#define CAR_SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE __BIT(5) 520#define CAR_SATA_PLL_CFG0_SEQ_IN_SWCTL __BIT(4) 521#define CAR_SATA_PLL_CFG0_PADPLL_USE_LOCKDET __BIT(2) 522#define CAR_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE __BIT(1) 523#define CAR_SATA_PLL_CFG0_PADPLL_RESET_SWCTL __BIT(0) 524 525#define CAR_SATA_PLL_CFG1_REG 0x494 526#define CAR_SATA_PLL_CFG1_LANE_IDDQ2_PADPLL_RESET_DLY __BITS(31,24) 527#define CAR_SATA_PLL_CFG1_PADPLL_IDDQ2LANE_SLUMBER_DLY __BITS(23,16) 528#define CAR_SATA_PLL_CFG1_PADPLL_PU_POST_DLY __BITS(15,8) 529#define CAR_SATA_PLL_CFG1_LANE_IDDQ2_PADPLL_IDDQ_DLY __BITS(7,0) 530 531#define CAR_PLLREFE_BASE_REG 0x4c4 532#define CAR_PLLREFE_BASE_BYPASS __BIT(31) 533#define CAR_PLLREFE_BASE_ENABLE __BIT(30) 534#define CAR_PLLREFE_BASE_REF_DIS __BIT(29) 535#define CAR_PLLREFE_BASE_KCP __BITS(28,27) 536#define CAR_PLLREFE_BASE_KVCO __BIT(26) 537#define CAR_PLLREFE_BASE_DIVP __BITS(19,16) 538#define CAR_PLLREFE_BASE_DIVN __BITS(15,8) 539#define CAR_PLLREFE_BASE_DIVM __BITS(7,0) 540 541#define CAR_PLLREFE_MISC_REG 0x4c8 542#define CAR_PLLREFE_MISC_LOCK_ENABLE __BIT(30) 543#define CAR_PLLREFE_MISC_LOCK_OVERRIDE __BIT(29) 544#define CAR_PLLREFE_MISC_LOCK __BIT(24) 545#define CAR_PLLREFE_MISC_IDDQ __BIT(16) 546 547#define CAR_XUSBIO_PLL_CFG0_REG 0x51c 548#define CAR_XUSBIO_PLL_CFG0_SEQ_STATE __BITS(27,26) 549#define CAR_XUSBIO_PLL_CFG0_SEQ_START_STATE __BIT(25) 550#define CAR_XUSBIO_PLL_CFG0_SEQ_ENABLE __BIT(24) 551#define CAR_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET __BIT(6) 552#define CAR_XUSBIO_PLL_CFG0_SEQ_RESET_INPUT_VALUE __BIT(5) 553#define CAR_XUSBIO_PLL_CFG0_SEQ_IN_SWCTL __BIT(4) 554#define CAR_XUSBIO_PLL_CFG0_CLK_ENABLE_OVERRIDE __BIT(3) 555#define CAR_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL __BIT(2) 556#define CAR_XUSBIO_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE __BIT(1) 557#define CAR_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL __BIT(0) 558 559#define CAR_CLKSRC_XUSB_HOST_REG 0x600 560#define CAR_CLKSRC_XUSB_HOST_SRC __BITS(31,29) 561#define CAR_CLKSRC_XUSB_HOST_DIV __BITS(7,0) 562 563#define CAR_CLKSRC_XUSB_FALCON_REG 0x604 564#define CAR_CLKSRC_XUSB_FALCON_SRC __BITS(31,29) 565#define CAR_CLKSRC_XUSB_FALCON_DIV __BITS(7,0) 566 567#define CAR_CLKSRC_XUSB_FS_REG 0x608 568#define CAR_CLKSRC_XUSB_FS_SRC __BITS(31,29) 569#define CAR_CLKSRC_XUSB_FS_DIV __BITS(7,0) 570 571#define CAR_CLKSRC_XUSB_SS_REG 0x610 572#define CAR_CLKSRC_XUSB_SS_SRC __BITS(31,29) 573#define CAR_CLKSRC_XUSB_SS_HS_CLK_BYPASS __BIT(25) 574#define CAR_CLKSRC_XUSB_SS_SS_CLK_BYPASS __BIT(24) 575#define CAR_CLKSRC_XUSB_SS_DIV __BITS(7,0) 576 577#define CAR_CLKSRC_SOC_THERM_REG 0x644 578#define CAR_CLKSRC_SOC_THERM_SRC __BITS(31,29) 579#define CAR_CLKSRC_SOC_THERM_SRC_PLLP_OUT0 2 580#define CAR_CLKSRC_SOC_THERM_DIV __BITS(7,0) 581 582#define CAR_CLKSRC_HDMI_AUDIO_REG 0x668 583#define CAR_CLKSRC_HDMI_AUDIO_SRC __BITS(31,29) 584#define CAR_CLKSRC_HDMI_AUDIO_SRC_PLLP_OUT0 0 585#define CAR_CLKSRC_HDMI_AUDIO_SRC_PLLC_OUT0 1 586#define CAR_CLKSRC_HDMI_AUDIO_SRC_PLLC2_OUT0 2 587#define CAR_CLKSRC_HDMI_AUDIO_SRC_CLKM 3 588#define CAR_CLKSRC_HDMI_AUDIO_DIV __BITS(7,0) 589 590#endif /* _ARM_TEGRA124_CARREG_H */ 591