1/* $Id: imx23_pinctrlreg.h,v 1.2 2013/10/07 17:36:40 matt Exp $ */ 2 3/* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Petri Laakso. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#ifndef _ARM_IMX_IMX23_PINCTRLREG_H_ 33#define _ARM_IMX_IMX23_PINCTRLREG_H_ 34 35#include <sys/cdefs.h> 36 37#define HW_PINCTRL_BASE 0x80018000 38#define HW_PINCTRL_SIZE 0x2000 39 40/* 41 * PINCTRL Block Control Register. 42 */ 43#define HW_PINCTRL_CTRL 0x000 44#define HW_PINCTRL_CTRL_SET 0x004 45#define HW_PINCTRL_CTRL_CLR 0x008 46#define HW_PINCTRL_CTRL_TOG 0x00C 47 48#define HW_PINCTRL_CTRL_SFTRST __BIT(31) 49#define HW_PINCTRL_CTRL_CLKGATE __BIT(30) 50#define HW_PINCTRL_CTRL_RSRVD2 __BITS(29, 28) 51#define HW_PINCTRL_CTRL_PRESENT3 __BIT(27) 52#define HW_PINCTRL_CTRL_PRESENT2 __BIT(26) 53#define HW_PINCTRL_CTRL_PRESENT1 __BIT(25) 54#define HW_PINCTRL_CTRL_PRESENT0 __BIT(24) 55#define HW_PINCTRL_CTRL_RSRVD1 __BIT(23, 3) 56#define HW_PINCTRL_CTRL_IRQOUT2 __BITS(2) 57#define HW_PINCTRL_CTRL_IRQOUT1 __BIT(1) 58#define HW_PINCTRL_CTRL_IRQOUT0 __BIT(0) 59 60/* 61 * PINCTRL Pin Mux Select Register 0. 62 */ 63#define HW_PINCTRL_MUXSEL0 0x100 64#define HW_PINCTRL_MUXSEL0_SET 0x104 65#define HW_PINCTRL_MUXSEL0_CLR 0x108 66#define HW_PINCTRL_MUXSEL0_TOG 0x10C 67 68#define HW_PINCTRL_MUXSEL0_BANK0_PIN15 __BITS(31, 30) 69#define HW_PINCTRL_MUXSEL0_BANK0_PIN14 __BITS(29, 28) 70#define HW_PINCTRL_MUXSEL0_BANK0_PIN13 __BITS(27, 26) 71#define HW_PINCTRL_MUXSEL0_BANK0_PIN12 __BITS(25, 24) 72#define HW_PINCTRL_MUXSEL0_BANK0_PIN11 __BITS(23, 22) 73#define HW_PINCTRL_MUXSEL0_BANK0_PIN10 __BITS(21, 20) 74#define HW_PINCTRL_MUXSEL0_BANK0_PIN09 __BITS(19, 18) 75#define HW_PINCTRL_MUXSEL0_BANK0_PIN08 __BITS(17, 16) 76#define HW_PINCTRL_MUXSEL0_BANK0_PIN07 __BITS(15, 14) 77#define HW_PINCTRL_MUXSEL0_BANK0_PIN06 __BITS(13, 12) 78#define HW_PINCTRL_MUXSEL0_BANK0_PIN05 __BITS(11, 10) 79#define HW_PINCTRL_MUXSEL0_BANK0_PIN04 __BITS(9, 8) 80#define HW_PINCTRL_MUXSEL0_BANK0_PIN03 __BITS(7, 6) 81#define HW_PINCTRL_MUXSEL0_BANK0_PIN02 __BITS(5, 4) 82#define HW_PINCTRL_MUXSEL0_BANK0_PIN01 __BITS(3, 2) 83#define HW_PINCTRL_MUXSEL0_BANK0_PIN00 __BITS(1, 0) 84 85/* Pin 59, GPMI_D15 pin function selection */ 86#define HW_PINCTRL_MUXSEL0_BANK0_PIN15_GPMI_DATA15 0x00 87#define HW_PINCTRL_MUXSEL0_BANK0_PIN15_AUART2_TX 0x01 88#define HW_PINCTRL_MUXSEL0_BANK0_PIN15_GPMI_CE3N 0x02 89#define HW_PINCTRL_MUXSEL0_BANK0_PIN15_GPIO 0x03 90 91/* Pin 58, GPMI_D14 pin function selection */ 92#define HW_PINCTRL_MUXSEL0_BANK0_PIN14_GPMI_DATA14 0x00 93#define HW_PINCTRL_MUXSEL0_BANK0_PIN14_AUART2_RX 0x01 94#define HW_PINCTRL_MUXSEL0_BANK0_PIN14_RESERVED 0x02 95#define HW_PINCTRL_MUXSEL0_BANK0_PIN14_GPIO 0x03 96 97/* Pin 57, GPMI_D13 pin function selection */ 98#define HW_PINCTRL_MUXSEL0_BANK0_PIN13_GPMI_DATA13 0x00 99#define HW_PINCTRL_MUXSEL0_BANK0_PIN13_LCD_D23 0x01 100#define HW_PINCTRL_MUXSEL0_BANK0_PIN13_RESERVED 0x02 101#define HW_PINCTRL_MUXSEL0_BANK0_PIN13_GPIO 0x03 102 103/* Pin 56, GPMI_D12 pin function selection */ 104#define HW_PINCTRL_MUXSEL0_BANK0_PIN12_GPMI_DATA12 0x00 105#define HW_PINCTRL_MUXSEL0_BANK0_PIN12_LCD_D22 0x01 106#define HW_PINCTRL_MUXSEL0_BANK0_PIN12_RESERVED 0x02 107#define HW_PINCTRL_MUXSEL0_BANK0_PIN12_GPIO 0x03 108 109/* Pin 55, GPMI_D11 pin function selection */ 110#define HW_PINCTRL_MUXSEL0_BANK0_PIN11_GPMI_DATA11 0x00 111#define HW_PINCTRL_MUXSEL0_BANK0_PIN11_LCD_D21 0x01 112#define HW_PINCTRL_MUXSEL0_BANK0_PIN11_SSP1_D7 0x02 113#define HW_PINCTRL_MUXSEL0_BANK0_PIN11_GPIO 0x03 114 115/* Pin 54, GPMI_D10 pin function selection */ 116#define HW_PINCTRL_MUXSEL0_BANK0_PIN10_GPMI_DATA10 0x00 117#define HW_PINCTRL_MUXSEL0_BANK0_PIN10_LCD_D20 0x01 118#define HW_PINCTRL_MUXSEL0_BANK0_PIN10_SSP1_D6 0x02 119#define HW_PINCTRL_MUXSEL0_BANK0_PIN10_GPIO 0x03 120 121/* Pin 53, GPMI_D09 pin function selection */ 122#define HW_PINCTRL_MUXSEL0_BANK0_PIN09_GPMI_DATA09 0x00 123#define HW_PINCTRL_MUXSEL0_BANK0_PIN09_LCD_D19 0x01 124#define HW_PINCTRL_MUXSEL0_BANK0_PIN09_SSP1_D5 0x02 125#define HW_PINCTRL_MUXSEL0_BANK0_PIN09_GPIO 0x03 126 127/* Pin 52, GPMI_D08 pin function selection */ 128#define HW_PINCTRL_MUXSEL0_BANK0_PIN08_GPMI_DATA08 0x00 129#define HW_PINCTRL_MUXSEL0_BANK0_PIN08_LCD_D18 0x01 130#define HW_PINCTRL_MUXSEL0_BANK0_PIN08_SSP1_D4 0x02 131#define HW_PINCTRL_MUXSEL0_BANK0_PIN08_GPIO 0x03 132 133/* Pin 50, GPMI_D07 pin function selection */ 134#define HW_PINCTRL_MUXSEL0_BANK0_PIN07_GPMI_DATA07 0x00 135#define HW_PINCTRL_MUXSEL0_BANK0_PIN07_LCD_D15 0x01 136#define HW_PINCTRL_MUXSEL0_BANK0_PIN07_SSP2_D7 0x02 137#define HW_PINCTRL_MUXSEL0_BANK0_PIN07_GPIO 0x03 138 139/* Pin 51, GPMI_D06 pin function selection */ 140#define HW_PINCTRL_MUXSEL0_BANK0_PIN06_GPMI_DATA06 0x00 141#define HW_PINCTRL_MUXSEL0_BANK0_PIN06_LCD_D14 0x01 142#define HW_PINCTRL_MUXSEL0_BANK0_PIN06_SSP2_D6 0x02 143#define HW_PINCTRL_MUXSEL0_BANK0_PIN06_GPIO 0x03 144 145/* Pin 48, GPMI_D05 pin function selection */ 146#define HW_PINCTRL_MUXSEL0_BANK0_PIN05_GPMI_DATA05 0x00 147#define HW_PINCTRL_MUXSEL0_BANK0_PIN05_LCD_D13 0x01 148#define HW_PINCTRL_MUXSEL0_BANK0_PIN05_SSP2_D5 0x02 149#define HW_PINCTRL_MUXSEL0_BANK0_PIN05_GPIO 0x03 150 151/* Pin 49, GPMI_D04 pin function selection */ 152#define HW_PINCTRL_MUXSEL0_BANK0_PIN04_GPMI_DATA04 0x00 153#define HW_PINCTRL_MUXSEL0_BANK0_PIN04_LCD_D12 0x01 154#define HW_PINCTRL_MUXSEL0_BANK0_PIN04_SSP2_D4 0x02 155#define HW_PINCTRL_MUXSEL0_BANK0_PIN04_GPIO 0x03 156 157/* Pin 47, GPMI_D03 pin function selection */ 158#define HW_PINCTRL_MUXSEL0_BANK0_PIN03_GPMI_DATA03 0x00 159#define HW_PINCTRL_MUXSEL0_BANK0_PIN03_LCD_D11 0x01 160#define HW_PINCTRL_MUXSEL0_BANK0_PIN03_SSP2_D3 0x02 161#define HW_PINCTRL_MUXSEL0_BANK0_PIN03_GPIO 0x03 162 163/* Pin 46, GPMI_D02 pin function selection */ 164#define HW_PINCTRL_MUXSEL0_BANK0_PIN02_GPMI_DATA02 0x00 165#define HW_PINCTRL_MUXSEL0_BANK0_PIN02_LCD_D10 0x01 166#define HW_PINCTRL_MUXSEL0_BANK0_PIN02_SSP2_D2 0x02 167#define HW_PINCTRL_MUXSEL0_BANK0_PIN02_GPIO 0x03 168 169/* Pin 45, GPMI_D01 pin function selection */ 170#define HW_PINCTRL_MUXSEL0_BANK0_PIN01_GPMI_DATA01 0x00 171#define HW_PINCTRL_MUXSEL0_BANK0_PIN01_LCD_D9 0x01 172#define HW_PINCTRL_MUXSEL0_BANK0_PIN01_SSP2_D1 0x02 173#define HW_PINCTRL_MUXSEL0_BANK0_PIN01_GPIO 0x03 174 175/* Pin 44, GPMI_D00 pin function selection */ 176#define HW_PINCTRL_MUXSEL0_BANK0_PIN00_GPMI_DATA00 0x00 177#define HW_PINCTRL_MUXSEL0_BANK0_PIN00_LCD_D8 0x01 178#define HW_PINCTRL_MUXSEL0_BANK0_PIN00_SSP2_D0 0x02 179#define HW_PINCTRL_MUXSEL0_BANK0_PIN00_GPIO 0x03 180 181/* 182 * PINCTRL Pin Mux Select Register 1. 183 */ 184#define HW_PINCTRL_MUXSEL1 0x110 185#define HW_PINCTRL_MUXSEL1_SET 0x114 186#define HW_PINCTRL_MUXSEL1_CLR 0x118 187#define HW_PINCTRL_MUXSEL1_TOG 0x11C 188 189#define HW_PINCTRL_MUXSEL1_BANK0_PIN31 __BITS(31, 30) 190#define HW_PINCTRL_MUXSEL1_BANK0_PIN30 __BITS(29, 28) 191#define HW_PINCTRL_MUXSEL1_BANK0_PIN29 __BITS(27, 26) 192#define HW_PINCTRL_MUXSEL1_BANK0_PIN28 __BITS(25, 24) 193#define HW_PINCTRL_MUXSEL1_BANK0_PIN27 __BITS(23, 22) 194#define HW_PINCTRL_MUXSEL1_BANK0_PIN26 __BITS(21, 20) 195#define HW_PINCTRL_MUXSEL1_BANK0_PIN25 __BITS(19, 18) 196#define HW_PINCTRL_MUXSEL1_BANK0_PIN24 __BITS(17, 16) 197#define HW_PINCTRL_MUXSEL1_BANK0_PIN23 __BITS(15, 14) 198#define HW_PINCTRL_MUXSEL1_BANK0_PIN22 __BITS(13, 12) 199#define HW_PINCTRL_MUXSEL1_BANK0_PIN21 __BITS(11, 10) 200#define HW_PINCTRL_MUXSEL1_BANK0_PIN20 __BITS(9, 8) 201#define HW_PINCTRL_MUXSEL1_BANK0_PIN19 __BITS(7, 6) 202#define HW_PINCTRL_MUXSEL1_BANK0_PIN18 __BITS(5, 4) 203#define HW_PINCTRL_MUXSEL1_BANK0_PIN17 __BITS(3, 2) 204#define HW_PINCTRL_MUXSEL1_BANK0_PIN16 __BITS(1, 0) 205 206/* Pin 4, I2C_SDA pin function selection */ 207#define HW_PINCTRL_MUXSEL1_BANK0_PIN31_I2C_SD 0x00 208#define HW_PINCTRL_MUXSEL1_BANK0_PIN31_GPMI_CE2N 0x01 209#define HW_PINCTRL_MUXSEL1_BANK0_PIN31_AUART1_RX 0x02 210#define HW_PINCTRL_MUXSEL1_BANK0_PIN31_GPIO 0x03 211 212/* Pin 2, I2C_SCL pin function selection */ 213#define HW_PINCTRL_MUXSEL1_BANK0_PIN30_I2C_CLK 0x00 214#define HW_PINCTRL_MUXSEL1_BANK0_PIN30_GPMI_READY2 0x01 215#define HW_PINCTRL_MUXSEL1_BANK0_PIN30_AUART1_TX 0x02 216#define HW_PINCTRL_MUXSEL1_BANK0_PIN30_GPIO 0x03 217 218/* Pin 69, AUART1_TX pin function selection */ 219#define HW_PINCTRL_MUXSEL1_BANK0_PIN29_AUART1_TX 0x00 220#define HW_PINCTRL_MUXSEL1_BANK0_PIN29_RESERVED 0x01 221#define HW_PINCTRL_MUXSEL1_BANK0_PIN29_SSP1_D7 0x02 222#define HW_PINCTRL_MUXSEL1_BANK0_PIN29_GPIO 0x03 223 224/* Pin 68, AUART1_RX pin function selection */ 225#define HW_PINCTRL_MUXSEL1_BANK0_PIN28_AUART1_RX 0x00 226#define HW_PINCTRL_MUXSEL1_BANK0_PIN28_RESERVED 0x01 227#define HW_PINCTRL_MUXSEL1_BANK0_PIN28_SSP1_D6 0x02 228#define HW_PINCTRL_MUXSEL1_BANK0_PIN28_GPIO 0x03 229 230/* Pin 67, AUART1_RTS pin function selection */ 231#define HW_PINCTRL_MUXSEL1_BANK0_PIN27_AUART1_RTS 0x00 232#define HW_PINCTRL_MUXSEL1_BANK0_PIN27_RESERVED 0x01 233#define HW_PINCTRL_MUXSEL1_BANK0_PIN27_SSP1_D5 0x02 234#define HW_PINCTRL_MUXSEL1_BANK0_PIN27_GPIO 0x03 235 236/* Pin 66, AUART1_CTS pin function selection */ 237#define HW_PINCTRL_MUXSEL1_BANK0_PIN26_AUART1_CTS 0x00 238#define HW_PINCTRL_MUXSEL1_BANK0_PIN26_ESERVED 0x01 239#define HW_PINCTRL_MUXSEL1_BANK0_PIN26_SSP1_D4 0x02 240#define HW_PINCTRL_MUXSEL1_BANK0_PIN26_GPIO 0x03 241 242/* Pin 60, GPMI_RDN pin function selection */ 243#define HW_PINCTRL_MUXSEL1_BANK0_PIN25_GPMI_RDN 0x00 244#define HW_PINCTRL_MUXSEL1_BANK0_PIN25_RESERVED1 0x01 245#define HW_PINCTRL_MUXSEL1_BANK0_PIN25_RESERVED2 0x02 246#define HW_PINCTRL_MUXSEL1_BANK0_PIN25_GPIO 0x03 247 248/* Pin 65, GPMI_WRN pin function selection */ 249#define HW_PINCTRL_MUXSEL1_BANK0_PIN24_GPMI_WRN 0x00 250#define HW_PINCTRL_MUXSEL1_BANK0_PIN24_RESERVED 0x01 251#define HW_PINCTRL_MUXSEL1_BANK0_PIN24_SSP2_SCK 0x02 252#define HW_PINCTRL_MUXSEL1_BANK0_PIN24_GPIO 0x03 253 254/* Pin 64, GPMI_WPN pin function selection */ 255#define HW_PINCTRL_MUXSEL1_BANK0_PIN23_GPMI_WPN 0x00 256#define HW_PINCTRL_MUXSEL1_BANK0_PIN23_RESERVED1 0x01 257#define HW_PINCTRL_MUXSEL1_BANK0_PIN23_RESERVED2 0x02 258#define HW_PINCTRL_MUXSEL1_BANK0_PIN23_GPIO 0x03 259 260/* Pin 63, GPMI_RDY3 pin function selection */ 261#define HW_PINCTRL_MUXSEL1_BANK0_PIN22_GPMI_READY3 0x00 262#define HW_PINCTRL_MUXSEL1_BANK0_PIN22_RESERVED1 0x01 263#define HW_PINCTRL_MUXSEL1_BANK0_PIN22_RESERVED2 0x02 264#define HW_PINCTRL_MUXSEL1_BANK0_PIN22_GPIO 0x03 265 266/* Pin 62, GPMI_RDY2 pin function selection */ 267#define HW_PINCTRL_MUXSEL1_BANK0_PIN21_GPMI_READY2 0x00 268#define HW_PINCTRL_MUXSEL1_BANK0_PIN21_RESERVED1 0x01 269#define HW_PINCTRL_MUXSEL1_BANK0_PIN21_RESERVED2 0x02 270#define HW_PINCTRL_MUXSEL1_BANK0_PIN21_GPIO 0x03 271 272/* Pin 43, GPMI_RDY1 pin function selection */ 273#define HW_PINCTRL_MUXSEL1_BANK0_PIN20_GPMI_READY1 0x00 274#define HW_PINCTRL_MUXSEL1_BANK0_PIN20_RESERVED 0x01 275#define HW_PINCTRL_MUXSEL1_BANK0_PIN20_SSP2_CMD 0x02 276#define HW_PINCTRL_MUXSEL1_BANK0_PIN20_GPIO 0x03 277 278/* Pin 61, GPMI_RDY0 pin function selection */ 279#define HW_PINCTRL_MUXSEL1_BANK0_PIN19_GPMI_READY0 0x00 280#define HW_PINCTRL_MUXSEL1_BANK0_PIN19_RESERVED 0x01 281#define HW_PINCTRL_MUXSEL1_BANK0_PIN19_SSP2_DETECT 0x02 282#define HW_PINCTRL_MUXSEL1_BANK0_PIN19_GPIO 0x03 283 284/* Pin 42, GPMI_CE2N pin function selection */ 285#define HW_PINCTRL_MUXSEL1_BANK0_PIN18_GPMI_CE2N 0x00 286#define HW_PINCTRL_MUXSEL1_BANK0_PIN18_RESERVED1 0x01 287#define HW_PINCTRL_MUXSEL1_BANK0_PIN18_RESERVED2 0x02 288#define HW_PINCTRL_MUXSEL1_BANK0_PIN18_GPIO 0x03 289 290/* Pin 41, GPMI_ALE pin function selection */ 291#define HW_PINCTRL_MUXSEL1_BANK0_PIN17_GPMI_ALE 0x00 292#define HW_PINCTRL_MUXSEL1_BANK0_PIN17_LCD_D17 0x01 293#define HW_PINCTRL_MUXSEL1_BANK0_PIN17_RESERVED 0x02 294#define HW_PINCTRL_MUXSEL1_BANK0_PIN17_GPIO 0x03 295 296/* Pin 40, GPMI_CLE pin function selection */ 297#define HW_PINCTRL_MUXSEL1_BANK0_PIN16_GPMI_CLE 0x00 298#define HW_PINCTRL_MUXSEL1_BANK0_PIN16_LCD_D16 0x01 299#define HW_PINCTRL_MUXSEL1_BANK0_PIN16_RESERVED 0x02 300#define HW_PINCTRL_MUXSEL1_BANK0_PIN16_GPIO 0x03 301 302/* 303 * PINCTRL Pin Mux Select Register 2. 304 */ 305#define HW_PINCTRL_MUXSEL2 0x120 306#define HW_PINCTRL_MUXSEL2_SET 0x124 307#define HW_PINCTRL_MUXSEL2_CLR 0x128 308#define HW_PINCTRL_MUXSEL2_TOG 0x12C 309 310#define HW_PINCTRL_MUXSEL2_BANK1_PIN15 __BITS(31, 30) 311#define HW_PINCTRL_MUXSEL2_BANK1_PIN14 __BITS(29, 28) 312#define HW_PINCTRL_MUXSEL2_BANK1_PIN13 __BITS(27, 26) 313#define HW_PINCTRL_MUXSEL2_BANK1_PIN12 __BITS(25, 24) 314#define HW_PINCTRL_MUXSEL2_BANK1_PIN11 __BITS(23, 22) 315#define HW_PINCTRL_MUXSEL2_BANK1_PIN10 __BITS(21, 20) 316#define HW_PINCTRL_MUXSEL2_BANK1_PIN09 __BITS(19, 18) 317#define HW_PINCTRL_MUXSEL2_BANK1_PIN08 __BITS(17, 16) 318#define HW_PINCTRL_MUXSEL2_BANK1_PIN07 __BITS(15, 14) 319#define HW_PINCTRL_MUXSEL2_BANK1_PIN06 __BITS(13, 12) 320#define HW_PINCTRL_MUXSEL2_BANK1_PIN05 __BITS(11, 10) 321#define HW_PINCTRL_MUXSEL2_BANK1_PIN04 __BITS(9, 8) 322#define HW_PINCTRL_MUXSEL2_BANK1_PIN03 __BITS(7, 6) 323#define HW_PINCTRL_MUXSEL2_BANK1_PIN02 __BITS(5, 4) 324#define HW_PINCTRL_MUXSEL2_BANK1_PIN01 __BITS(3, 2) 325#define HW_PINCTRL_MUXSEL2_BANK1_PIN00 __BITS(1, 0) 326 327/* Pin 15, LCD_D15 pin function selection */ 328#define HW_PINCTRL_MUXSEL2_BANK1_PIN15_LCD_D15 0x00 329#define HW_PINCTRL_MUXSEL2_BANK1_PIN15_ETM_DA7 0x01 330#define HW_PINCTRL_MUXSEL2_BANK1_PIN15_SAIF1_SDATA1 0x02 331#define HW_PINCTRL_MUXSEL2_BANK1_PIN15_GPIO 0x03 332 333/* Pin 17, LCD_D14 pin function selection */ 334#define HW_PINCTRL_MUXSEL2_BANK1_PIN14_LCD_D14 0x00 335#define HW_PINCTRL_MUXSEL2_BANK1_PIN14_ETM_DA6 0x01 336#define HW_PINCTRL_MUXSEL2_BANK1_PIN14_SAIF1_SDATA2 0x02 337#define HW_PINCTRL_MUXSEL2_BANK1_PIN14_GPIO 0x03 338 339/* Pin 19, LCD_D13 pin function selection */ 340#define HW_PINCTRL_MUXSEL2_BANK1_PIN13_LCD_D13 0x00 341#define HW_PINCTRL_MUXSEL2_BANK1_PIN13_ETM_DA5 0x01 342#define HW_PINCTRL_MUXSEL2_BANK1_PIN13_SAIF2_SDATA2 0x02 343#define HW_PINCTRL_MUXSEL2_BANK1_PIN13_GPIO 0x03 344 345/* Pin 22, LCD_D12 pin function selection */ 346#define HW_PINCTRL_MUXSEL2_BANK1_PIN12_LCD_D12 0x00 347#define HW_PINCTRL_MUXSEL2_BANK1_PIN12_ETM_DA4 0x01 348#define HW_PINCTRL_MUXSEL2_BANK1_PIN12_SAIF2_SDATA1 0x02 349#define HW_PINCTRL_MUXSEL2_BANK1_PIN12_GPIO 0x03 350 351/* Pin 24, LCD_D11 pin function selection */ 352#define HW_PINCTRL_MUXSEL2_BANK1_PIN11_LCD_D11 0x00 353#define HW_PINCTRL_MUXSEL2_BANK1_PIN11_ETM_DA3 0x01 354#define HW_PINCTRL_MUXSEL2_BANK1_PIN11_SAIF_LRCLK 0x02 355#define HW_PINCTRL_MUXSEL2_BANK1_PIN11_GPIO 0x03 356 357/* Pin 26, LCD_D10 pin function selection */ 358#define HW_PINCTRL_MUXSEL2_BANK1_PIN10_LCD_D10 0x00 359#define HW_PINCTRL_MUXSEL2_BANK1_PIN10_ETM_DA2 0x01 360#define HW_PINCTRL_MUXSEL2_BANK1_PIN10_SAIF_BITCLK 0x02 361#define HW_PINCTRL_MUXSEL2_BANK1_PIN10_GPIO 0x03 362 363/* Pin 28, LCD_D09 pin function selection */ 364#define HW_PINCTRL_MUXSEL2_BANK1_PIN09_LCD_D9 0x00 365#define HW_PINCTRL_MUXSEL2_BANK1_PIN09_ETM_DA1 0x01 366#define HW_PINCTRL_MUXSEL2_BANK1_PIN09_SAIF1_SDATA0 0x02 367#define HW_PINCTRL_MUXSEL2_BANK1_PIN09_GPIO 0x03 368 369/* Pin 27, LCD_D08 pin function selection */ 370#define HW_PINCTRL_MUXSEL2_BANK1_PIN08_LCD_D8 0x00 371#define HW_PINCTRL_MUXSEL2_BANK1_PIN08_ETM_DA0 0x01 372#define HW_PINCTRL_MUXSEL2_BANK1_PIN08_SAIF2_SDATA0 0x02 373#define HW_PINCTRL_MUXSEL2_BANK1_PIN08_GPIO 0x03 374 375/* Pin 25, LCD_D07 pin function selection */ 376#define HW_PINCTRL_MUXSEL2_BANK1_PIN07_LCD_D7 0x00 377#define HW_PINCTRL_MUXSEL2_BANK1_PIN07_ETM_DA15 0x01 378#define HW_PINCTRL_MUXSEL2_BANK1_PIN07_RESERVED 0x02 379#define HW_PINCTRL_MUXSEL2_BANK1_PIN07_GPIO 0x03 380 381/* Pin 23, LCD_D06 pin function selection */ 382#define HW_PINCTRL_MUXSEL2_BANK1_PIN06_LCD_D6 0x00 383#define HW_PINCTRL_MUXSEL2_BANK1_PIN06_ETM_DA14 0x01 384#define HW_PINCTRL_MUXSEL2_BANK1_PIN06_RESERVED 0x02 385#define HW_PINCTRL_MUXSEL2_BANK1_PIN06_GPIO 0x03 386 387/* Pin 21, LCD_D05 pin function selection */ 388#define HW_PINCTRL_MUXSEL2_BANK1_PIN05_LCD_D5 0x00 389#define HW_PINCTRL_MUXSEL2_BANK1_PIN05_ETM_DA13 0x01 390#define HW_PINCTRL_MUXSEL2_BANK1_PIN05_RESERVED 0x02 391#define HW_PINCTRL_MUXSEL2_BANK1_PIN05_GPIO 0x03 392 393/* Pin 18, LCD_D04 pin function selection */ 394#define HW_PINCTRL_MUXSEL2_BANK1_PIN04_LCD_D4 0x00 395#define HW_PINCTRL_MUXSEL2_BANK1_PIN04_ETM_DA12 0x01 396#define HW_PINCTRL_MUXSEL2_BANK1_PIN04_RESERVED 0x02 397#define HW_PINCTRL_MUXSEL2_BANK1_PIN04_GPIO 0x03 398 399/* Pin 16, LCD_D03 pin function selection */ 400#define HW_PINCTRL_MUXSEL2_BANK1_PIN03_LCD_D3 0x00 401#define HW_PINCTRL_MUXSEL2_BANK1_PIN03_ETM_DA11 0x01 402#define HW_PINCTRL_MUXSEL2_BANK1_PIN03_RESERVED 0x02 403#define HW_PINCTRL_MUXSEL2_BANK1_PIN03_GPIO 0x03 404 405/* Pin 14, LCD_D02 pin function selection */ 406#define HW_PINCTRL_MUXSEL2_BANK1_PIN02_LCD_D2 0x00 407#define HW_PINCTRL_MUXSEL2_BANK1_PIN02_ETM_DA10 0x01 408#define HW_PINCTRL_MUXSEL2_BANK1_PIN02_RESERVED 0x02 409#define HW_PINCTRL_MUXSEL2_BANK1_PIN02_GPIO 0x03 410 411/* Pin 12, LCD_D01 pin function selection */ 412#define HW_PINCTRL_MUXSEL2_BANK1_PIN01_LCD_D1 0x00 413#define HW_PINCTRL_MUXSEL2_BANK1_PIN01_ETM_DA9 0x01 414#define HW_PINCTRL_MUXSEL2_BANK1_PIN01_RESERVED 0x02 415#define HW_PINCTRL_MUXSEL2_BANK1_PIN01_GPIO 0x03 416 417/* Pin 10, LCD_D00 pin function selection */ 418#define HW_PINCTRL_MUXSEL2_BANK1_PIN00_LCD_D0 0x00 419#define HW_PINCTRL_MUXSEL2_BANK1_PIN00_ETM_DA8 0x01 420#define HW_PINCTRL_MUXSEL2_BANK1_PIN00_RESERVED 0x02 421#define HW_PINCTRL_MUXSEL2_BANK1_PIN00_GPIO 0x03 422 423/* 424 * PINCTRL Pin Mux Select Register 3. 425 */ 426#define HW_PINCTRL_MUXSEL3 0x130 427#define HW_PINCTRL_MUXSEL3_SET 0x134 428#define HW_PINCTRL_MUXSEL3_CLR 0x138 429#define HW_PINCTRL_MUXSEL3_TOG 0x13C 430 431#define HW_PINCTRL_MUXSEL3_RSRVD0 __BITS(31, 30) 432#define HW_PINCTRL_MUXSEL3_BANK1_PIN30 __BITS(29, 28) 433#define HW_PINCTRL_MUXSEL3_BANK1_PIN29 __BITS(27, 26) 434#define HW_PINCTRL_MUXSEL3_BANK1_PIN28 __BITS(25, 24) 435#define HW_PINCTRL_MUXSEL3_BANK1_PIN27 __BITS(23, 22) 436#define HW_PINCTRL_MUXSEL3_BANK1_PIN26 __BITS(21, 20) 437#define HW_PINCTRL_MUXSEL3_BANK1_PIN25 __BITS(19, 18) 438#define HW_PINCTRL_MUXSEL3_BANK1_PIN24 __BITS(17, 16) 439#define HW_PINCTRL_MUXSEL3_BANK1_PIN23 __BITS(15, 14) 440#define HW_PINCTRL_MUXSEL3_BANK1_PIN22 __BITS(13, 12) 441#define HW_PINCTRL_MUXSEL3_BANK1_PIN21 __BITS(11, 10) 442#define HW_PINCTRL_MUXSEL3_BANK1_PIN20 __BITS(9, 8) 443#define HW_PINCTRL_MUXSEL3_BANK1_PIN19 __BITS(7, 6) 444#define HW_PINCTRL_MUXSEL3_BANK1_PIN18 __BITS(5, 4) 445#define HW_PINCTRL_MUXSEL3_BANK1_PIN17 __BITS(3, 2) 446#define HW_PINCTRL_MUXSEL3_BANK1_PIN16 __BITS(1, 0) 447 448/* Always write zeroes to this field */ 449#define HW_PINCTRL_MUXSEL3_RSRVD0_ZERO 0x00 450 451/* Pin 131, PWM4 pin function selection */ 452#define HW_PINCTRL_MUXSEL3_BANK1_PIN30_PWM4 0x00 453#define HW_PINCTRL_MUXSEL3_BANK1_PIN30_ETM_TCLK 0x01 454#define HW_PINCTRL_MUXSEL3_BANK1_PIN30_AUART1_RTS 0x02 455#define HW_PINCTRL_MUXSEL3_BANK1_PIN30_GPIO 0x03 456 457/* Pin 130, PWM3 pin function selection */ 458#define HW_PINCTRL_MUXSEL3_BANK1_PIN29_PWM3 0x00 459#define HW_PINCTRL_MUXSEL3_BANK1_PIN29_ETM_TCTL 0x01 460#define HW_PINCTRL_MUXSEL3_BANK1_PIN29_AUART1_CTS 0x02 461#define HW_PINCTRL_MUXSEL3_BANK1_PIN29_GPIO 0x03 462 463/* Pin 129, PWM2 pin function selection */ 464#define HW_PINCTRL_MUXSEL3_BANK1_PIN28_PWM2 0x00 465#define HW_PINCTRL_MUXSEL3_BANK1_PIN28_GPMI_READY3 0x01 466#define HW_PINCTRL_MUXSEL3_BANK1_PIN28_RESERVED 0x02 467#define HW_PINCTRL_MUXSEL3_BANK1_PIN28_GPIO 0x03 468 469/* Pin 3, PWM1 pin function selection */ 470#define HW_PINCTRL_MUXSEL3_BANK1_PIN27_PWM1 0x00 471#define HW_PINCTRL_MUXSEL3_BANK1_PIN27_TIMROT2 0x01 472#define HW_PINCTRL_MUXSEL3_BANK1_PIN27_DUART_TX 0x02 473#define HW_PINCTRL_MUXSEL3_BANK1_PIN27_GPIO 0x03 474 475/* Pin 1, PWM0 pin function selection */ 476#define HW_PINCTRL_MUXSEL3_BANK1_PIN26_PWM0 0x00 477#define HW_PINCTRL_MUXSEL3_BANK1_PIN26_TIMROT1 0x01 478#define HW_PINCTRL_MUXSEL3_BANK1_PIN26_DUART_RX 0x02 479#define HW_PINCTRL_MUXSEL3_BANK1_PIN26_GPIO 0x03 480 481/* Pin 35, LCD_VSYNC pin function selection */ 482#define HW_PINCTRL_MUXSEL3_BANK1_PIN25_LCD_VSYNC 0x00 483#define HW_PINCTRL_MUXSEL3_BANK1_PIN25_LCD_BUSY 0x01 484#define HW_PINCTRL_MUXSEL3_BANK1_PIN25_RESERVED 0x02 485#define HW_PINCTRL_MUXSEL3_BANK1_PIN25_GPIO 0x03 486 487/* Pin 34, LCD_HSYNC pin function selection */ 488#define HW_PINCTRL_MUXSEL3_BANK1_PIN24_LCD_HSYNC 0x00 489#define HW_PINCTRL_MUXSEL3_BANK1_PIN24_I2C_SD 0x01 490#define HW_PINCTRL_MUXSEL3_BANK1_PIN24_RESERVED 0x02 491#define HW_PINCTRL_MUXSEL3_BANK1_PIN24_GPIO 0x03 492 493/* Pin 30, LCD_ENABLE pin function selection */ 494#define HW_PINCTRL_MUXSEL3_BANK1_PIN23_LCD_ENABLE 0x00 495#define HW_PINCTRL_MUXSEL3_BANK1_PIN23_I2C_CLK 0x01 496#define HW_PINCTRL_MUXSEL3_BANK1_PIN23_RESERVED 0x02 497#define HW_PINCTRL_MUXSEL3_BANK1_PIN23_GPIO 0x03 498 499/* Pin 36, LCD_DOTCK pin function selection */ 500#define HW_PINCTRL_MUXSEL3_BANK1_PIN22_LCD_DOTCK 0x00 501#define HW_PINCTRL_MUXSEL3_BANK1_PIN22_GPMI_READY3 0x01 502#define HW_PINCTRL_MUXSEL3_BANK1_PIN22_RESERVED 0x02 503#define HW_PINCTRL_MUXSEL3_BANK1_PIN22_GPIO 0x03 504 505/* Pin 29, LCD_CS pin function selection */ 506#define HW_PINCTRL_MUXSEL3_BANK1_PIN21_LCD_CS 0x00 507#define HW_PINCTRL_MUXSEL3_BANK1_PIN21_RESERVED1 0x01 508#define HW_PINCTRL_MUXSEL3_BANK1_PIN21_RESERVED2 0x02 509#define HW_PINCTRL_MUXSEL3_BANK1_PIN21_GPIO 0x03 510 511/* Pin 32, LCD_WR pin function selection */ 512#define HW_PINCTRL_MUXSEL3_BANK1_PIN20_LCD_WR 0x00 513#define HW_PINCTRL_MUXSEL3_BANK1_PIN20_RESERVED1 0x01 514#define HW_PINCTRL_MUXSEL3_BANK1_PIN20_RESERVED2 0x02 515#define HW_PINCTRL_MUXSEL3_BANK1_PIN20_GPIO 0x03 516 517/* Pin 33, LCD_RS pin function selection */ 518#define HW_PINCTRL_MUXSEL3_BANK1_PIN19_LCD_RS 0x00 519#define HW_PINCTRL_MUXSEL3_BANK1_PIN19_ETM_TCLK 0x01 520#define HW_PINCTRL_MUXSEL3_BANK1_PIN19_RESERVED 0x02 521#define HW_PINCTRL_MUXSEL3_BANK1_PIN19_GPIO 0x03 522 523/* Pin 31, LCD_RESET pin function selection */ 524#define HW_PINCTRL_MUXSEL3_BANK1_PIN18_LCD_RESET 0x00 525#define HW_PINCTRL_MUXSEL3_BANK1_PIN18_ETM_TCTL 0x01 526#define HW_PINCTRL_MUXSEL3_BANK1_PIN18_GPMI_CE3N 0x02 527#define HW_PINCTRL_MUXSEL3_BANK1_PIN18_GPIO 0x03 528 529/* Pin 11, LCD_D17 pin function selection */ 530#define HW_PINCTRL_MUXSEL3_BANK1_PIN17_LCD_D17 0x00 531#define HW_PINCTRL_MUXSEL3_BANK1_PIN17_RESERVED1 0x01 532#define HW_PINCTRL_MUXSEL3_BANK1_PIN17_RESERVED2 0x02 533#define HW_PINCTRL_MUXSEL3_BANK1_PIN17_GPIO 0x03 534 535/* Pin 13, LCD_D16 pin function selection */ 536#define HW_PINCTRL_MUXSEL3_BANK1_PIN16_LCD_D16 0x00 537#define HW_PINCTRL_MUXSEL3_BANK1_PIN16_RESERVED 0x01 538#define HW_PINCTRL_MUXSEL3_BANK1_PIN16_SAIF_ALT_BITCLK 0x02 539#define HW_PINCTRL_MUXSEL3_BANK1_PIN16_GPIO 0x03 540 541/* 542 * PINCTRL Pin Mux Select Register 4. 543 */ 544#define HW_PINCTRL_MUXSEL4 0x140 545#define HW_PINCTRL_MUXSEL4_SET 0x144 546#define HW_PINCTRL_MUXSEL4_CLR 0x148 547#define HW_PINCTRL_MUXSEL4_TOG 0x14C 548 549#define HW_PINCTRL_MUXSEL4_BANK2_PIN15 __BITS(31,30) 550#define HW_PINCTRL_MUXSEL4_BANK2_PIN14 __BITS(29,28) 551#define HW_PINCTRL_MUXSEL4_BANK2_PIN13 __BITS(27,26) 552#define HW_PINCTRL_MUXSEL4_BANK2_PIN12 __BITS(25,24) 553#define HW_PINCTRL_MUXSEL4_BANK2_PIN11 __BITS(23,22) 554#define HW_PINCTRL_MUXSEL4_BANK2_PIN10 __BITS(21,20) 555#define HW_PINCTRL_MUXSEL4_BANK2_PIN09 __BITS(19,18) 556#define HW_PINCTRL_MUXSEL4_BANK2_PIN08 __BITS(17,16) 557#define HW_PINCTRL_MUXSEL4_BANK2_PIN07 __BITS(15,14) 558#define HW_PINCTRL_MUXSEL4_BANK2_PIN06 __BITS(13,12) 559#define HW_PINCTRL_MUXSEL4_BANK2_PIN05 __BITS(11,10) 560#define HW_PINCTRL_MUXSEL4_BANK2_PIN04 __BITS(9,8) 561#define HW_PINCTRL_MUXSEL4_BANK2_PIN03 __BITS(7,6) 562#define HW_PINCTRL_MUXSEL4_BANK2_PIN02 __BITS(5,4) 563#define HW_PINCTRL_MUXSEL4_BANK2_PIN01 __BITS(3,2) 564#define HW_PINCTRL_MUXSEL4_BANK2_PIN00 __BITS(1,0) 565 566/* Pin 108, EMI_A06 pin function selection */ 567#define HW_PINCTRL_MUXSEL4_BANK2_PIN15_EMI_ADDR06 0x00 568#define HW_PINCTRL_MUXSEL4_BANK2_PIN15_RESERVED1 0x01 569#define HW_PINCTRL_MUXSEL4_BANK2_PIN15_RESERVED2 0x02 570#define HW_PINCTRL_MUXSEL4_BANK2_PIN15_GPIO 0x03 571 572/* Pin 107, EMI_A05 pin function selection */ 573#define HW_PINCTRL_MUXSEL4_BANK2_PIN14_EMI_ADDR05 0x00 574#define HW_PINCTRL_MUXSEL4_BANK2_PIN14_RESERVED1 0x01 575#define HW_PINCTRL_MUXSEL4_BANK2_PIN14_RESERVED2 0x02 576#define HW_PINCTRL_MUXSEL4_BANK2_PIN14_GPIO 0x03 577 578/* Pin 109, EMI_A04 pin function selection */ 579#define HW_PINCTRL_MUXSEL4_BANK2_PIN13_EMI_ADDR04 0x00 580#define HW_PINCTRL_MUXSEL4_BANK2_PIN13_RESERVED1 0x01 581#define HW_PINCTRL_MUXSEL4_BANK2_PIN13_RESERVED2 0x02 582#define HW_PINCTRL_MUXSEL4_BANK2_PIN13_GPIO 0x03 583 584/* Pin 110, EMI_A03 pin function selection */ 585#define HW_PINCTRL_MUXSEL4_BANK2_PIN12_EMI_ADDR03 0x00 586#define HW_PINCTRL_MUXSEL4_BANK2_PIN12_RESERVED1 0x01 587#define HW_PINCTRL_MUXSEL4_BANK2_PIN12_RESERVED2 0x02 588#define HW_PINCTRL_MUXSEL4_BANK2_PIN12_GPIO 0x03 589 590/* Pin 111, EMI_A02 pin function selection */ 591#define HW_PINCTRL_MUXSEL4_BANK2_PIN11_EMI_ADDR02 0x00 592#define HW_PINCTRL_MUXSEL4_BANK2_PIN11_RESERVED1 0x01 593#define HW_PINCTRL_MUXSEL4_BANK2_PIN11_RESERVED2 0x02 594#define HW_PINCTRL_MUXSEL4_BANK2_PIN11_GPIO 0x03 595 596/* Pin 112, EMI_A01 pin function selection */ 597#define HW_PINCTRL_MUXSEL4_BANK2_PIN10_EMI_ADDR01 0x00 598#define HW_PINCTRL_MUXSEL4_BANK2_PIN10_RESERVED1 0x01 599#define HW_PINCTRL_MUXSEL4_BANK2_PIN10_RESERVED2 0x02 600#define HW_PINCTRL_MUXSEL4_BANK2_PIN10_GPIO 0x03 601 602/* Pin 113, EMI_A00 pin function selection */ 603#define HW_PINCTRL_MUXSEL4_BANK2_PIN09_EMI_ADDR00 0x00 604#define HW_PINCTRL_MUXSEL4_BANK2_PIN09_RESERVED1 0x01 605#define HW_PINCTRL_MUXSEL4_BANK2_PIN09_RESERVED2 0x02 606#define HW_PINCTRL_MUXSEL4_BANK2_PIN09_GPIO 0x03 607 608/* Pin 38, ROTARYB pin function selection */ 609#define HW_PINCTRL_MUXSEL4_BANK2_PIN08_TIMROT2 0x00 610#define HW_PINCTRL_MUXSEL4_BANK2_PIN08_AUART2_CTS 0x01 611#define HW_PINCTRL_MUXSEL4_BANK2_PIN08_GPMI_CE3N 0x02 612#define HW_PINCTRL_MUXSEL4_BANK2_PIN08_GPIO 0x03 613 614/* Pin 37, ROTARYA pin function selection */ 615#define HW_PINCTRL_MUXSEL4_BANK2_PIN07_TIMROT1 0x00 616#define HW_PINCTRL_MUXSEL4_BANK2_PIN07_AUART2_RTS 0x01 617#define HW_PINCTRL_MUXSEL4_BANK2_PIN07_SPDIF 0x02 618#define HW_PINCTRL_MUXSEL4_BANK2_PIN07_GPIO 0x03 619 620/* Pin 127, SSP1_SCK pin function selection */ 621#define HW_PINCTRL_MUXSEL4_BANK2_PIN06_SSP1_SCK 0x00 622#define HW_PINCTRL_MUXSEL4_BANK2_PIN06_RESERVED 0x01 623#define HW_PINCTRL_MUXSEL4_BANK2_PIN06_ALT_JTAG_TRST_N 0x02 624#define HW_PINCTRL_MUXSEL4_BANK2_PIN06_GPIO 0x03 625 626/* Pin 125, SSP1_DATA3 pin function selection */ 627#define HW_PINCTRL_MUXSEL4_BANK2_PIN05_SSP1_D3 0x00 628#define HW_PINCTRL_MUXSEL4_BANK2_PIN05_RESERVED 0x01 629#define HW_PINCTRL_MUXSEL4_BANK2_PIN05_ALT_JTAG_TMS 0x02 630#define HW_PINCTRL_MUXSEL4_BANK2_PIN05_GPIO 0x03 631 632/* Pin 124, SSP1_DATA2 pin function selection */ 633#define HW_PINCTRL_MUXSEL4_BANK2_PIN04_SSP1_D2 0x00 634#define HW_PINCTRL_MUXSEL4_BANK2_PIN04_I2C_SD 0x01 635#define HW_PINCTRL_MUXSEL4_BANK2_PIN04_ALT_JTAG_RTCK 0x02 636#define HW_PINCTRL_MUXSEL4_BANK2_PIN04_GPIO 0x03 637 638/* Pin 123, SSP1_DATA1 pin function selection */ 639#define HW_PINCTRL_MUXSEL4_BANK2_PIN03_SSP1_D1 0x00 640#define HW_PINCTRL_MUXSEL4_BANK2_PIN03_I2C_CLK 0x01 641#define HW_PINCTRL_MUXSEL4_BANK2_PIN03_ALT_JTAG_TCK 0x02 642#define HW_PINCTRL_MUXSEL4_BANK2_PIN03_GPIO 0x03 643 644/* Pin 122, SSP1_DATA0 pin function selection */ 645#define HW_PINCTRL_MUXSEL4_BANK2_PIN02_SSP1_D0 0x00 646#define HW_PINCTRL_MUXSEL4_BANK2_PIN02_RESERVED 0x01 647#define HW_PINCTRL_MUXSEL4_BANK2_PIN02_ALT_JTAG_TDI 0x02 648#define HW_PINCTRL_MUXSEL4_BANK2_PIN02_GPIO 0x03 649 650/* Pin 126, SSP1_DETECT pin function selection */ 651#define HW_PINCTRL_MUXSEL4_BANK2_PIN01_SSP1_DETECT 0x00 652#define HW_PINCTRL_MUXSEL4_BANK2_PIN01_GPMI_CE3N 0x01 653#define HW_PINCTRL_MUXSEL4_BANK2_PIN01_USB_ID 0x02 654#define HW_PINCTRL_MUXSEL4_BANK2_PIN01_GPIO 0x03 655 656/* Pin 121, SSP1_CMD pin function selection */ 657#define HW_PINCTRL_MUXSEL4_BANK2_PIN00_SSP1_CMD 0x00 658#define HW_PINCTRL_MUXSEL4_BANK2_PIN00_RESERVED 0x01 659#define HW_PINCTRL_MUXSEL4_BANK2_PIN00_ALT_JTAG_TDO 0x02 660#define HW_PINCTRL_MUXSEL4_BANK2_PIN00_GPIO 0x03 661 662/* 663 * PINCTRL Pin Mux Select Register 5. 664 */ 665#define HW_PINCTRL_MUXSEL5 0x150 666#define HW_PINCTRL_MUXSEL5_SET 0x154 667#define HW_PINCTRL_MUXSEL5_CLR 0x158 668#define HW_PINCTRL_MUXSEL5_TOG 0x15C 669 670#define HW_PINCTRL_MUXSEL5_BANK2_PIN31 __BITS(31,30) 671#define HW_PINCTRL_MUXSEL5_BANK2_PIN30 __BITS(29,28) 672#define HW_PINCTRL_MUXSEL5_BANK2_PIN29 __BITS(27,26) 673#define HW_PINCTRL_MUXSEL5_BANK2_PIN28 __BITS(25,24) 674#define HW_PINCTRL_MUXSEL5_BANK2_PIN27 __BITS(23,22) 675#define HW_PINCTRL_MUXSEL5_BANK2_PIN26 __BITS(21,20) 676#define HW_PINCTRL_MUXSEL5_BANK2_PIN25 __BITS(19,18) 677#define HW_PINCTRL_MUXSEL5_BANK2_PIN24 __BITS(17,16) 678#define HW_PINCTRL_MUXSEL5_BANK2_PIN23 __BITS(15,14) 679#define HW_PINCTRL_MUXSEL5_BANK2_PIN22 __BITS(13,12) 680#define HW_PINCTRL_MUXSEL5_BANK2_PIN21 __BITS(11,10) 681#define HW_PINCTRL_MUXSEL5_BANK2_PIN20 __BITS(9,8) 682#define HW_PINCTRL_MUXSEL5_BANK2_PIN19 __BITS(7,6) 683#define HW_PINCTRL_MUXSEL5_BANK2_PIN18 __BITS(5,4) 684#define HW_PINCTRL_MUXSEL5_BANK2_PIN17 __BITS(3,2) 685#define HW_PINCTRL_MUXSEL5_BANK2_PIN16 __BITS(1,0) 686 687/* Pin 114, EMI_WEN pin function selection */ 688#define HW_PINCTRL_MUXSEL5_BANK2_PIN31_EMI_WEN 0x00 689#define HW_PINCTRL_MUXSEL5_BANK2_PIN31_RESERVED1 0x01 690#define HW_PINCTRL_MUXSEL5_BANK2_PIN31_RESERVED2 0x02 691#define HW_PINCTRL_MUXSEL5_BANK2_PIN31_GPIO 0x03 692 693/* Pin 98, EMI_RASN pin function selection */ 694#define HW_PINCTRL_MUXSEL5_BANK2_PIN30_EMI_RASN 0x00 695#define HW_PINCTRL_MUXSEL5_BANK2_PIN30_RESERVED1 0x01 696#define HW_PINCTRL_MUXSEL5_BANK2_PIN30_RESERVED2 0x02 697#define HW_PINCTRL_MUXSEL5_BANK2_PIN30_GPIO 0x03 698 699/* Pin 115, EMI_CKE pin function selection */ 700#define HW_PINCTRL_MUXSEL5_BANK2_PIN29_EMI_CKE 0x00 701#define HW_PINCTRL_MUXSEL5_BANK2_PIN29_RESERVED1 0x01 702#define HW_PINCTRL_MUXSEL5_BANK2_PIN29_RESERVED2 0x02 703#define HW_PINCTRL_MUXSEL5_BANK2_PIN29_GPIO 0x03 704 705/* Pin 120, GPMI_CE0N pin function selection */ 706#define HW_PINCTRL_MUXSEL5_BANK2_PIN28_GPMI_CE0N 0x00 707#define HW_PINCTRL_MUXSEL5_BANK2_PIN28_RESERVED1 0x01 708#define HW_PINCTRL_MUXSEL5_BANK2_PIN28_RESERVED2 0x02 709#define HW_PINCTRL_MUXSEL5_BANK2_PIN28_GPIO 0x03 710 711/* Pin 118, GPMI_CE1N pin function selection */ 712#define HW_PINCTRL_MUXSEL5_BANK2_PIN27_GPMI_CE1N 0x00 713#define HW_PINCTRL_MUXSEL5_BANK2_PIN27_RESERVED1 0x01 714#define HW_PINCTRL_MUXSEL5_BANK2_PIN27_RESERVED2 0x02 715#define HW_PINCTRL_MUXSEL5_BANK2_PIN27_GPIO 0x03 716 717/* Pin 99, EMI_CE1N pin function selection */ 718#define HW_PINCTRL_MUXSEL5_BANK2_PIN26_EMI_CE1N 0x00 719#define HW_PINCTRL_MUXSEL5_BANK2_PIN26_RESERVED1 0x01 720#define HW_PINCTRL_MUXSEL5_BANK2_PIN26_RESERVED2 0x02 721#define HW_PINCTRL_MUXSEL5_BANK2_PIN26_GPIO 0x03 722 723/* Pin 100, EMI_CE0N pin function selection */ 724#define HW_PINCTRL_MUXSEL5_BANK2_PIN25_EMI_CE0N 0x00 725#define HW_PINCTRL_MUXSEL5_BANK2_PIN25_RESERVED1 0x01 726#define HW_PINCTRL_MUXSEL5_BANK2_PIN25_RESERVED2 0x02 727#define HW_PINCTRL_MUXSEL5_BANK2_PIN25_GPIO 0x03 728 729/* Pin 97, EMI_CASN pin function selection */ 730#define HW_PINCTRL_MUXSEL5_BANK2_PIN24_EMI_CASN 0x00 731#define HW_PINCTRL_MUXSEL5_BANK2_PIN24_RESERVED1 0x01 732#define HW_PINCTRL_MUXSEL5_BANK2_PIN24_RESERVED2 0x02 733#define HW_PINCTRL_MUXSEL5_BANK2_PIN24_GPIO 0x03 734 735/* Pin 117, EMI_BA1 pin function selection */ 736#define HW_PINCTRL_MUXSEL5_BANK2_PIN23_EMI_BA1 0x00 737#define HW_PINCTRL_MUXSEL5_BANK2_PIN23_RESERVED1 0x01 738#define HW_PINCTRL_MUXSEL5_BANK2_PIN23_RESERVED2 0x02 739#define HW_PINCTRL_MUXSEL5_BANK2_PIN23_GPIO 0x03 740 741/* Pin 116, EMI_BA0 pin function selection */ 742#define HW_PINCTRL_MUXSEL5_BANK2_PIN22_EMI_BA0 0x00 743#define HW_PINCTRL_MUXSEL5_BANK2_PIN22_RESERVED1 0x01 744#define HW_PINCTRL_MUXSEL5_BANK2_PIN22_RESERVED2 0x02 745#define HW_PINCTRL_MUXSEL5_BANK2_PIN22_GPIO 0x03 746 747/* Pin 101, EMI_A12 pin function selection */ 748#define HW_PINCTRL_MUXSEL5_BANK2_PIN21_EMI_ADDR12 0x00 749#define HW_PINCTRL_MUXSEL5_BANK2_PIN21_RESERVED1 0x01 750#define HW_PINCTRL_MUXSEL5_BANK2_PIN21_RESERVED2 0x02 751#define HW_PINCTRL_MUXSEL5_BANK2_PIN21_GPIO 0x03 752 753/* Pin 102, EMI_A11 pin function selection */ 754#define HW_PINCTRL_MUXSEL5_BANK2_PIN20_EMI_ADDR11 0x00 755#define HW_PINCTRL_MUXSEL5_BANK2_PIN20_RESERVED1 0x01 756#define HW_PINCTRL_MUXSEL5_BANK2_PIN20_RESERVED2 0x02 757#define HW_PINCTRL_MUXSEL5_BANK2_PIN20_GPIO 0x03 758 759/* Pin 104, EMI_A10 pin function selection */ 760#define HW_PINCTRL_MUXSEL5_BANK2_PIN19_EMI_ADDR10 0x00 761#define HW_PINCTRL_MUXSEL5_BANK2_PIN19_RESERVED1 0x01 762#define HW_PINCTRL_MUXSEL5_BANK2_PIN19_RESERVED2 0x02 763#define HW_PINCTRL_MUXSEL5_BANK2_PIN19_GPIO 0x03 764 765/* Pin 103, EMI_A09 pin function selection */ 766#define HW_PINCTRL_MUXSEL5_BANK2_PIN18_EMI_ADDR09 0x00 767#define HW_PINCTRL_MUXSEL5_BANK2_PIN18_RESERVED1 0x01 768#define HW_PINCTRL_MUXSEL5_BANK2_PIN18_RESERVED2 0x02 769#define HW_PINCTRL_MUXSEL5_BANK2_PIN18_GPIO 0x03 770 771/* Pin 106, EMI_A08 pin function selection */ 772#define HW_PINCTRL_MUXSEL5_BANK2_PIN17_EMI_ADDR08 0x00 773#define HW_PINCTRL_MUXSEL5_BANK2_PIN17_RESERVED1 0x01 774#define HW_PINCTRL_MUXSEL5_BANK2_PIN17_RESERVED2 0x02 775#define HW_PINCTRL_MUXSEL5_BANK2_PIN17_GPIO 0x03 776 777/* Pin 105, EMI_A07 pin function selection */ 778#define HW_PINCTRL_MUXSEL5_BANK2_PIN16_EMI_ADDR07 0x00 779#define HW_PINCTRL_MUXSEL5_BANK2_PIN16_RESERVED1 0x01 780#define HW_PINCTRL_MUXSEL5_BANK2_PIN16_RESERVED2 0x02 781#define HW_PINCTRL_MUXSEL5_BANK2_PIN16_GPIO 0x03 782 783/* 784 * PINCTRL Pin Mux Select Register 6. 785 */ 786#define HW_PINCTRL_MUXSEL6 0x160 787#define HW_PINCTRL_MUXSEL6_SET 0x164 788#define HW_PINCTRL_MUXSEL6_CLR 0x168 789#define HW_PINCTRL_MUXSEL6_TOG 0x16C 790 791#define HW_PINCTRL_MUXSEL6_BANK3_PIN15 __BITS(31,30) 792#define HW_PINCTRL_MUXSEL6_BANK3_PIN14 __BITS(29,28) 793#define HW_PINCTRL_MUXSEL6_BANK3_PIN13 __BITS(27,26) 794#define HW_PINCTRL_MUXSEL6_BANK3_PIN12 __BITS(25,24) 795#define HW_PINCTRL_MUXSEL6_BANK3_PIN11 __BITS(23,22) 796#define HW_PINCTRL_MUXSEL6_BANK3_PIN10 __BITS(21,20) 797#define HW_PINCTRL_MUXSEL6_BANK3_PIN09 __BITS(19,18) 798#define HW_PINCTRL_MUXSEL6_BANK3_PIN08 __BITS(17,16) 799#define HW_PINCTRL_MUXSEL6_BANK3_PIN07 __BITS(15,14) 800#define HW_PINCTRL_MUXSEL6_BANK3_PIN06 __BITS(13,12) 801#define HW_PINCTRL_MUXSEL6_BANK3_PIN05 __BITS(11,10) 802#define HW_PINCTRL_MUXSEL6_BANK3_PIN04 __BITS(9,8) 803#define HW_PINCTRL_MUXSEL6_BANK3_PIN03 __BITS(7,6) 804#define HW_PINCTRL_MUXSEL6_BANK3_PIN02 __BITS(5,4) 805#define HW_PINCTRL_MUXSEL6_BANK3_PIN01 __BITS(3,2) 806#define HW_PINCTRL_MUXSEL6_BANK3_PIN00 __BITS(1,0) 807 808/* Pin 95, EMI_D15 pin function selection */ 809#define HW_PINCTRL_MUXSEL6_BANK3_PIN15_EMI_DATA15 0x00 810#define HW_PINCTRL_MUXSEL6_BANK3_PIN15_RESERVED1 0x01 811#define HW_PINCTRL_MUXSEL6_BANK3_PIN15_RESERVED2 0x02 812#define HW_PINCTRL_MUXSEL6_BANK3_PIN15_DISABLED 0x03 813 814/* Pin 96, EMI_D14 pin function selection */ 815#define HW_PINCTRL_MUXSEL6_BANK3_PIN14_EMI_DATA14 0x00 816#define HW_PINCTRL_MUXSEL6_BANK3_PIN14_RESERVED1 0x01 817#define HW_PINCTRL_MUXSEL6_BANK3_PIN14_RESERVED2 0x02 818#define HW_PINCTRL_MUXSEL6_BANK3_PIN14_DISABLED 0x03 819 820/* Pin 94, EMI_D13 pin function selection */ 821#define HW_PINCTRL_MUXSEL6_BANK3_PIN13_EMI_DATA13 0x00 822#define HW_PINCTRL_MUXSEL6_BANK3_PIN13_RESERVED1 0x01 823#define HW_PINCTRL_MUXSEL6_BANK3_PIN13_RESERVED2 0x02 824#define HW_PINCTRL_MUXSEL6_BANK3_PIN13_DISABLED 0x03 825 826/* Pin 93, EMI_D12 pin function selection */ 827#define HW_PINCTRL_MUXSEL6_BANK3_PIN12_EMI_DATA12 0x00 828#define HW_PINCTRL_MUXSEL6_BANK3_PIN12_RESERVED1 0x01 829#define HW_PINCTRL_MUXSEL6_BANK3_PIN12_RESERVED2 0x02 830#define HW_PINCTRL_MUXSEL6_BANK3_PIN12_DISABLED 0x03 831 832/* Pin 91, EMI_D11 pin function selection */ 833#define HW_PINCTRL_MUXSEL6_BANK3_PIN11_EMI_DATA11 0x00 834#define HW_PINCTRL_MUXSEL6_BANK3_PIN11_RESERVED1 0x01 835#define HW_PINCTRL_MUXSEL6_BANK3_PIN11_RESERVED2 0x02 836#define HW_PINCTRL_MUXSEL6_BANK3_PIN11_DISABLED 0x03 837 838/* Pin 89, EMI_D10 pin function selection */ 839#define HW_PINCTRL_MUXSEL6_BANK3_PIN10_EMI_DATA10 0x00 840#define HW_PINCTRL_MUXSEL6_BANK3_PIN10_RESERVED1 0x01 841#define HW_PINCTRL_MUXSEL6_BANK3_PIN10_RESERVED2 0x02 842#define HW_PINCTRL_MUXSEL6_BANK3_PIN10_DISABLED 0x03 843 844/* Pin 87, EMI_D09 pin function selection */ 845#define HW_PINCTRL_MUXSEL6_BANK3_PIN09_EMI_DATA09 0x00 846#define HW_PINCTRL_MUXSEL6_BANK3_PIN09_RESERVED1 0x01 847#define HW_PINCTRL_MUXSEL6_BANK3_PIN09_RESERVED2 0x02 848#define HW_PINCTRL_MUXSEL6_BANK3_PIN09_DISABLED 0x03 849 850/* Pin 86, EMI_D08 pin function selection */ 851#define HW_PINCTRL_MUXSEL6_BANK3_PIN08_EMI_DATA08 0x00 852#define HW_PINCTRL_MUXSEL6_BANK3_PIN08_RESERVED1 0x01 853#define HW_PINCTRL_MUXSEL6_BANK3_PIN08_RESERVED2 0x02 854#define HW_PINCTRL_MUXSEL6_BANK3_PIN08_DISABLED 0x03 855 856/* Pin 85, EMI_D07 pin function selection */ 857#define HW_PINCTRL_MUXSEL6_BANK3_PIN07_EMI_DATA07 0x00 858#define HW_PINCTRL_MUXSEL6_BANK3_PIN07_RESERVED1 0x01 859#define HW_PINCTRL_MUXSEL6_BANK3_PIN07_RESERVED2 0x02 860#define HW_PINCTRL_MUXSEL6_BANK3_PIN07_DISABLED 0x03 861 862/* Pin 84, EMI_D06 pin function selection */ 863#define HW_PINCTRL_MUXSEL6_BANK3_PIN06_EMI_DATA06 0x00 864#define HW_PINCTRL_MUXSEL6_BANK3_PIN06_RESERVED1 0x01 865#define HW_PINCTRL_MUXSEL6_BANK3_PIN06_RESERVED2 0x02 866#define HW_PINCTRL_MUXSEL6_BANK3_PIN06_DISABLED 0x03 867 868/* Pin 83, EMI_D05 pin function selection */ 869#define HW_PINCTRL_MUXSEL6_BANK3_PIN05_EMI_DATA05 0x00 870#define HW_PINCTRL_MUXSEL6_BANK3_PIN05_RESERVED1 0x01 871#define HW_PINCTRL_MUXSEL6_BANK3_PIN05_RESERVED2 0x02 872#define HW_PINCTRL_MUXSEL6_BANK3_PIN05_DISABLED 0x03 873 874/* Pin 82, EMI_D04 pin function selection */ 875#define HW_PINCTRL_MUXSEL6_BANK3_PIN04_EMI_DATA04 0x00 876#define HW_PINCTRL_MUXSEL6_BANK3_PIN04_RESERVED1 0x01 877#define HW_PINCTRL_MUXSEL6_BANK3_PIN04_RESERVED2 0x02 878#define HW_PINCTRL_MUXSEL6_BANK3_PIN04_DISABLED 0x03 879 880/* Pin 79, EMI_D03 pin function selection */ 881#define HW_PINCTRL_MUXSEL6_BANK3_PIN03_EMI_DATA03 0x00 882#define HW_PINCTRL_MUXSEL6_BANK3_PIN03_RESERVED1 0x01 883#define HW_PINCTRL_MUXSEL6_BANK3_PIN03_RESERVED2 0x02 884#define HW_PINCTRL_MUXSEL6_BANK3_PIN03_DISABLED 0x03 885 886/* Pin 77, EMI_D02 pin function selection */ 887#define HW_PINCTRL_MUXSEL6_BANK3_PIN02_EMI_DATA02 0x00 888#define HW_PINCTRL_MUXSEL6_BANK3_PIN02_RESERVED1 0x01 889#define HW_PINCTRL_MUXSEL6_BANK3_PIN02_RESERVED2 0x02 890#define HW_PINCTRL_MUXSEL6_BANK3_PIN02_DISABLED 0x03 891 892/* Pin 76, EMI_D01 pin function selection */ 893#define HW_PINCTRL_MUXSEL6_BANK3_PIN01_EMI_DATA01 0x00 894#define HW_PINCTRL_MUXSEL6_BANK3_PIN01_RESERVED1 0x01 895#define HW_PINCTRL_MUXSEL6_BANK3_PIN01_RESERVED2 0x02 896#define HW_PINCTRL_MUXSEL6_BANK3_PIN01_DISABLED 0x03 897 898/* Pin 75, EMI_D00 pin function selection */ 899#define HW_PINCTRL_MUXSEL6_BANK3_PIN00_EMI_DATA00 0x00 900#define HW_PINCTRL_MUXSEL6_BANK3_PIN00_RESERVED1 0x01 901#define HW_PINCTRL_MUXSEL6_BANK3_PIN00_RESERVED2 0x02 902#define HW_PINCTRL_MUXSEL6_BANK3_PIN00_DISABLED 0x03 903 904/* 905 * PINCTRL Pin Mux Select Register 7. 906 */ 907#define HW_PINCTRL_MUXSEL7 0x170 908#define HW_PINCTRL_MUXSEL7_SET 0x174 909#define HW_PINCTRL_MUXSEL7_CLR 0x178 910#define HW_PINCTRL_MUXSEL7_TOG 0x17C 911 912#define HW_PINCTRL_MUXSEL7_RSRVD0 __BITS(31,12) 913#define HW_PINCTRL_MUXSEL7_BANK3_PIN21 __BITS(11,10) 914#define HW_PINCTRL_MUXSEL7_BANK3_PIN20 __BITS(9,8) 915#define HW_PINCTRL_MUXSEL7_BANK3_PIN19 __BITS(7,6) 916#define HW_PINCTRL_MUXSEL7_BANK3_PIN18 __BITS(5,4) 917#define HW_PINCTRL_MUXSEL7_BANK3_PIN17 __BITS(3,2) 918#define HW_PINCTRL_MUXSEL7_BANK3_PIN16 __BITS(1,0) 919 920/* Always write zeroes to this field */ 921#define HW_PINCTRL_MUXSEL7_RSRVD0_ZERO 0x00 922 923/* Pin 72, EMI_CLKN pin function selection */ 924#define HW_PINCTRL_MUXSEL7_BANK3_PIN21_EMI_CLKN 0x00 925#define HW_PINCTRL_MUXSEL7_BANK3_PIN21_RESERVED1 0x01 926#define HW_PINCTRL_MUXSEL7_BANK3_PIN21_RESERVED2 0x02 927#define HW_PINCTRL_MUXSEL7_BANK3_PIN21_DISABLED 0x03 928 929/* Pin 70, EMI_CLK pin function selection */ 930#define HW_PINCTRL_MUXSEL7_BANK3_PIN20_EMI_CLK 0x00 931#define HW_PINCTRL_MUXSEL7_BANK3_PIN20_RESERVED1 0x01 932#define HW_PINCTRL_MUXSEL7_BANK3_PIN20_RESERVED2 0x02 933#define HW_PINCTRL_MUXSEL7_BANK3_PIN20_DISABLED 0x03 934 935/* Pin 74, EMI_DQS1 pin function selection */ 936#define HW_PINCTRL_MUXSEL7_BANK3_PIN19_EMI_DQS1 0x00 937#define HW_PINCTRL_MUXSEL7_BANK3_PIN19_RESERVED1 0x01 938#define HW_PINCTRL_MUXSEL7_BANK3_PIN19_RESERVED2 0x02 939#define HW_PINCTRL_MUXSEL7_BANK3_PIN19_DISABLED 0x03 940 941/* Pin 73, EMI_DQS0 pin function selection */ 942#define HW_PINCTRL_MUXSEL7_BANK3_PIN18_EMI_DQS0 0x00 943#define HW_PINCTRL_MUXSEL7_BANK3_PIN18_RESERVED1 0x01 944#define HW_PINCTRL_MUXSEL7_BANK3_PIN18_RESERVED2 0x02 945#define HW_PINCTRL_MUXSEL7_BANK3_PIN18_DISABLED 0x03 946 947/* Pin 92, EMI_DQM1 pin function selection */ 948#define HW_PINCTRL_MUXSEL7_BANK3_PIN17_EMI_DQM1 0x00 949#define HW_PINCTRL_MUXSEL7_BANK3_PIN17_RESERVED1 0x01 950#define HW_PINCTRL_MUXSEL7_BANK3_PIN17_RESERVED2 0x02 951#define HW_PINCTRL_MUXSEL7_BANK3_PIN17_DISABLED 0x03 952 953/* Pin 81, EMI_DQM0 pin function selection */ 954#define HW_PINCTRL_MUXSEL7_BANK3_PIN16_EMI_DQM0 0x00 955#define HW_PINCTRL_MUXSEL7_BANK3_PIN16_RESERVED1 0x01 956#define HW_PINCTRL_MUXSEL7_BANK3_PIN16_RESERVED2 0x02 957#define HW_PINCTRL_MUXSEL7_BANK3_PIN16_DISABLED 0x03 958 959/* 960 * PINCTRL Drive Strength and Voltage Register 0. 961 */ 962#define HW_PINCTRL_DRIVE0 0x200 963#define HW_PINCTRL_DRIVE0_SET 0x204 964#define HW_PINCTRL_DRIVE0_CLR 0x208 965#define HW_PINCTRL_DRIVE0_TOG 0x20C 966 967/* 968 * PINCTRL Drive Strength and Voltage Register 2. 969 */ 970#define HW_PINCTRL_DRIVE2 0x220 971#define HW_PINCTRL_DRIVE2_SET 0x224 972#define HW_PINCTRL_DRIVE2_CLR 0x228 973#define HW_PINCTRL_DRIVE2_TOG 0x22C 974 975#define HW_PINCTRL_DRIVE2_RSRVD7 __BITS(31, 30) 976#define HW_PINCTRL_DRIVE2_BANK0_PIN23_MA __BITS(29, 28) 977#define HW_PINCTRL_DRIVE2_RSRVD6 __BITS(27, 26) 978#define HW_PINCTRL_DRIVE2_BANK0_PIN22_MA __BITS(25, 24) 979#define HW_PINCTRL_DRIVE2_RSRVD5 __BITS(23, 22) 980#define HW_PINCTRL_DRIVE2_BANK0_PIN21_MA __BITS(21, 20) 981#define HW_PINCTRL_DRIVE2_RSRVD4 __BITS(19, 18) 982#define HW_PINCTRL_DRIVE2_BANK0_PIN20_MA __BITS(17, 16) 983#define HW_PINCTRL_DRIVE2_RSRVD3 __BITS(15, 14) 984#define HW_PINCTRL_DRIVE2_BANK0_PIN19_MA __BITS(13, 12) 985#define HW_PINCTRL_DRIVE2_RSRVD2 __BITS(11, 10) 986#define HW_PINCTRL_DRIVE2_BANK0_PIN18_MA __BITS(9, 8) 987#define HW_PINCTRL_DRIVE2_RSRVD1 __BITS(7, 6) 988#define HW_PINCTRL_DRIVE2_BANK0_PIN17_MA __BITS(5, 4) 989#define HW_PINCTRL_DRIVE2_RSRVD0 __BITS(3, 2) 990#define HW_PINCTRL_DRIVE2_BANK0_PIN16_MA __BITS(1, 0) 991 992/* 993 * PINCTRL Drive Strength and Voltage Register 8. 994 */ 995#define HW_PINCTRL_DRIVE8 0x280 996#define HW_PINCTRL_DRIVE8_SET 0x284 997#define HW_PINCTRL_DRIVE8_CLR 0x288 998#define HW_PINCTRL_DRIVE8_TOG 0x28C 999 1000#define HW_PINCTRL_DRIVE8_RSRVD7 __BITS(31, 30) 1001#define HW_PINCTRL_DRIVE8_BANK2_PIN07_MA __BITS(29, 28) 1002#define HW_PINCTRL_DRIVE8_RSRVD6 __BITS(27, 26) 1003#define HW_PINCTRL_DRIVE8_BANK2_PIN06_MA __BITS(25, 24) 1004#define HW_PINCTRL_DRIVE8_RSRVD5 __BITS(23, 22) 1005#define HW_PINCTRL_DRIVE8_BANK2_PIN05_MA __BITS(21, 20) 1006#define HW_PINCTRL_DRIVE8_RSRVD4 __BITS(19, 18) 1007#define HW_PINCTRL_DRIVE8_BANK2_PIN04_MA __BITS(17, 16) 1008#define HW_PINCTRL_DRIVE8_RSRVD3 __BITS(15, 14) 1009#define HW_PINCTRL_DRIVE8_BANK2_PIN03_MA __BITS(13, 12) 1010#define HW_PINCTRL_DRIVE8_RSRVD2 __BITS(11, 10) 1011#define HW_PINCTRL_DRIVE8_BANK2_PIN02_MA __BITS(9, 8) 1012#define HW_PINCTRL_DRIVE8_RSRVD1 __BITS(7, 6) 1013#define HW_PINCTRL_DRIVE8_BANK2_PIN01_MA __BITS(5, 4) 1014#define HW_PINCTRL_DRIVE8_RSRVD0 __BITS(3, 2) 1015#define HW_PINCTRL_DRIVE8_BANK2_PIN00_MA __BITS(1, 0) 1016 1017/* 1018 * PINCTRL Drive Strength and Voltage Register 9. 1019 */ 1020#define HW_PINCTRL_DRIVE9 0x290 1021#define HW_PINCTRL_DRIVE9_SET 0x294 1022#define HW_PINCTRL_DRIVE9_CLR 0x298 1023#define HW_PINCTRL_DRIVE9_TOG 0x29C 1024 1025#define HW_PINCTRL_DRIVE9_RSRVD7 __BIT(31) 1026#define HW_PINCTRL_DRIVE9_BANK2_PIN15_V __BIT(30) 1027#define HW_PINCTRL_DRIVE9_BANK2_PIN15_MA __BITS(29, 28) 1028#define HW_PINCTRL_DRIVE9_RSRVD6 __BIT(27) 1029#define HW_PINCTRL_DRIVE9_BANK2_PIN14_V __BIT(26) 1030#define HW_PINCTRL_DRIVE9_BANK2_PIN14_MA __BITS(25, 24) 1031#define HW_PINCTRL_DRIVE9_RSRVD5 __BIT(23) 1032#define HW_PINCTRL_DRIVE9_BANK2_PIN13_V __BIT(22) 1033#define HW_PINCTRL_DRIVE9_BANK2_PIN13_MA __BITS(21, 20) 1034#define HW_PINCTRL_DRIVE9_RSRVD4 __BIT(19) 1035#define HW_PINCTRL_DRIVE9_BANK2_PIN12_V __BIT(18) 1036#define HW_PINCTRL_DRIVE9_BANK2_PIN12_MA __BITS(17, 16) 1037#define HW_PINCTRL_DRIVE9_RSRVD3 __BIT(15) 1038#define HW_PINCTRL_DRIVE9_BANK2_PIN11_V __BIT(14) 1039#define HW_PINCTRL_DRIVE9_BANK2_PIN11_MA __BITS(13, 12) 1040#define HW_PINCTRL_DRIVE9_RSRVD2 __BIT(11) 1041#define HW_PINCTRL_DRIVE9_BANK2_PIN10_V __BIT(10) 1042#define HW_PINCTRL_DRIVE9_BANK2_PIN10_MA __BITS(9, 8) 1043#define HW_PINCTRL_DRIVE9_RSRVD1 __BIT(7) 1044#define HW_PINCTRL_DRIVE9_BANK2_PIN09_V __BIT(6) 1045#define HW_PINCTRL_DRIVE9_BANK2_PIN09_MA __BITS(5, 4) 1046#define HW_PINCTRL_DRIVE9_RSRVD0 __BITS(3, 2) 1047#define HW_PINCTRL_DRIVE9_BANK2_PIN08_MA __BITS(1, 0) 1048 1049/* 1050 * PINCTRL Drive Strength and Voltage Register 10. 1051 */ 1052#define HW_PINCTRL_DRIVE10 0x2a0 1053#define HW_PINCTRL_DRIVE10_SET 0x2a4 1054#define HW_PINCTRL_DRIVE10_CLR 0x2a8 1055#define HW_PINCTRL_DRIVE10_TOG 0x2ac 1056 1057#define HW_PINCTRL_DRIVE10_RSRVD7 __BIT(31) 1058#define HW_PINCTRL_DRIVE10_BANK2_PIN23_V __BIT(30) 1059#define HW_PINCTRL_DRIVE10_BANK2_PIN23_MA __BITS(29, 28) 1060#define HW_PINCTRL_DRIVE10_RSRVD6 __BIT(27) 1061#define HW_PINCTRL_DRIVE10_BANK2_PIN22_V __BIT(26) 1062#define HW_PINCTRL_DRIVE10_BANK2_PIN22_MA __BITS(25, 24) 1063#define HW_PINCTRL_DRIVE10_RSRVD5 __BIT(23) 1064#define HW_PINCTRL_DRIVE10_BANK2_PIN21_V __BIT(22) 1065#define HW_PINCTRL_DRIVE10_BANK2_PIN21_MA __BITS(21, 20) 1066#define HW_PINCTRL_DRIVE10_RSRVD4 __BIT(19) 1067#define HW_PINCTRL_DRIVE10_BANK2_PIN20_V __BIT(18) 1068#define HW_PINCTRL_DRIVE10_BANK2_PIN20_MA __BITS(17, 16) 1069#define HW_PINCTRL_DRIVE10_RSRVD3 __BIT(15) 1070#define HW_PINCTRL_DRIVE10_BANK2_PIN19_V __BIT(14) 1071#define HW_PINCTRL_DRIVE10_BANK2_PIN19_MA __BITS(13, 12) 1072#define HW_PINCTRL_DRIVE10_RSRVD2 __BIT(11) 1073#define HW_PINCTRL_DRIVE10_BANK2_PIN18_V __BIT(10) 1074#define HW_PINCTRL_DRIVE10_BANK2_PIN18_MA __BITS(9, 8) 1075#define HW_PINCTRL_DRIVE10_RSRVD1 __BIT(7) 1076#define HW_PINCTRL_DRIVE10_BANK2_PIN17_V __BIT(6) 1077#define HW_PINCTRL_DRIVE10_BANK2_PIN17_MA __BITS(5, 4) 1078#define HW_PINCTRL_DRIVE10_RSRVD0 __BIT(3) 1079#define HW_PINCTRL_DRIVE10_BANK2_PIN16_V __BIT(2) 1080#define HW_PINCTRL_DRIVE10_BANK2_PIN16_MA __BITS(1, 0) 1081 1082/* 1083 * PINCTRL Drive Strength and Voltage Register 11. 1084 */ 1085#define HW_PINCTRL_DRIVE11 0x2b0 1086#define HW_PINCTRL_DRIVE11_SET 0x2b4 1087#define HW_PINCTRL_DRIVE11_CLR 0x2b8 1088#define HW_PINCTRL_DRIVE11_TOG 0x2bC 1089 1090#define HW_PINCTRL_DRIVE11_RSRVD7 __BIT(31) 1091#define HW_PINCTRL_DRIVE11_BANK2_PIN31_V __BIT(30) 1092#define HW_PINCTRL_DRIVE11_BANK2_PIN31_MA __BITS(29, 28) 1093#define HW_PINCTRL_DRIVE11_RSRVD6 __BIT(27) 1094#define HW_PINCTRL_DRIVE11_BANK2_PIN30_V __BIT(26) 1095#define HW_PINCTRL_DRIVE11_BANK2_PIN30_MA __BITS(25, 24) 1096#define HW_PINCTRL_DRIVE11_RSRVD5 __BIT(23) 1097#define HW_PINCTRL_DRIVE11_BANK2_PIN29_V __BIT(22) 1098#define HW_PINCTRL_DRIVE11_BANK2_PIN29_MA __BITS(21, 20) 1099#define HW_PINCTRL_DRIVE11_RSRVD4 __BITS(19, 18) 1100#define HW_PINCTRL_DRIVE11_BANK2_PIN28_MA __BIT(17, 16) 1101#define HW_PINCTRL_DRIVE11_RSRVD3 __BITS(15, 14) 1102#define HW_PINCTRL_DRIVE11_BANK2_PIN27_MA __BITS(13, 12) 1103#define HW_PINCTRL_DRIVE11_RSRVD2 __BIT(11) 1104#define HW_PINCTRL_DRIVE11_BANK2_PIN26_V __BIT(10) 1105#define HW_PINCTRL_DRIVE11_BANK2_PIN26_MA __BITS(9, 8) 1106#define HW_PINCTRL_DRIVE11_RSRVD1 __BIT(7) 1107#define HW_PINCTRL_DRIVE11_BANK2_PIN25_V __BIT(6) 1108#define HW_PINCTRL_DRIVE11_BANK2_PIN25_MA __BITS(5, 4) 1109#define HW_PINCTRL_DRIVE11_RSRVD0 __BIT(3) 1110#define HW_PINCTRL_DRIVE11_BANK2_PIN24_V __BIT(2) 1111#define HW_PINCTRL_DRIVE11_BANK2_PIN24_MA __BITS(1, 0) 1112 1113/* 1114 * PINCTRL Drive Strength and Voltage Register 12. 1115 */ 1116#define HW_PINCTRL_DRIVE12 0x2c0 1117#define HW_PINCTRL_DRIVE12_SET 0x2c4 1118#define HW_PINCTRL_DRIVE12_CLR 0x2c8 1119#define HW_PINCTRL_DRIVE12_TOG 0x2cC 1120 1121#define HW_PINCTRL_DRIVE12_RSRVD7 __BIT(31) 1122#define HW_PINCTRL_DRIVE12_BANK3_PIN07_V __BIT(30) 1123#define HW_PINCTRL_DRIVE12_BANK3_PIN07_MA __BITS(29, 28) 1124#define HW_PINCTRL_DRIVE12_RSRVD6 __BIT(27) 1125#define HW_PINCTRL_DRIVE12_BANK3_PIN06_V __BIT(26) 1126#define HW_PINCTRL_DRIVE12_BANK3_PIN06_MA __BITS(25, 24) 1127#define HW_PINCTRL_DRIVE12_RSRVD5 __BIT(23) 1128#define HW_PINCTRL_DRIVE12_BANK3_PIN05_V __BIT(22) 1129#define HW_PINCTRL_DRIVE12_BANK3_PIN05_MA __BITS(21, 20) 1130#define HW_PINCTRL_DRIVE12_RSRVD4 __BIT(19) 1131#define HW_PINCTRL_DRIVE12_BANK3_PIN04_V __BIT(18) 1132#define HW_PINCTRL_DRIVE12_BANK3_PIN04_MA __BITS(17, 15) 1133#define HW_PINCTRL_DRIVE12_RSRVD3 __BIT(15) 1134#define HW_PINCTRL_DRIVE12_BANK3_PIN03_V __BIT(14) 1135#define HW_PINCTRL_DRIVE12_BANK3_PIN03_MA __BITS(13, 12) 1136#define HW_PINCTRL_DRIVE12_RSRVD2 __BIT(11) 1137#define HW_PINCTRL_DRIVE12_BANK3_PIN02_V __BIT(10) 1138#define HW_PINCTRL_DRIVE12_BANK3_PIN02_MA __BITS(9, 8) 1139#define HW_PINCTRL_DRIVE12_RSRVD1 __BIT(7) 1140#define HW_PINCTRL_DRIVE12_BANK3_PIN01_V __BIT(6) 1141#define HW_PINCTRL_DRIVE12_BANK3_PIN01_MA __BITS(5, 4) 1142#define HW_PINCTRL_DRIVE12_RSRVD0 __BIT(3) 1143#define HW_PINCTRL_DRIVE12_BANK3_PIN00_V __BIT(2) 1144#define HW_PINCTRL_DRIVE12_BANK3_PIN00_MA __BITS(1, 0) 1145 1146/* 1147 * PINCTRL Drive Strength and Voltage Register 13. 1148 */ 1149#define HW_PINCTRL_DRIVE13 0x2d0 1150#define HW_PINCTRL_DRIVE13_SET 0x2d4 1151#define HW_PINCTRL_DRIVE13_CLR 0x2d8 1152#define HW_PINCTRL_DRIVE13_TOG 0x2dc 1153 1154#define HW_PINCTRL_DRIVE13_RSRVD7 __BIT(31) 1155#define HW_PINCTRL_DRIVE13_BANK3_PIN15_V __BIT(30) 1156#define HW_PINCTRL_DRIVE13_BANK3_PIN15_MA __BITS(29, 28) 1157#define HW_PINCTRL_DRIVE13_RSRVD6 __BIT(27) 1158#define HW_PINCTRL_DRIVE13_BANK3_PIN14_V __BIT(26) 1159#define HW_PINCTRL_DRIVE13_BANK3_PIN14_MA __BITS(25, 24) 1160#define HW_PINCTRL_DRIVE13_RSRVD5 __BIT(23) 1161#define HW_PINCTRL_DRIVE13_BANK3_PIN13_V __BIT(22) 1162#define HW_PINCTRL_DRIVE13_BANK3_PIN13_MA __BITS(21, 20) 1163#define HW_PINCTRL_DRIVE13_RSRVD4 __BIT(19) 1164#define HW_PINCTRL_DRIVE13_BANK3_PIN12_V __BIT(18) 1165#define HW_PINCTRL_DRIVE13_BANK3_PIN12_MA __BITS(17, 16) 1166#define HW_PINCTRL_DRIVE13_RSRVD3 __BIT(15) 1167#define HW_PINCTRL_DRIVE13_BANK3_PIN11_V __BIT(14) 1168#define HW_PINCTRL_DRIVE13_BANK3_PIN11_MA __BITS(13, 12) 1169#define HW_PINCTRL_DRIVE13_RSRVD2 __BIT(11) 1170#define HW_PINCTRL_DRIVE13_BANK3_PIN10_V __BIT(10) 1171#define HW_PINCTRL_DRIVE13_BANK3_PIN10_MA __BITS(9, 8) 1172#define HW_PINCTRL_DRIVE13_RSRVD1 __BIT(7) 1173#define HW_PINCTRL_DRIVE13_BANK3_PIN09_V __BIT(6) 1174#define HW_PINCTRL_DRIVE13_BANK3_PIN09_MA __BITS(5, 4) 1175#define HW_PINCTRL_DRIVE13_RSRVD0 __BIT(3) 1176#define HW_PINCTRL_DRIVE13_BANK3_PIN08_V __BIT(2) 1177#define HW_PINCTRL_DRIVE13_BANK3_PIN08_MA __BITS(1, 0) 1178 1179/* 1180 * PINCTRL Drive Strength and Voltage Register 14. 1181 */ 1182#define HW_PINCTRL_DRIVE14 0x2e0 1183#define HW_PINCTRL_DRIVE14_SET 0x2e4 1184#define HW_PINCTRL_DRIVE14_CLR 0x2e8 1185#define HW_PINCTRL_DRIVE14_TOG 0x2ec 1186 1187#define HW_PINCTRL_DRIVE14_RSRVD6 __BITS(31, 24) 1188#define HW_PINCTRL_DRIVE14_RSRVD5 __BIT(23) 1189#define HW_PINCTRL_DRIVE14_BANK3_PIN21_V __BIT(22) 1190#define HW_PINCTRL_DRIVE14_BANK3_PIN21_MA __BITS(21, 20) 1191#define HW_PINCTRL_DRIVE14_RSRVD4 __BIT(19) 1192#define HW_PINCTRL_DRIVE14_BANK3_PIN20_V __BIT(18) 1193#define HW_PINCTRL_DRIVE14_BANK3_PIN20_MA __BITS(17, 16) 1194#define HW_PINCTRL_DRIVE14_RSRVD3 __BIT(15) 1195#define HW_PINCTRL_DRIVE14_BANK3_PIN19_V __BIT(14) 1196#define HW_PINCTRL_DRIVE14_BANK3_PIN19_MA __BITS(13, 12) 1197#define HW_PINCTRL_DRIVE14_RSRVD2 __BIT(11) 1198#define HW_PINCTRL_DRIVE14_BANK3_PIN18_V __BIT(10) 1199#define HW_PINCTRL_DRIVE14_BANK3_PIN18_MA __BITS(9, 8) 1200#define HW_PINCTRL_DRIVE14_RSRVD1 __BIT(7) 1201#define HW_PINCTRL_DRIVE14_BANK3_PIN17_V __BIT(6) 1202#define HW_PINCTRL_DRIVE14_BANK3_PIN17_MA __BITS(5, 4) 1203#define HW_PINCTRL_DRIVE14_RSRVD0 __BIT(3) 1204#define HW_PINCTRL_DRIVE14_BANK3_PIN16_V __BIT(2) 1205#define HW_PINCTRL_DRIVE14_BANK3_PIN16_MA __BITS(1, 0) 1206 1207/* 1208 * PINCTRL Bank 0 Pull Up Resistor Enable Register. 1209 */ 1210#define HW_PINCTRL_PULL0 0x400 1211#define HW_PINCTRL_PULL0_SET 0x404 1212#define HW_PINCTRL_PULL0_CLR 0x408 1213#define HW_PINCTRL_PULL0_TOG 0x40C 1214 1215/* 1216 * PINCTRL Bank 2 Pull Up Resistor Enable Register. 1217 */ 1218#define HW_PINCTRL_PULL2 0x420 1219#define HW_PINCTRL_PULL2_SET 0x424 1220#define HW_PINCTRL_PULL2_CLR 0x428 1221#define HW_PINCTRL_PULL2_TOG 0x42C 1222 1223#define HW_PINCTRL_PULL2_RSRVD2 __BITS(31, 29) 1224#define HW_PINCTRL_PULL2_BANK2_PIN28 __BIT(28) 1225#define HW_PINCTRL_PULL2_BANK2_PIN27 __BIT(27) 1226#define HW_PINCTRL_PULL2_RSRVD1 __BITS(26, 9) 1227#define HW_PINCTRL_PULL2_BANK2_PIN08 __BIT(8) 1228#define HW_PINCTRL_PULL2_RSRVD0 __BITS(7, 6) 1229#define HW_PINCTRL_PULL2_BANK2_PIN05 __BIT(5) 1230#define HW_PINCTRL_PULL2_BANK2_PIN04 __BIT(4) 1231#define HW_PINCTRL_PULL2_BANK2_PIN03 __BIT(3) 1232#define HW_PINCTRL_PULL2_BANK2_PIN02 __BIT(2) 1233#define HW_PINCTRL_PULL2_BANK2_PIN01 __BIT(1) 1234#define HW_PINCTRL_PULL2_BANK2_PIN00 __BIT(0) 1235 1236/* 1237 * PINCTRL Bank 3 Pad Keeper Disable Register. 1238 */ 1239#define HW_PINCTRL_PULL3 0x430 1240#define HW_PINCTRL_PULL3_SET 0x434 1241#define HW_PINCTRL_PULL3_CLR 0x438 1242#define HW_PINCTRL_PULL3_TOG 0x43C 1243 1244#define HW_PINCTRL_PULL3_RSRVD0 __BITS(31, 18) 1245#define HW_PINCTRL_PULL3_BANK3_PIN17 __BIT(17) 1246#define HW_PINCTRL_PULL3_BANK3_PIN16 __BIT(16) 1247#define HW_PINCTRL_PULL3_BANK3_PIN15 __BIT(15) 1248#define HW_PINCTRL_PULL3_BANK3_PIN14 __BIT(14) 1249#define HW_PINCTRL_PULL3_BANK3_PIN13 __BIT(13) 1250#define HW_PINCTRL_PULL3_BANK3_PIN12 __BIT(12) 1251#define HW_PINCTRL_PULL3_BANK3_PIN11 __BIT(11) 1252#define HW_PINCTRL_PULL3_BANK3_PIN10 __BIT(10) 1253#define HW_PINCTRL_PULL3_BANK3_PIN09 __BIT(9) 1254#define HW_PINCTRL_PULL3_BANK3_PIN08 __BIT(8) 1255#define HW_PINCTRL_PULL3_BANK3_PIN07 __BIT(7) 1256#define HW_PINCTRL_PULL3_BANK3_PIN06 __BIT(6) 1257#define HW_PINCTRL_PULL3_BANK3_PIN05 __BIT(5) 1258#define HW_PINCTRL_PULL3_BANK3_PIN04 __BIT(4) 1259#define HW_PINCTRL_PULL3_BANK3_PIN03 __BIT(3) 1260#define HW_PINCTRL_PULL3_BANK3_PIN02 __BIT(2) 1261#define HW_PINCTRL_PULL3_BANK3_PIN01 __BIT(1) 1262#define HW_PINCTRL_PULL3_BANK3_PIN00 __BIT(0) 1263 1264/* 1265 * PINCTRL Bank 0 Data Output Register. 1266 */ 1267#define HW_PINCTRL_DOUT0 0x500 1268#define HW_PINCTRL_DOUT0_SET 0x504 1269#define HW_PINCTRL_DOUT0_CLR 0x508 1270#define HW_PINCTRL_DOUT0_TOG 0x50C 1271 1272#define HW_PINCTRL_DOUT0_DOUT __BITS(31, 0) 1273 1274/* 1275 * PINCTRL Bank 1 Data Output Register. 1276 */ 1277#define HW_PINCTRL_DOUT1 0x510 1278#define HW_PINCTRL_DOUT1_SET 0x514 1279#define HW_PINCTRL_DOUT1_CLR 0x518 1280#define HW_PINCTRL_DOUT1_TOG 0x51C 1281 1282#define HW_PINCTRL_DOUT1_DOUT __BITS(31, 0) 1283 1284/* 1285 * PINCTRL Bank 0 Data Input Register. 1286 */ 1287#define HW_PINCTRL_DIN0 0x600 1288#define HW_PINCTRL_DIN0_SET 0x604 1289#define HW_PINCTRL_DIN0_CLR 0x608 1290#define HW_PINCTRL_DIN0_TOG 0x60C 1291 1292/* 1293 * PINCTRL Bank 0 Data Output Enable Register. 1294 */ 1295#define HW_PINCTRL_DOE0 0x700 1296#define HW_PINCTRL_DOE0_SET 0x704 1297#define HW_PINCTRL_DOE0_CLR 0x708 1298#define HW_PINCTRL_DOE0_TOG 0x70C 1299 1300#define HW_PINCTRL_DOE0_DOE __BITS(31, 0) 1301 1302#endif /* !_ARM_IMX_IMX23_PINCTRLREG_H_ */ 1303