1/* $NetBSD: tegra210_carreg.h,v 1.9 2018/12/14 12:29:22 skrll Exp $ */ 2 3/*- 4 * Copyright (c) 2017 Jared McNeill <jmcneill@invisible.ca> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29#ifndef _ARM_TEGRA210_CARREG_H 30#define _ARM_TEGRA210_CARREG_H 31 32#define TEGRA210_REF_FREQ 38400000 33 34#define CAR_RST_SOURCE_REG 0x00 35#define CAR_RST_SOURCE_WDT_EN __BIT(5) 36#define CAR_RST_SOURCE_WDT_SEL __BIT(4) 37#define CAR_RST_SOURCE_WDT_SYS_RST_EN __BIT(2) 38#define CAR_RST_SOURCE_WDT_COP_RST_EN __BIT(1) 39#define CAR_RST_SOURCE_WDT_CPU_RST_EN __BIT(0) 40 41#define CAR_CLK_OUT_ENB_L_REG 0x10 42#define CAR_CLK_OUT_ENB_H_REG 0x14 43#define CAR_CLK_OUT_ENB_U_REG 0x18 44 45#define CAR_PLLE_SS_CNTL_REG 0x68 46#define CAR_PLLE_SS_CNTL_INTEGOFFSET __BITS(31,30) 47#define CAR_PLLE_SS_CNTL_SSCINCINTRV __BITS(29,24) 48#define CAR_PLLE_SS_CNTL_SSCINC __BITS(23,16) 49#define CAR_PLLE_SS_CNTL_SSCINVERT __BIT(15) 50#define CAR_PLLE_SS_CNTL_SSCCENTER __BIT(14) 51#define CAR_PLLE_SS_CNTL_SSCPDMBYP __BIT(13) 52#define CAR_PLLE_SS_CNTL_SSCBYP __BIT(12) 53#define CAR_PLLE_SS_CNTL_INTERP_RESET __BIT(11) 54#define CAR_PLLE_SS_CNTL_BYPASS_SS __BIT(10) 55#define CAR_PLLE_SS_CNTL_SSCMAX __BITS(8,0) 56 57#define CAR_PLLP_BASE_REG 0xa0 58#define CAR_PLLP_BASE_BYPASS __BIT(31) 59#define CAR_PLLP_BASE_ENABLE __BIT(30) 60#define CAR_PLLP_BASE_REF_DIS __BIT(29) 61#define CAR_PLLP_BASE_OVERRIDE __BIT(28) 62#define CAR_PLLP_BASE_LOCK __BIT(27) 63#define CAR_PLLP_BASE_DIVP __BITS(24,20) 64#define CAR_PLLP_BASE_DIVN __BITS(17,10) 65#define CAR_PLLP_BASE_DIVM __BITS(7,0) 66 67#define CAR_PLLP_OUTA_REG 0xa4 68#define CAR_PLLP_OUTA_OUT1_RATIO __BITS(15,8) 69#define CAR_PLLP_OUTA_OUT1_OVRRIDE __BIT(2) 70#define CAR_PLLP_OUTA_OUT1_CLKEN __BIT(1) 71#define CAR_PLLP_OUTA_OUT1_RSTN __BIT(0) 72#define CAR_PLLP_OUTB_REG 0xa8 73#define CAR_PLLP_OUTB_OUT4_RATIO __BITS(31,24) 74#define CAR_PLLP_OUTB_OUT4_OVRRIDE __BIT(18) 75#define CAR_PLLP_OUTB_OUT4_CLKEN __BIT(17) 76#define CAR_PLLP_OUTB_OUT4_RSTN __BIT(16) 77#define CAR_PLLP_OUTB_OUT3_RATIO __BITS(15,8) 78#define CAR_PLLP_OUTB_OUT3_OVRRIDE __BIT(2) 79#define CAR_PLLP_OUTB_OUT3_CLKEN __BIT(1) 80#define CAR_PLLP_OUTB_OUT3_RSTN __BIT(0) 81#define CAR_PLLP_OUTC_REG 0x67c 82#define CAR_PLLP_OUTC_OUT5_RATIO __BITS(31,24) 83#define CAR_PLLP_OUTC_OUT5_OVERRIDE __BIT(18) 84#define CAR_PLLP_OUTC_OUT5_CLKEN __BIT(17) 85#define CAR_PLLP_OUTC_OUT5_RSTN __BIT(16) 86#define CAR_PLLP_MISC_REG 0xac 87 88#define CAR_PLLC_BASE_REG 0x80 89#define CAR_PLLC_BASE_BYPASS __BIT(31) 90#define CAR_PLLC_BASE_ENABLE __BIT(30) 91#define CAR_PLLC_BASE_REF_DIS __BIT(29) 92#define CAR_PLLC_BASE_LOCK_OVERRIDE __BIT(27) 93#define CAR_PLLC_BASE_LOCK __BIT(26) 94#define CAR_PLLC_BASE_DIVP __BITS(24,20) 95#define CAR_PLLC_BASE_DIVN __BITS(17,10) 96#define CAR_PLLC_BASE_DIVM __BITS(7,0) 97 98#define CAR_PLLU_BASE_REG 0xc0 99#define CAR_PLLU_BASE_BYPASS __BIT(31) 100#define CAR_PLLU_BASE_ENABLE __BIT(30) 101#define CAR_PLLU_BASE_REF_DIS __BIT(29) 102#define CAR_PLLU_BASE_LOCK __BIT(27) 103#define CAR_PLLU_BASE_CLKENABLE_48M __BIT(25) 104#define CAR_PLLU_BASE_OVERRIDE __BIT(24) 105#define CAR_PLLU_BASE_CLKENABLE_ICUSB __BIT(23) 106#define CAR_PLLU_BASE_CLKENABLE_HSIC __BIT(22) 107#define CAR_PLLU_BASE_CLKENABLE_USB __BIT(21) 108#define CAR_PLLU_BASE_DIVP __BITS(20,16) 109#define CAR_PLLU_BASE_DIVN __BITS(15,8) 110#define CAR_PLLU_BASE_DIVM __BITS(4,0) 111 112#define CAR_PLLU_OUTA_REG 0xc4 113#define CAR_PLLU_OUTA_OUT2_RATIO __BITS(31,24) 114#define CAR_PLLU_OUTA_OUT2_OVRRIDE __BIT(18) 115#define CAR_PLLU_OUTA_OUT2_CLKEN __BIT(17) 116#define CAR_PLLU_OUTA_OUT2_RSTN __BIT(16) 117#define CAR_PLLU_OUTA_OUT1_RATIO __BITS(15,8) 118#define CAR_PLLU_OUTA_OUT1_OVRRIDE __BIT(2) 119#define CAR_PLLU_OUTA_OUT1_CLKEN __BIT(1) 120#define CAR_PLLU_OUTA_OUT1_RSTN __BIT(0) 121 122#define CAR_PLLU_MISC_REG 0xcc 123#define CAR_PLLU_MISC_IDDQ __BIT(31) 124#define CAR_PLLU_MISC_FREQLOCK __BIT(30) 125#define CAR_PLLU_MISC_EN_LCKDET __BIT(29) 126#define CAR_PLLU_MISC_PTS __BITS(28,27) 127#define CAR_PLLU_MISC_KCP __BITS(26,25) 128#define CAR_PLLU_MISC_KVCO __BIT(24) 129#define CAR_PLLU_MISC_SETUP __BITS(23,0) 130 131#define CAR_PLLD_BASE_REG 0xd0 132#define CAR_PLLD_BASE_BYPASS __BIT(31) 133#define CAR_PLLD_BASE_ENABLE __BIT(30) 134#define CAR_PLLD_BASE_REF_DIS __BIT(29) 135#define CAR_PLLD_BASE_LOCK __BIT(27) 136#define CAR_PLLD_BASE_DSIA_CLK_SRC __BIT(25) 137#define CAR_PLLD_BASE_CSI_CLK_SRC __BIT(23) 138#define CAR_PLLD_BASE_DIVP __BITS(22,20) 139#define CAR_PLLD_BASE_DIVN __BITS(18,11) 140#define CAR_PLLD_BASE_DIVM __BITS(7,0) 141 142#define CAR_PLLD_MISC_REG 0xdc 143 144#define CAR_PLLX_BASE_REG 0xe0 145#define CAR_PLLX_BASE_BYPASS __BIT(31) 146#define CAR_PLLX_BASE_ENABLE __BIT(30) 147#define CAR_PLLX_BASE_REF_DIS __BIT(29) 148#define CAR_PLLX_BASE_LOCK __BIT(27) 149#define CAR_PLLX_BASE_DIVP __BITS(24,20) 150#define CAR_PLLX_BASE_DIVN __BITS(15,8) 151#define CAR_PLLX_BASE_DIVM __BITS(7,0) 152 153#define CAR_PLLX_MISC_REG 0xe4 154#define CAR_PLLX_MISC_FO_G_DISABLE __BIT(28) 155#define CAR_PLLX_MISC_PTS __BITS(23,22) 156#define CAR_PLLX_MISC_LOCK_ENABLE __BIT(18) 157 158#define CAR_PLLE_BASE_REG 0xe8 159#define CAR_PLLE_BASE_ENABLE __BIT(31) 160#define CAR_PLLE_BASE_LOCK_OVERRIDE __BIT(30) 161#define CAR_PLLE_BASE_FDIV4B __BIT(29) 162#define CAR_PLLE_BASE_DIVP_CML __BITS(28,24) 163#define CAR_PLLE_BASE_EXT_SETUP_23_16 __BITS(23,16) 164#define CAR_PLLE_BASE_DIVN __BITS(15,8) 165#define CAR_PLLE_BASE_DIVM __BITS(7,0) 166 167#define CAR_PLLE_MISC_REG 0xec 168#define CAR_PLLE_MISC_SETUP __BITS(31,16) 169#define CAR_PLLE_MISC_ENABLE __BIT(15) 170#define CAR_PLLE_MISC_IDDQ_SWCTL __BIT(14) 171#define CAR_PLLE_MISC_IDDQ_OVERRIDE __BIT(13) 172#define CAR_PLLE_MISC_LOCK __BIT(11) 173#define CAR_PLLE_MISC_LOCK_ENABLE __BIT(9) 174#define CAR_PLLE_MISC_PTS __BIT(8) 175#define CAR_PLLE_MISC_KCP __BITS(7,6) 176#define CAR_PLLE_MISC_VREG_BG_CTRL __BITS(5,4) 177#define CAR_PLLE_MISC_VREG_CTRL __BITS(3,2) 178#define CAR_PLLE_MISC_KVCO __BIT(0) 179 180#define CAR_PLLD2_BASE_REG 0x4b8 181#define CAR_PLLD2_BASE_BYPASS __BIT(31) 182#define CAR_PLLD2_BASE_ENABLE __BIT(30) 183#define CAR_PLLD2_BASE_REF_DIS __BIT(29) 184#define CAR_PLLD2_BASE_FREQLOCK __BIT(28) 185#define CAR_PLLD2_BASE_LOCK __BIT(27) 186#define CAR_PLLD2_BASE_REF_SRC_SEL __BITS(26,25) 187#define CAR_PLLD2_BASE_REF_SRC_SEL_PLL_D 0 188#define CAR_PLLD2_BASE_REF_SRC_SEL_PLL_D2 1 189#define CAR_PLLD2_BASE_LOCK_OVERRIDE __BIT(24) 190#define CAR_PLLD2_BASE_DIVP __BITS(23,19) 191#define CAR_PLLD2_BASE_IDDQ __BIT(18) 192#define CAR_PLLD2_BASE_PTS __BIT(16) 193#define CAR_PLLD2_BASE_DIVN __BITS(15,8) 194#define CAR_PLLD2_BASE_DIVM __BITS(7,0) 195 196#define CAR_PLLD2_MISC_REG 0x4bc 197#define CAR_PLLD2_MISC_LOCK_ENABLE __BIT(30) 198#define CAR_PLLD2_MISC_KCP __BITS(26,25) 199#define CAR_PLLD2_MISC_KVCO __BIT(24) 200#define CAR_PLLD2_MISC_SETUP __BITS(23,0) 201 202#define CAR_CLKSRC_I2C1_REG 0x124 203#define CAR_CLKSRC_I2C2_REG 0x198 204#define CAR_CLKSRC_I2C3_REG 0x1b8 205#define CAR_CLKSRC_I2C4_REG 0x3c4 206#define CAR_CLKSRC_I2C5_REG 0x128 207#define CAR_CLKSRC_I2C6_REG 0x65c 208 209#define CAR_CLKSRC_I2C_SRC __BITS(31,29) 210#define CAR_CLKSRC_I2C_SRC_PLLP_OUT0 0 211#define CAR_CLKSRC_I2C_SRC_PLLC2_OUT0 1 212#define CAR_CLKSRC_I2C_SRC_PLLC_OUT0 2 213#define CAR_CLKSRC_I2C_SRC_PLLC4_OUT0 3 214#define CAR_CLKSRC_I2C_SRC_PLLC4_OUT1 5 215#define CAR_CLKSRC_I2C_SRC_CLK_M 6 216#define CAR_CLKSRC_I2C_SRC_PLLC4_OUT2 7 217#define CAR_CLKSRC_I2C_DIV __BITS(15,0) 218 219#define CAR_CLKSRC_SPI1_REG 0x134 220#define CAR_CLKSRC_SPI2_REG 0x118 221#define CAR_CLKSRC_SPI3_REG 0x11c 222#define CAR_CLKSRC_SPI4_REG 0x1b4 223#define CAR_CLKSRC_SPI5_REG 0x3c8 224#define CAR_CLKSRC_SPI6_REG 0x3cc 225 226#define CAR_CLKSRC_SPI_SRC __BITS(31,29) 227#define CAR_CLKSRC_SPI_SRC_PLLP_OUT0 0 228#define CAR_CLKSRC_SPI_SRC_PLLC2_OUT0 1 229#define CAR_CLKSRC_SPI_SRC_PLLC_OUT0 2 230#define CAR_CLKSRC_SPI_SRC_PLLC4_OUT0 3 231#define CAR_CLKSRC_SPI_SRC_PLLC4_OUT1 5 232#define CAR_CLKSRC_SPI_SRC_CLK_M 6 233#define CAR_CLKSRC_SPI_SRC_PLLC4_OUT2 7 234#define CAR_CLKSRC_SPI_DIV __BITS(7,0) 235 236#define CAR_CLKSRC_UARTA_REG 0x178 237#define CAR_CLKSRC_UARTB_REG 0x17c 238#define CAR_CLKSRC_UARTC_REG 0x1a0 239#define CAR_CLKSRC_UARTD_REG 0x1c0 240 241#define CAR_CLKSRC_UART_SRC __BITS(31,29) 242#define CAR_CLKSRC_UART_SRC_PLLP_OUT0 0 243#define CAR_CLKSRC_UART_SRC_PLLC2_OUT0 1 244#define CAR_CLKSRC_UART_SRC_PLLC_OUT0 2 245#define CAR_CLKSRC_UART_SRC_PLLC4_OUT0 3 246#define CAR_CLKSRC_UART_SRC_PLLC4_OUT1 5 247#define CAR_CLKSRC_UART_SRC_CLK_M 6 248#define CAR_CLKSRC_UART_SRC_PLLC4_OUT2 7 249#define CAR_CLKSRC_UART_DIV_ENB __BIT(24) 250#define CAR_CLKSRC_UART_DIV __BITS(15,0) 251 252#define CAR_CLKSRC_SDMMC1_REG 0x150 253#define CAR_CLKSRC_SDMMC2_REG 0x154 254#define CAR_CLKSRC_SDMMC4_REG 0x164 255#define CAR_CLKSRC_SDMMC3_REG 0x1bc 256 257#define CAR_CLKSRC_SDMMC_SRC __BITS(31,29) 258/* CAR_CLKSRC_SDMMC_SRC_* differs for each instance */ 259#define CAR_CLKSRC_SDMMC_DIV __BITS(7,0) 260 261#define CAR_CLKSRC_DISP1_REG 0x138 262#define CAR_CLKSRC_DISP2_REG 0x13c 263#define CAR_CLKSRC_DISP_SRC __BITS(31,29) 264#define CAR_CLKSRC_DISP_SRC_PLLP_OUT0 0 265#define CAR_CLKSRC_DISP_SRC_PLLD_OUT 1 266#define CAR_CLKSRC_DISP_SRC_PLLD_OUT0 2 /* DISP1 only */ 267#define CAR_CLKSRC_DISP_SRC_PLLD2_OUT0 5 268#define CAR_CLKSRC_DISP_SRC_CLK_M 6 269 270#define CAR_CLKSRC_HOST1X_REG 0x180 271#define CAR_CLKSRC_HOST1X_SRC __BITS(31,29) 272#define CAR_CLKSRC_HOST1X_IDLE_DIVISOR __BITS(15,8) 273#define CAR_CLKSRC_HOST1X_CLK_DIVISOR __BITS(7,0) 274 275#define CAR_RST_DEV_L_SET_REG 0x300 276#define CAR_RST_DEV_L_CLR_REG 0x304 277#define CAR_RST_DEV_H_SET_REG 0x308 278#define CAR_RST_DEV_H_CLR_REG 0x30c 279#define CAR_RST_DEV_U_SET_REG 0x310 280#define CAR_RST_DEV_U_CLR_REG 0x314 281#define CAR_RST_DEV_V_SET_REG 0x430 282#define CAR_RST_DEV_V_CLR_REG 0x434 283#define CAR_RST_DEV_W_SET_REG 0x438 284#define CAR_RST_DEV_W_CLR_REG 0x43c 285#define CAR_RST_DEV_X_SET_REG 0x290 286#define CAR_RST_DEV_X_CLR_REG 0x294 287#define CAR_RST_DEV_Y_SET_REG 0x2a8 288#define CAR_RST_DEV_Y_CLR_REG 0x2ac 289 290#define CAR_CLK_ENB_L_SET_REG 0x320 291#define CAR_CLK_ENB_L_CLR_REG 0x324 292#define CAR_CLK_ENB_H_SET_REG 0x328 293#define CAR_CLK_ENB_H_CLR_REG 0x32c 294#define CAR_CLK_ENB_U_SET_REG 0x330 295#define CAR_CLK_ENB_U_CLR_REG 0x334 296#define CAR_CLK_ENB_V_SET_REG 0x440 297#define CAR_CLK_ENB_V_CLR_REG 0x444 298#define CAR_CLK_ENB_W_SET_REG 0x448 299#define CAR_CLK_ENB_W_CLR_REG 0x44c 300#define CAR_CLK_ENB_X_SET_REG 0x284 301#define CAR_CLK_ENB_X_CLR_REG 0x288 302#define CAR_CLK_ENB_Y_SET_REG 0x29c 303#define CAR_CLK_ENB_Y_CLR_REG 0x2a0 304 305#define CAR_DEV_L_CACHE2 __BIT(31) 306#define CAR_DEV_L_I2S1 __BIT(30) 307#define CAR_DEV_L_HOST1X __BIT(28) 308#define CAR_DEV_L_DISP1 __BIT(27) 309#define CAR_DEV_L_DISP2 __BIT(26) 310#define CAR_DEV_L_ISP __BIT(23) 311#define CAR_DEV_L_USBD __BIT(22) 312#define CAR_DEV_L_VI __BIT(20) 313#define CAR_DEV_L_I2S3 __BIT(18) 314#define CAR_DEV_L_PWM __BIT(17) 315#define CAR_DEV_L_SDMMC4 __BIT(15) 316#define CAR_DEV_L_SDMMC1 __BIT(14) 317#define CAR_DEV_L_I2C1 __BIT(12) 318#define CAR_DEV_L_I2S2 __BIT(11) 319#define CAR_DEV_L_SPDIF __BIT(10) 320#define CAR_DEV_L_SDMMC2 __BIT(9) 321#define CAR_DEV_L_GPIO __BIT(8) 322#define CAR_DEV_L_UARTB __BIT(7) 323#define CAR_DEV_L_UARTA __BIT(6) 324#define CAR_DEV_L_TMR __BIT(5) 325#define CAR_DEV_L_RTC __BIT(4) 326#define CAR_DEV_L_ISPB __BIT(3) 327#define CAR_DEV_L_TRIG_SYS __BIT(2) 328#define CAR_DEV_L_COP __BIT(1) 329#define CAR_DEV_L_CPU __BIT(0) 330 331#define CAR_DEV_U_XUSB_DEV __BIT(31) 332#define CAR_DEV_U_DEV1_OUT __BIT(30) 333#define CAR_DEV_U_DEV2_OUT __BIT(29) 334#define CAR_DEV_U_SUS_OUT __BIT(28) 335#define CAR_DEV_U_MSENC __BIT(27) 336#define CAR_DEV_U_XUSB_HOST __BIT(25) 337#define CAR_DEV_U_CRAM2 __BIT(24) 338#define CAR_DEV_U_IRAMD __BIT(23) 339#define CAR_DEV_U_IRAMC __BIT(22) 340#define CAR_DEV_U_IRAMB __BIT(21) 341#define CAR_DEV_U_IRAMA __BIT(20) 342#define CAR_DEV_U_TSEC __BIT(19) 343#define CAR_DEV_U_DSIB __BIT(18) 344#define CAR_DEV_U_I2C_SLOW __BIT(17) 345#define CAR_DEV_U_DTV __BIT(15) 346#define CAR_DEV_U_SOC_THERM __BIT(14) 347#define CAR_DEV_U_PCIEXCLK __BIT(10) 348#define CAR_DEV_U_CSITE __BIT(9) 349#define CAR_DEV_U_AFI __BIT(8) 350#define CAR_DEV_U_PCIE __BIT(6) 351#define CAR_DEV_U_SDMMC3 __BIT(5) 352#define CAR_DEV_U_SPI4 __BIT(4) 353#define CAR_DEV_U_I2C3 __BIT(3) 354#define CAR_DEV_U_UARTD __BIT(1) 355 356#define CAR_DEV_H_BSEV __BIT(31) 357#define CAR_DEV_H_USB2 __BIT(26) 358#define CAR_DEV_H_EMC __BIT(25) 359#define CAR_DEV_H_MIPI_CAL __BIT(24) 360#define CAR_DEV_H_UARTC __BIT(23) 361#define CAR_DEV_H_I2C2 __BIT(22) 362#define CAR_DEV_H_CSI __BIT(20) 363#define CAR_DEV_H_DSI __BIT(16) 364#define CAR_DEV_H_I2C5 __BIT(15) 365#define CAR_DEV_H_SPI3 __BIT(14) 366#define CAR_DEV_H_SPI2 __BIT(12) 367#define CAR_DEV_H_SPI1 __BIT(9) 368#define CAR_DEV_H_KFUSE __BIT(8) 369#define CAR_DEV_H_FUSE __BIT(7) 370#define CAR_DEV_H_PMC __BIT(6) 371#define CAR_DEV_H_STAT_MON __BIT(5) 372#define CAR_DEV_H_APBDMA __BIT(2) 373#define CAR_DEV_H_AHBDMA __BIT(1) 374#define CAR_DEV_H_MEM __BIT(0) 375 376#define CAR_DEV_V_HDA __BIT(29) 377#define CAR_DEV_V_SATA __BIT(28) 378#define CAR_DEV_V_SATA_OOB __BIT(27) 379#define CAR_DEV_V_EXTPERIPH3 __BIT(26) 380#define CAR_DEV_V_EXTPERIPH2 __BIT(25) 381#define CAR_DEV_V_EXTPERIPH1 __BIT(24) 382#define CAR_DEV_V_ACTMON __BIT(23) 383#define CAR_DEV_V_SPDIF_DOUBLER __BIT(22) 384#define CAR_DEV_V_ATOMICS __BIT(16) 385#define CAR_DEV_V_HDA2CODEC_2X __BIT(15) 386#define CAR_DEV_V_APB2APE __BIT(11) 387#define CAR_DEV_V_AHUB __BIT(10) 388#define CAR_DEV_V_I2C4 __BIT(7) 389#define CAR_DEV_V_I2S5 __BIT(6) 390#define CAR_DEV_V_I2S4 __BIT(5) 391#define CAR_DEV_V_TSENSOR __BIT(4) 392#define CAR_DEV_V_MSELECT __BIT(3) 393#define CAR_DEV_V_CPULP __BIT(1) 394#define CAR_DEV_V_CPUG __BIT(0) 395 396#define CAR_DEV_W_MC1 __BIT(30) 397#define CAR_DEV_W_EMC_DLL __BIT(29) 398#define CAR_DEV_W_XUSB_SS __BIT(28) 399#define CAR_DEV_W_DVFS __BIT(27) 400#define CAR_DEV_W_ENTROPY __BIT(21) 401#define CAR_DEV_W_DSIB_LP __BIT(20) 402#define CAR_DEV_W_DSIA_LP __BIT(19) 403#define CAR_DEV_W_CILEF __BIT(18) 404#define CAR_DEV_W_CILCD __BIT(17) 405#define CAR_DEV_W_CILAB __BIT(16) 406#define CAR_DEV_W_XUSB __BIT(15) 407#define CAR_DEV_W_XUSB_PADCTL __BIT(14) 408#define CAR_DEV_W_MIPI_IOBIST __BIT(13) 409#define CAR_DEV_W_SATA_IOBIST __BIT(12) 410#define CAR_DEV_W_EMC_IOBIST __BIT(10) 411#define CAR_DEV_W_PCIE2_IOBIST __BIT(9) 412#define CAR_DEV_W_CEC __BIT(8) 413#define CAR_DEV_W_PCIERX5 __BIT(7) 414#define CAR_DEV_W_PCIERX4 __BIT(6) 415#define CAR_DEV_W_PCIERX3 __BIT(5) 416#define CAR_DEV_W_PCIERX2 __BIT(4) 417#define CAR_DEV_W_PCIERX1 __BIT(3) 418#define CAR_DEV_W_PCIERX0 __BIT(2) 419#define CAR_DEV_W_SATACOLD __BIT(1) 420#define CAR_DEV_W_HDA2HDMICODEC __BIT(0) 421 422#define CAR_DEV_X_PLLG_REF __BIT(29) 423#define CAR_DEV_X_PLLA_ADSP __BIT(28) 424#define CAR_DEV_X_PLLP_ADSP __BIT(27) 425#define CAR_DEV_X_HPLL_ADSP __BIT(26) 426#define CAR_DEV_X_DBGAPB __BIT(25) 427#define CAR_DEV_X_GPU __BIT(24) 428#define CAR_DEV_X_SOR1 __BIT(23) 429#define CAR_DEV_X_SOR0 __BIT(22) 430#define CAR_DEV_X_DPAUX __BIT(21) 431#define CAR_DEV_X_VIC __BIT(18) 432#define CAR_DEV_X_UART_FST_MIPI_CAL __BIT(17) 433#define CAR_DEV_X_EMC_DLL __BIT(14) 434#define CAR_DEV_X_VIM2_CLK __BIT(11) 435#define CAR_DEV_X_MC_BBC __BIT(10) 436#define CAR_DEV_X_MC_CPU __BIT(9) 437#define CAR_DEV_X_MC_CBPA __BIT(8) 438#define CAR_DEV_X_MC_CAPA __BIT(7) 439#define CAR_DEV_X_I2C6 __BIT(6) 440#define CAR_DEV_X_CAM_MCLK2 __BIT(5) 441#define CAR_DEV_X_CAM_MCLK __BIT(4) 442#define CAR_DEV_X_ETR __BIT(3) 443#define CAR_DEV_X_SPARE __BIT(0) 444 445#define CAR_DEV_Y_PLLP_OUT_CPU __BIT(31) 446#define CAR_DEV_Y_SOR_SAFE __BIT(30) 447#define CAR_DEV_Y_IQC1 __BIT(29) 448#define CAR_DEV_Y_IQC2 __BIT(28) 449#define CAR_DEV_Y_NVENC __BIT(27) 450#define CAR_DEV_Y_ADSPNEON __BIT(26) 451#define CAR_DEV_Y_ADSPSCU __BIT(25) 452#define CAR_DEV_Y_ADSPWDT __BIT(24) 453#define CAR_DEV_Y_ADSPDBG __BIT(23) 454#define CAR_DEV_Y_ADSPPERIPH __BIT(22) 455#define CAR_DEV_Y_ADSPINTF __BIT(21) 456#define CAR_DEV_Y_UARTAPE __BIT(20) 457#define CAR_DEV_Y_QSPI __BIT(19) 458#define CAR_DEV_Y_USB2_TRK __BIT(18) 459#define CAR_DEV_Y_HSIC_TRK __BIT(17) 460#define CAR_DEV_Y_VI_I2C __BIT(16) 461#define CAR_DEV_Y_DPAUX __BIT(15) 462#define CAR_DEV_Y_TSECB __BIT(14) 463#define CAR_DEV_Y_PEX_USB_UPHY __BIT(13) 464#define CAR_DEV_Y_SATA_USB_UPHY __BIT(12) 465#define CAR_DEV_Y_MAUD __BIT(10) 466#define CAR_DEV_Y_MC_CCPA __BIT(9) 467#define CAR_DEV_Y_MC_CDPA __BIT(8) 468#define CAR_DEV_Y_ADSP __BIT(7) 469#define CAR_DEV_Y_APE __BIT(6) 470#define CAR_DEV_Y_DMIC3 __BIT(5) 471#define CAR_DEV_Y_AXIAP __BIT(4) 472#define CAR_DEV_Y_NVJPG __BIT(3) 473#define CAR_DEV_Y_NVDEC __BIT(2) 474#define CAR_DEV_Y_SDMMC_LEGACY_TM __BIT(1) 475#define CAR_DEV_Y_SPARE1 __BIT(0) 476 477#define CAR_CCLKG_BURST_POLICY_REG 0x368 478#define CAR_CCLKG_BURST_POLICY_CPU_STATE __BITS(31,28) 479#define CAR_CCLKG_BURST_POLICY_CPU_STATE_IDLE 1 480#define CAR_CCLKG_BURST_POLICY_CPU_STATE_RUN 2 481#define CAR_CCLKG_BURST_POLICY_CWAKEUP_IDLE_SOURCE __BITS(3,0) 482#define CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_CLKM 0 483#define CAR_CCLKG_BURST_POLICY_CWAKEUP_SOURCE_PLLX_OUT0_LJ 8 484 485#define CAR_CLKSRC_MSELECT_REG 0x3b4 486#define CAR_CLKSRC_MSELECT_SRC __BITS(31,29) 487#define CAR_CLKSRC_MSELECT_DIV __BITS(7,0) 488 489#define CAR_CLKSRC_TSENSOR_REG 0x3b8 490#define CAR_CLKSRC_TSENSOR_SRC __BITS(31,29) 491#define CAR_CLKSRC_TSENSOR_SRC_CLK_M 4 492#define CAR_CLKSRC_TSENSOR_DIV __BITS(7,0) 493 494#define CAR_CLKSRC_HDA2CODEC_2X_REG 0x3e4 495#define CAR_CLKSRC_HDA2CODEC_2X_SRC __BITS(31,29) 496#define CAR_CLKSRC_HDA2CODEC_2X_DIV __BITS(7,0) 497 498#define CAR_CLKSRC_SATA_OOB_REG 0x420 499#define CAR_CLKSRC_SATA_OOB_SRC __BITS(31,29) 500#define CAR_CLKSRC_SATA_OOB_DIV __BITS(7,0) 501 502#define CAR_CLKSRC_SATA_REG 0x424 503#define CAR_CLKSRC_SATA_SRC __BITS(31,29) 504#define CAR_CLKSRC_SATA_AUX_CLK_ENB __BIT(24) 505#define CAR_CLKSRC_SATA_DIV __BITS(7,0) 506 507#define CAR_CLKSRC_HDA_REG 0x428 508#define CAR_CLKSRC_HDA_SRC __BITS(31,29) 509#define CAR_CLKSRC_HDA_DIV __BITS(7,0) 510 511#define CAR_UTMIP_PLL_CFG0_REG 0x480 512 513#define CAR_UTMIP_PLL_CFG1_REG 0x484 514#define CAR_UTMIP_PLL_CFG1_ENABLE_DLY_COUNT __BITS(31,27) 515#define CAR_UTMIP_PLL_CFG1_PLLU_POWERUP __BIT(17) 516#define CAR_UTMIP_PLL_CFG1_PLLU_POWERDOWN __BIT(16) 517#define CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERUP __BIT(15) 518#define CAR_UTMIP_PLL_CFG1_PLL_ENABLE_POWERDOWN __BIT(14) 519#define CAR_UTMIP_PLL_CFG1_XTAL_FREQ_COUNT __BITS(11,0) 520 521#define CAR_UTMIP_PLL_CFG2_REG 0x488 522#define CAR_UTMIP_PLL_CFG2_PHY_XTAL_CLOCKEN __BIT(30) 523#define CAR_UTMIP_PLL_CFG2_PD_SAMP_D_POWERUP __BIT(25) 524#define CAR_UTMIP_PLL_CFG2_PD_SAMP_D_POWERDOWN __BIT(24) 525#define CAR_UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT __BITS(23,18) 526#define CAR_UTMIP_PLL_CFG2_STABLE_COUNT __BITS(17,6) 527#define CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERUP __BIT(5) 528#define CAR_UTMIP_PLL_CFG2_PD_SAMP_C_POWERDOWN __BIT(4) 529#define CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERUP __BIT(3) 530#define CAR_UTMIP_PLL_CFG2_PD_SAMP_B_POWERDOWN __BIT(2) 531#define CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERUP __BIT(1) 532#define CAR_UTMIP_PLL_CFG2_PD_SAMP_A_POWERDOWN __BIT(0) 533 534#define CAR_PLLE_AUX_REG 0x48c 535#define CAR_PLLE_AUX_SS_SEQ_INCLUDE __BIT(31) 536#define CAR_PLLE_AUX_REF_SEL_PLLREFE __BIT(28) 537#define CAR_PLLE_AUX_SEQ_STATE __BITS(27,26) 538#define CAR_PLLE_AUX_SEQ_START_STATE __BIT(25) 539#define CAR_PLLE_AUX_SEQ_ENABLE __BIT(24) 540#define CAR_PLLE_AUX_SS_DLY __BITS(23,16) 541#define CAR_PLLE_AUX_LOCK_DLY __BITS(15,8) 542#define CAR_PLLE_AUX_FAST_PT __BIT(7) 543#define CAR_PLLE_AUX_SS_SWCTL __BIT(6) 544#define CAR_PLLE_AUX_CONFIG_SWCTL __BIT(5) 545#define CAR_PLLE_AUX_ENABLE_SWCTL __BIT(4) 546#define CAR_PLLE_AUX_USE_LOCKDET __BIT(3) 547#define CAR_PLLE_AUX_REF_SRC __BIT(2) 548#define CAR_PLLE_AUX_CML1_OEN __BIT(1) 549#define CAR_PLLE_AUX_CML0_OEN __BIT(0) 550 551#define CAR_SATA_PLL_CFG0_REG 0x490 552#define CAR_SATA_PLL_CFG0_SEQ_STATE __BITS(27,26) 553#define CAR_SATA_PLL_CFG0_SEQ_START_STATE __BIT(25) 554#define CAR_SATA_PLL_CFG0_SEQ_ENABLE __BIT(24) 555#define CAR_SATA_PLL_CFG0_SEQ_PADPLL_SLEEP_IDDQ __BIT(13) 556#define CAR_SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE __BIT(7) 557#define CAR_SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE __BIT(6) 558#define CAR_SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE __BIT(5) 559#define CAR_SATA_PLL_CFG0_SEQ_IN_SWCTL __BIT(4) 560#define CAR_SATA_PLL_CFG0_PADPLL_USE_LOCKDET __BIT(2) 561#define CAR_SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE __BIT(1) 562#define CAR_SATA_PLL_CFG0_PADPLL_RESET_SWCTL __BIT(0) 563 564#define CAR_SATA_PLL_CFG1_REG 0x494 565#define CAR_SATA_PLL_CFG1_LANE_IDDQ2_PADPLL_RESET_DLY __BITS(31,24) 566#define CAR_SATA_PLL_CFG1_PADPLL_IDDQ2LANE_SLUMBER_DLY __BITS(23,16) 567#define CAR_SATA_PLL_CFG1_PADPLL_PU_POST_DLY __BITS(15,8) 568#define CAR_SATA_PLL_CFG1_LANE_IDDQ2_PADPLL_IDDQ_DLY __BITS(7,0) 569 570#define CAR_UTMIP_PLL_CFG3_REG 0x4c0 571#define CAR_UTMIP_PLL_CFG3_REF_SRC_SEL __BIT(26) 572#define CAR_UTMIP_PLL_CFG3_REF_DIS __BIT(25) 573#define CAR_UTMIP_PLL_CFG3_PTS __BIT(24) 574#define CAR_UTMIP_PLL_CFG3_SETUP __BITS(23,0) 575 576#define CAR_PLLREFE_BASE_REG 0x4c4 577#define CAR_PLLREFE_BASE_BYPASS __BIT(31) 578#define CAR_PLLREFE_BASE_ENABLE __BIT(30) 579#define CAR_PLLREFE_BASE_REF_DIS __BIT(29) 580#define CAR_PLLREFE_BASE_KCP __BITS(28,27) 581#define CAR_PLLREFE_BASE_KVCO __BIT(26) 582#define CAR_PLLREFE_BASE_DIVP __BITS(20,16) 583#define CAR_PLLREFE_BASE_DIVN __BITS(15,8) 584#define CAR_PLLREFE_BASE_DIVM __BITS(7,0) 585 586#define CAR_PLLREFE_MISC_REG 0x4c8 587#define CAR_PLLREFE_MISC_LOCK_ENABLE __BIT(30) 588#define CAR_PLLREFE_MISC_LOCK_OVERRIDE __BIT(29) 589#define CAR_PLLREFE_MISC_FREQLOCK __BIT(28) 590#define CAR_PLLREFE_MISC_LOCK __BIT(27) 591#define CAR_PLLREFE_MISC_PTS __BITS(26,25) 592#define CAR_PLLREFE_MISC_IDDQ __BIT(24) 593#define CAR_PLLREFE_MISC_SETUP __BITS(23,0) 594 595#define CAR_XUSBIO_PLL_CFG0_REG 0x51c 596#define CAR_XUSBIO_PLL_CFG0_SEQ_STATE __BITS(27,26) 597#define CAR_XUSBIO_PLL_CFG0_SEQ_START_STATE __BIT(25) 598#define CAR_XUSBIO_PLL_CFG0_SEQ_ENABLE __BIT(24) 599#define CAR_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ __BIT(13) 600#define CAR_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET __BIT(6) 601#define CAR_XUSBIO_PLL_CFG0_SEQ_RESET_INPUT_VALUE __BIT(5) 602#define CAR_XUSBIO_PLL_CFG0_SEQ_IN_SWCTL __BIT(4) 603#define CAR_XUSBIO_PLL_CFG0_CLK_ENABLE_OVERRIDE __BIT(3) 604#define CAR_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL __BIT(2) 605#define CAR_XUSBIO_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE __BIT(1) 606#define CAR_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL __BIT(0) 607 608#define CAR_UTMIPLL_HW_PWRDN_CFG0_REG 0x52c 609#define CAR_UTMIPLL_HW_PWRDN_CFG0_LOCK __BIT(31) 610#define CAR_UTMIPLL_HW_PWRDN_CFG0_SEQ_STATE __BITS(27,26) 611#define CAR_UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE __BIT(25) 612#define CAR_UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE __BIT(24) 613#define CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE __BIT(7) 614#define CAR_UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET __BIT(6) 615#define CAR_UTMIPLL_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE __BIT(5) 616#define CAR_UTMIPLL_HW_PWRDN_CFG0_SEQ_IN_SWCTL __BIT(4) 617#define CAR_UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_OVERRIDE __BIT(3) 618#define CAR_UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL __BIT(2) 619#define CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE __BIT(1) 620#define CAR_UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL __BIT(0) 621 622#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_REG 0x530 623#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_IDDQ_PD_INCLUDE __BIT(28) 624#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_STATE __BITS(27,26) 625#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_START_STATE __BIT(25) 626#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_ENABLE __BIT(24) 627#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_USE_SWITCH_DETECT __BIT(7) 628#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_USE_LOCKDET __BIT(6) 629#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_RESET_INPUT_VALUE __BIT(5) 630#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_SEQ_IN_SWCTL __BIT(4) 631#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_ENABLE_OVERRIDE_VALUE __BIT(3) 632#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL __BIT(2) 633#define CLK_RST_CONTROLLER_PLLU_HW_PWRDN_CFG0_CLK_SWITCH_SWCTL __BIT(0) 634 635#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_REG 0x534 636#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_PLLU_CLK_SWITCH_DLY __BITS(31,24) 637#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_PLLU_LOCK_DLY __BITS(23,14) 638#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_UTMIPLL_IDDQ2_ENABLE_DLY __BITS(13,10) 639#define CLK_RST_CONTROLLER_XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY __BITS(9,0) 640 641#define CAR_CLKSRC_XUSB_HOST_REG 0x600 642#define CAR_CLKSRC_XUSB_HOST_SRC __BITS(31,29) 643#define CAR_CLKSRC_XUSB_HOST_DIV __BITS(7,0) 644 645#define CAR_CLKSRC_XUSB_FALCON_REG 0x604 646#define CAR_CLKSRC_XUSB_FALCON_SRC __BITS(31,29) 647#define CAR_CLKSRC_XUSB_FALCON_DIV __BITS(7,0) 648 649#define CAR_CLKSRC_XUSB_FS_REG 0x608 650#define CAR_CLKSRC_XUSB_FS_SRC __BITS(31,29) 651#define CAR_CLKSRC_XUSB_FS_DIV __BITS(7,0) 652 653#define CAR_CLKSRC_XUSB_SS_REG 0x610 654#define CAR_CLKSRC_XUSB_SS_SRC __BITS(31,29) 655#define CAR_CLKSRC_XUSB_SS_HS_CLK_BYPASS __BIT(25) 656#define CAR_CLKSRC_XUSB_SS_SS_CLK_BYPASS __BIT(24) 657#define CAR_CLKSRC_XUSB_SS_DIV __BITS(7,0) 658 659#define CAR_CLKSRC_SOC_THERM_REG 0x644 660#define CAR_CLKSRC_SOC_THERM_SRC __BITS(31,29) 661#define CAR_CLKSRC_SOC_THERM_SRC_PLLP_OUT0 2 662#define CAR_CLKSRC_SOC_THERM_DDLL_SEL __BITS(11,10) 663#define CAR_CLKSRC_SOC_THERM_DIV __BITS(7,0) 664 665#define CAR_CLKSRC_USB2_HSIC_TRK_REG 0x6cc 666#define CAR_CLKSRC_USB2_HSIC_TRK_DIV __BITS(7,0) 667 668#endif /* _ARM_TEGRA210_CARREG_H */ 669