1/* $NetBSD: tonga_ppsmc.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $ */ 2 3/* 4 * Copyright 2015 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26#ifndef TONGA_PP_SMC_H 27#define TONGA_PP_SMC_H 28 29#pragma pack(push, 1) 30 31#define PPSMC_SWSTATE_FLAG_DC 0x01 32#define PPSMC_SWSTATE_FLAG_UVD 0x02 33#define PPSMC_SWSTATE_FLAG_VCE 0x04 34#define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08 35 36#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00 37#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01 38#define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff 39 40#define PPSMC_SYSTEMFLAG_GPIO_DC 0x01 41#define PPSMC_SYSTEMFLAG_STEPVDDC 0x02 42#define PPSMC_SYSTEMFLAG_GDDR5 0x04 43 44#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08 45 46#define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10 47#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20 48#define PPSMC_SYSTEMFLAG_12CHANNEL 0x40 49 50 51#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07 52#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08 53 54#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00 55#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01 56 57#define PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH 0x10 58#define PPSMC_EXTRAFLAGS_DRIVER_TO_GPIO17 0x20 59#define PPSMC_EXTRAFLAGS_PCC_TO_GPIO17 0x40 60 61/* Defines for DPM 2.0 */ 62#define PPSMC_DPM2FLAGS_TDPCLMP 0x01 63#define PPSMC_DPM2FLAGS_PWRSHFT 0x02 64#define PPSMC_DPM2FLAGS_OCP 0x04 65 66/* Defines for display watermark level */ 67 68#define PPSMC_DISPLAY_WATERMARK_LOW 0 69#define PPSMC_DISPLAY_WATERMARK_HIGH 1 70 71/* In the HW performance level's state flags:*/ 72#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01 73#define PPSMC_STATEFLAG_POWERBOOST 0x02 74#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04 75#define PPSMC_STATEFLAG_POWERSHIFT 0x08 76#define PPSMC_STATEFLAG_SLOW_READ_MARGIN 0x10 77#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20 78#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40 79 80/* Fan control algorithm:*/ 81#define FDO_MODE_HARDWARE 0 82#define FDO_MODE_PIECE_WISE_LINEAR 1 83 84enum FAN_CONTROL { 85 FAN_CONTROL_FUZZY, 86 FAN_CONTROL_TABLE 87}; 88 89/* Return codes for driver to SMC communication.*/ 90 91#define PPSMC_Result_OK ((uint16_t)0x01) 92#define PPSMC_Result_NoMore ((uint16_t)0x02) 93#define PPSMC_Result_NotNow ((uint16_t)0x03) 94 95#define PPSMC_Result_Failed ((uint16_t)0xFF) 96#define PPSMC_Result_UnknownCmd ((uint16_t)0xFE) 97#define PPSMC_Result_UnknownVT ((uint16_t)0xFD) 98 99typedef uint16_t PPSMC_Result; 100 101#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x)) 102 103 104#define PPSMC_MSG_Halt ((uint16_t)0x10) 105#define PPSMC_MSG_Resume ((uint16_t)0x11) 106#define PPSMC_MSG_EnableDPMLevel ((uint16_t)0x12) 107#define PPSMC_MSG_ZeroLevelsDisabled ((uint16_t)0x13) 108#define PPSMC_MSG_OneLevelsDisabled ((uint16_t)0x14) 109#define PPSMC_MSG_TwoLevelsDisabled ((uint16_t)0x15) 110#define PPSMC_MSG_EnableThermalInterrupt ((uint16_t)0x16) 111#define PPSMC_MSG_RunningOnAC ((uint16_t)0x17) 112#define PPSMC_MSG_LevelUp ((uint16_t)0x18) 113#define PPSMC_MSG_LevelDown ((uint16_t)0x19) 114#define PPSMC_MSG_ResetDPMCounters ((uint16_t)0x1a) 115#define PPSMC_MSG_SwitchToSwState ((uint16_t)0x20) 116 117#define PPSMC_MSG_SwitchToSwStateLast ((uint16_t)0x3f) 118#define PPSMC_MSG_SwitchToInitialState ((uint16_t)0x40) 119#define PPSMC_MSG_NoForcedLevel ((uint16_t)0x41) 120#define PPSMC_MSG_ForceHigh ((uint16_t)0x42) 121#define PPSMC_MSG_ForceMediumOrHigh ((uint16_t)0x43) 122 123#define PPSMC_MSG_SwitchToMinimumPower ((uint16_t)0x51) 124#define PPSMC_MSG_ResumeFromMinimumPower ((uint16_t)0x52) 125#define PPSMC_MSG_EnableCac ((uint16_t)0x53) 126#define PPSMC_MSG_DisableCac ((uint16_t)0x54) 127#define PPSMC_DPMStateHistoryStart ((uint16_t)0x55) 128#define PPSMC_DPMStateHistoryStop ((uint16_t)0x56) 129#define PPSMC_CACHistoryStart ((uint16_t)0x57) 130#define PPSMC_CACHistoryStop ((uint16_t)0x58) 131#define PPSMC_TDPClampingActive ((uint16_t)0x59) 132#define PPSMC_TDPClampingInactive ((uint16_t)0x5A) 133#define PPSMC_StartFanControl ((uint16_t)0x5B) 134#define PPSMC_StopFanControl ((uint16_t)0x5C) 135#define PPSMC_NoDisplay ((uint16_t)0x5D) 136#define PPSMC_HasDisplay ((uint16_t)0x5E) 137#define PPSMC_MSG_UVDPowerOFF ((uint16_t)0x60) 138#define PPSMC_MSG_UVDPowerON ((uint16_t)0x61) 139#define PPSMC_MSG_EnableULV ((uint16_t)0x62) 140#define PPSMC_MSG_DisableULV ((uint16_t)0x63) 141#define PPSMC_MSG_EnterULV ((uint16_t)0x64) 142#define PPSMC_MSG_ExitULV ((uint16_t)0x65) 143#define PPSMC_PowerShiftActive ((uint16_t)0x6A) 144#define PPSMC_PowerShiftInactive ((uint16_t)0x6B) 145#define PPSMC_OCPActive ((uint16_t)0x6C) 146#define PPSMC_OCPInactive ((uint16_t)0x6D) 147#define PPSMC_CACLongTermAvgEnable ((uint16_t)0x6E) 148#define PPSMC_CACLongTermAvgDisable ((uint16_t)0x6F) 149#define PPSMC_MSG_InferredStateSweep_Start ((uint16_t)0x70) 150#define PPSMC_MSG_InferredStateSweep_Stop ((uint16_t)0x71) 151#define PPSMC_MSG_SwitchToLowestInfState ((uint16_t)0x72) 152#define PPSMC_MSG_SwitchToNonInfState ((uint16_t)0x73) 153#define PPSMC_MSG_AllStateSweep_Start ((uint16_t)0x74) 154#define PPSMC_MSG_AllStateSweep_Stop ((uint16_t)0x75) 155#define PPSMC_MSG_SwitchNextLowerInfState ((uint16_t)0x76) 156#define PPSMC_MSG_SwitchNextHigherInfState ((uint16_t)0x77) 157#define PPSMC_MSG_MclkRetrainingTest ((uint16_t)0x78) 158#define PPSMC_MSG_ForceTDPClamping ((uint16_t)0x79) 159#define PPSMC_MSG_CollectCAC_PowerCorreln ((uint16_t)0x7A) 160#define PPSMC_MSG_CollectCAC_WeightCalib ((uint16_t)0x7B) 161#define PPSMC_MSG_CollectCAC_SQonly ((uint16_t)0x7C) 162#define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0x7D) 163 164#define PPSMC_MSG_ExtremitiesTest_Start ((uint16_t)0x7E) 165#define PPSMC_MSG_ExtremitiesTest_Stop ((uint16_t)0x7F) 166#define PPSMC_FlushDataCache ((uint16_t)0x80) 167#define PPSMC_FlushInstrCache ((uint16_t)0x81) 168 169#define PPSMC_MSG_SetEnabledLevels ((uint16_t)0x82) 170#define PPSMC_MSG_SetForcedLevels ((uint16_t)0x83) 171 172#define PPSMC_MSG_ResetToDefaults ((uint16_t)0x84) 173 174#define PPSMC_MSG_SetForcedLevelsAndJump ((uint16_t)0x85) 175#define PPSMC_MSG_SetCACHistoryMode ((uint16_t)0x86) 176#define PPSMC_MSG_EnableDTE ((uint16_t)0x87) 177#define PPSMC_MSG_DisableDTE ((uint16_t)0x88) 178 179#define PPSMC_MSG_SmcSpaceSetAddress ((uint16_t)0x89) 180#define PPSMC_MSG_ChangeNearTDPLimit ((uint16_t)0x90) 181#define PPSMC_MSG_ChangeSafePowerLimit ((uint16_t)0x91) 182 183#define PPSMC_MSG_DPMStateSweepStart ((uint16_t)0x92) 184#define PPSMC_MSG_DPMStateSweepStop ((uint16_t)0x93) 185 186#define PPSMC_MSG_OVRDDisableSCLKDS ((uint16_t)0x94) 187#define PPSMC_MSG_CancelDisableOVRDSCLKDS ((uint16_t)0x95) 188#define PPSMC_MSG_ThrottleOVRDSCLKDS ((uint16_t)0x96) 189#define PPSMC_MSG_CancelThrottleOVRDSCLKDS ((uint16_t)0x97) 190#define PPSMC_MSG_GPIO17 ((uint16_t)0x98) 191 192#define PPSMC_MSG_API_SetSvi2Volt_Vddc ((uint16_t)0x99) 193#define PPSMC_MSG_API_SetSvi2Volt_Vddci ((uint16_t)0x9A) 194#define PPSMC_MSG_API_SetSvi2Volt_Mvdd ((uint16_t)0x9B) 195#define PPSMC_MSG_API_GetSvi2Volt_Vddc ((uint16_t)0x9C) 196#define PPSMC_MSG_API_GetSvi2Volt_Vddci ((uint16_t)0x9D) 197#define PPSMC_MSG_API_GetSvi2Volt_Mvdd ((uint16_t)0x9E) 198 199#define PPSMC_MSG_BREAK ((uint16_t)0xF8) 200 201/* Trinity Specific Messages*/ 202#define PPSMC_MSG_Test ((uint16_t) 0x100) 203#define PPSMC_MSG_DPM_Voltage_Pwrmgt ((uint16_t) 0x101) 204#define PPSMC_MSG_DPM_Config ((uint16_t) 0x102) 205#define PPSMC_MSG_PM_Controller_Start ((uint16_t) 0x103) 206#define PPSMC_MSG_DPM_ForceState ((uint16_t) 0x104) 207#define PPSMC_MSG_PG_PowerDownSIMD ((uint16_t) 0x105) 208#define PPSMC_MSG_PG_PowerUpSIMD ((uint16_t) 0x106) 209#define PPSMC_MSG_PM_Controller_Stop ((uint16_t) 0x107) 210#define PPSMC_MSG_PG_SIMD_Config ((uint16_t) 0x108) 211#define PPSMC_MSG_Voltage_Cntl_Enable ((uint16_t) 0x109) 212#define PPSMC_MSG_Thermal_Cntl_Enable ((uint16_t) 0x10a) 213#define PPSMC_MSG_Reset_Service ((uint16_t) 0x10b) 214#define PPSMC_MSG_VCEPowerOFF ((uint16_t) 0x10e) 215#define PPSMC_MSG_VCEPowerON ((uint16_t) 0x10f) 216#define PPSMC_MSG_DPM_Disable_VCE_HS ((uint16_t) 0x110) 217#define PPSMC_MSG_DPM_Enable_VCE_HS ((uint16_t) 0x111) 218#define PPSMC_MSG_DPM_N_LevelsDisabled ((uint16_t) 0x112) 219#define PPSMC_MSG_DCEPowerOFF ((uint16_t) 0x113) 220#define PPSMC_MSG_DCEPowerON ((uint16_t) 0x114) 221#define PPSMC_MSG_PCIE_DDIPowerDown ((uint16_t) 0x117) 222#define PPSMC_MSG_PCIE_DDIPowerUp ((uint16_t) 0x118) 223#define PPSMC_MSG_PCIE_CascadePLLPowerDown ((uint16_t) 0x119) 224#define PPSMC_MSG_PCIE_CascadePLLPowerUp ((uint16_t) 0x11a) 225#define PPSMC_MSG_SYSPLLPowerOff ((uint16_t) 0x11b) 226#define PPSMC_MSG_SYSPLLPowerOn ((uint16_t) 0x11c) 227#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint16_t) 0x11d) 228#define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint16_t) 0x11e) 229#define PPSMC_MSG_DISPLAYPHYStatusNotify ((uint16_t) 0x11f) 230#define PPSMC_MSG_EnableBAPM ((uint16_t) 0x120) 231#define PPSMC_MSG_DisableBAPM ((uint16_t) 0x121) 232#define PPSMC_MSG_PCIE_PHYPowerDown ((uint16_t) 0x122) 233#define PPSMC_MSG_PCIE_PHYPowerUp ((uint16_t) 0x123) 234#define PPSMC_MSG_UVD_DPM_Config ((uint16_t) 0x124) 235#define PPSMC_MSG_Spmi_Enable ((uint16_t) 0x122) 236#define PPSMC_MSG_Spmi_Timer ((uint16_t) 0x123) 237#define PPSMC_MSG_LCLK_DPM_Config ((uint16_t) 0x124) 238#define PPSMC_MSG_NBDPM_Config ((uint16_t) 0x125) 239#define PPSMC_MSG_PCIE_DDIPhyPowerDown ((uint16_t) 0x126) 240#define PPSMC_MSG_PCIE_DDIPhyPowerUp ((uint16_t) 0x127) 241#define PPSMC_MSG_MCLKDPM_Config ((uint16_t) 0x128) 242 243#define PPSMC_MSG_UVDDPM_Config ((uint16_t) 0x129) 244#define PPSMC_MSG_VCEDPM_Config ((uint16_t) 0x12A) 245#define PPSMC_MSG_ACPDPM_Config ((uint16_t) 0x12B) 246#define PPSMC_MSG_SAMUDPM_Config ((uint16_t) 0x12C) 247#define PPSMC_MSG_UVDDPM_SetEnabledMask ((uint16_t) 0x12D) 248#define PPSMC_MSG_VCEDPM_SetEnabledMask ((uint16_t) 0x12E) 249#define PPSMC_MSG_ACPDPM_SetEnabledMask ((uint16_t) 0x12F) 250#define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130) 251#define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131) 252#define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132) 253#define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133) 254#define PPSMC_MSG_SetTDPLimit ((uint16_t) 0x134) 255#define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135) 256#define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136) 257#define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0x137) 258#define PPSMC_MSG_ACPPowerON ((uint16_t) 0x138) 259#define PPSMC_MSG_SAMPowerOFF ((uint16_t) 0x139) 260#define PPSMC_MSG_SAMPowerON ((uint16_t) 0x13a) 261#define PPSMC_MSG_SDMAPowerOFF ((uint16_t) 0x13b) 262#define PPSMC_MSG_SDMAPowerON ((uint16_t) 0x13c) 263#define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d) 264#define PPSMC_MSG_IOMMUPowerOFF ((uint16_t) 0x13e) 265#define PPSMC_MSG_IOMMUPowerON ((uint16_t) 0x13f) 266#define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0x140) 267#define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141) 268#define PPSMC_MSG_NBDPM_ForceNominal ((uint16_t) 0x142) 269#define PPSMC_MSG_NBDPM_ForcePerformance ((uint16_t) 0x143) 270#define PPSMC_MSG_NBDPM_UnForce ((uint16_t) 0x144) 271#define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145) 272#define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146) 273#define PPSMC_MSG_PCIeDPM_ForceLevel ((uint16_t) 0x147) 274#define PPSMC_MSG_PCIeDPM_UnForceLevel ((uint16_t) 0x148) 275#define PPSMC_MSG_EnableACDCGPIOInterrupt ((uint16_t) 0x149) 276#define PPSMC_MSG_EnableVRHotGPIOInterrupt ((uint16_t) 0x14a) 277#define PPSMC_MSG_SwitchToAC ((uint16_t) 0x14b) 278 279#define PPSMC_MSG_XDMAPowerOFF ((uint16_t) 0x14c) 280#define PPSMC_MSG_XDMAPowerON ((uint16_t) 0x14d) 281 282#define PPSMC_MSG_DPM_Enable ((uint16_t)0x14e) 283#define PPSMC_MSG_DPM_Disable ((uint16_t)0x14f) 284#define PPSMC_MSG_MCLKDPM_Enable ((uint16_t)0x150) 285#define PPSMC_MSG_MCLKDPM_Disable ((uint16_t)0x151) 286#define PPSMC_MSG_LCLKDPM_Enable ((uint16_t)0x152) 287#define PPSMC_MSG_LCLKDPM_Disable ((uint16_t)0x153) 288#define PPSMC_MSG_UVDDPM_Enable ((uint16_t)0x154) 289#define PPSMC_MSG_UVDDPM_Disable ((uint16_t)0x155) 290#define PPSMC_MSG_SAMUDPM_Enable ((uint16_t)0x156) 291#define PPSMC_MSG_SAMUDPM_Disable ((uint16_t)0x157) 292#define PPSMC_MSG_ACPDPM_Enable ((uint16_t)0x158) 293#define PPSMC_MSG_ACPDPM_Disable ((uint16_t)0x159) 294#define PPSMC_MSG_VCEDPM_Enable ((uint16_t)0x15a) 295#define PPSMC_MSG_VCEDPM_Disable ((uint16_t)0x15b) 296#define PPSMC_MSG_LCLKDPM_SetEnabledMask ((uint16_t)0x15c) 297 298#define PPSMC_MSG_DPM_FPS_Mode ((uint16_t) 0x15d) 299#define PPSMC_MSG_DPM_Activity_Mode ((uint16_t) 0x15e) 300#define PPSMC_MSG_VddC_Request ((uint16_t) 0x15f) 301#define PPSMC_MSG_MCLKDPM_GetEnabledMask ((uint16_t) 0x160) 302#define PPSMC_MSG_LCLKDPM_GetEnabledMask ((uint16_t) 0x161) 303#define PPSMC_MSG_SCLKDPM_GetEnabledMask ((uint16_t) 0x162) 304#define PPSMC_MSG_UVDDPM_GetEnabledMask ((uint16_t) 0x163) 305#define PPSMC_MSG_SAMUDPM_GetEnabledMask ((uint16_t) 0x164) 306#define PPSMC_MSG_ACPDPM_GetEnabledMask ((uint16_t) 0x165) 307#define PPSMC_MSG_VCEDPM_GetEnabledMask ((uint16_t) 0x166) 308#define PPSMC_MSG_PCIeDPM_SetEnabledMask ((uint16_t) 0x167) 309#define PPSMC_MSG_PCIeDPM_GetEnabledMask ((uint16_t) 0x168) 310#define PPSMC_MSG_TDCLimitEnable ((uint16_t) 0x169) 311#define PPSMC_MSG_TDCLimitDisable ((uint16_t) 0x16a) 312#define PPSMC_MSG_DPM_AutoRotate_Mode ((uint16_t) 0x16b) 313#define PPSMC_MSG_DISPCLK_FROM_FCH ((uint16_t)0x16c) 314#define PPSMC_MSG_DISPCLK_FROM_DFS ((uint16_t)0x16d) 315#define PPSMC_MSG_DPREFCLK_FROM_FCH ((uint16_t)0x16e) 316#define PPSMC_MSG_DPREFCLK_FROM_DFS ((uint16_t)0x16f) 317#define PPSMC_MSG_PmStatusLogStart ((uint16_t)0x170) 318#define PPSMC_MSG_PmStatusLogSample ((uint16_t)0x171) 319#define PPSMC_MSG_SCLK_AutoDPM_ON ((uint16_t) 0x172) 320#define PPSMC_MSG_MCLK_AutoDPM_ON ((uint16_t) 0x173) 321#define PPSMC_MSG_LCLK_AutoDPM_ON ((uint16_t) 0x174) 322#define PPSMC_MSG_UVD_AutoDPM_ON ((uint16_t) 0x175) 323#define PPSMC_MSG_SAMU_AutoDPM_ON ((uint16_t) 0x176) 324#define PPSMC_MSG_ACP_AutoDPM_ON ((uint16_t) 0x177) 325#define PPSMC_MSG_VCE_AutoDPM_ON ((uint16_t) 0x178) 326#define PPSMC_MSG_PCIe_AutoDPM_ON ((uint16_t) 0x179) 327#define PPSMC_MSG_MASTER_AutoDPM_ON ((uint16_t) 0x17a) 328#define PPSMC_MSG_MASTER_AutoDPM_OFF ((uint16_t) 0x17b) 329#define PPSMC_MSG_DYNAMICDISPPHYPOWER ((uint16_t) 0x17c) 330#define PPSMC_MSG_CAC_COLLECTION_ON ((uint16_t) 0x17d) 331#define PPSMC_MSG_CAC_COLLECTION_OFF ((uint16_t) 0x17e) 332#define PPSMC_MSG_CAC_CORRELATION_ON ((uint16_t) 0x17f) 333#define PPSMC_MSG_CAC_CORRELATION_OFF ((uint16_t) 0x180) 334#define PPSMC_MSG_PM_STATUS_TO_DRAM_ON ((uint16_t) 0x181) 335#define PPSMC_MSG_PM_STATUS_TO_DRAM_OFF ((uint16_t) 0x182) 336#define PPSMC_MSG_UVD_HANDSHAKE_OFF ((uint16_t) 0x183) 337#define PPSMC_MSG_ALLOW_LOWSCLK_INTERRUPT ((uint16_t) 0x184) 338#define PPSMC_MSG_PkgPwrLimitEnable ((uint16_t) 0x185) 339#define PPSMC_MSG_PkgPwrLimitDisable ((uint16_t) 0x186) 340#define PPSMC_MSG_PkgPwrSetLimit ((uint16_t) 0x187) 341#define PPSMC_MSG_OverDriveSetTargetTdp ((uint16_t) 0x188) 342#define PPSMC_MSG_SCLKDPM_FreezeLevel ((uint16_t) 0x189) 343#define PPSMC_MSG_SCLKDPM_UnfreezeLevel ((uint16_t) 0x18A) 344#define PPSMC_MSG_MCLKDPM_FreezeLevel ((uint16_t) 0x18B) 345#define PPSMC_MSG_MCLKDPM_UnfreezeLevel ((uint16_t) 0x18C) 346#define PPSMC_MSG_START_DRAM_LOGGING ((uint16_t) 0x18D) 347#define PPSMC_MSG_STOP_DRAM_LOGGING ((uint16_t) 0x18E) 348#define PPSMC_MSG_MASTER_DeepSleep_ON ((uint16_t) 0x18F) 349#define PPSMC_MSG_MASTER_DeepSleep_OFF ((uint16_t) 0x190) 350#define PPSMC_MSG_Remove_DC_Clamp ((uint16_t) 0x191) 351#define PPSMC_MSG_DisableACDCGPIOInterrupt ((uint16_t) 0x192) 352#define PPSMC_MSG_OverrideVoltageControl_SetVddc ((uint16_t) 0x193) 353#define PPSMC_MSG_OverrideVoltageControl_SetVddci ((uint16_t) 0x194) 354#define PPSMC_MSG_SetVidOffset_1 ((uint16_t) 0x195) 355#define PPSMC_MSG_SetVidOffset_2 ((uint16_t) 0x207) 356#define PPSMC_MSG_GetVidOffset_1 ((uint16_t) 0x196) 357#define PPSMC_MSG_GetVidOffset_2 ((uint16_t) 0x208) 358#define PPSMC_MSG_THERMAL_OVERDRIVE_Enable ((uint16_t) 0x197) 359#define PPSMC_MSG_THERMAL_OVERDRIVE_Disable ((uint16_t) 0x198) 360#define PPSMC_MSG_SetTjMax ((uint16_t) 0x199) 361#define PPSMC_MSG_SetFanPwmMax ((uint16_t) 0x19A) 362 363#define PPSMC_MSG_WaitForMclkSwitchFinish ((uint16_t) 0x19B) 364#define PPSMC_MSG_ENABLE_THERMAL_DPM ((uint16_t) 0x19C) 365#define PPSMC_MSG_DISABLE_THERMAL_DPM ((uint16_t) 0x19D) 366#define PPSMC_MSG_Enable_PCC ((uint16_t) 0x19E) 367#define PPSMC_MSG_Disable_PCC ((uint16_t) 0x19F) 368 369#define PPSMC_MSG_API_GetSclkFrequency ((uint16_t) 0x200) 370#define PPSMC_MSG_API_GetMclkFrequency ((uint16_t) 0x201) 371#define PPSMC_MSG_API_GetSclkBusy ((uint16_t) 0x202) 372#define PPSMC_MSG_API_GetMclkBusy ((uint16_t) 0x203) 373#define PPSMC_MSG_API_GetAsicPower ((uint16_t) 0x204) 374#define PPSMC_MSG_SetFanRpmMax ((uint16_t) 0x205) 375#define PPSMC_MSG_SetFanSclkTarget ((uint16_t) 0x206) 376#define PPSMC_MSG_SetFanMinPwm ((uint16_t) 0x209) 377#define PPSMC_MSG_SetFanTemperatureTarget ((uint16_t) 0x20A) 378 379#define PPSMC_MSG_BACO_StartMonitor ((uint16_t) 0x240) 380#define PPSMC_MSG_BACO_Cancel ((uint16_t) 0x241) 381#define PPSMC_MSG_EnableVddGfx ((uint16_t) 0x242) 382#define PPSMC_MSG_DisableVddGfx ((uint16_t) 0x243) 383#define PPSMC_MSG_UcodeAddressLow ((uint16_t) 0x244) 384#define PPSMC_MSG_UcodeAddressHigh ((uint16_t) 0x245) 385#define PPSMC_MSG_UcodeLoadStatus ((uint16_t) 0x246) 386 387#define PPSMC_MSG_DRV_DRAM_ADDR_HI ((uint16_t) 0x250) 388#define PPSMC_MSG_DRV_DRAM_ADDR_LO ((uint16_t) 0x251) 389#define PPSMC_MSG_SMU_DRAM_ADDR_HI ((uint16_t) 0x252) 390#define PPSMC_MSG_SMU_DRAM_ADDR_LO ((uint16_t) 0x253) 391#define PPSMC_MSG_LoadUcodes ((uint16_t) 0x254) 392#define PPSMC_MSG_PowerStateNotify ((uint16_t) 0x255) 393#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_HI ((uint16_t) 0x256) 394#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_LO ((uint16_t) 0x257) 395#define PPSMC_MSG_VBIOS_DRAM_ADDR_HI ((uint16_t) 0x258) 396#define PPSMC_MSG_VBIOS_DRAM_ADDR_LO ((uint16_t) 0x259) 397#define PPSMC_MSG_LoadVBios ((uint16_t) 0x25A) 398#define PPSMC_MSG_GetUcodeVersion ((uint16_t) 0x25B) 399#define DMCUSMC_MSG_PSREntry ((uint16_t) 0x25C) 400#define DMCUSMC_MSG_PSRExit ((uint16_t) 0x25D) 401#define PPSMC_MSG_EnableClockGatingFeature ((uint16_t) 0x260) 402#define PPSMC_MSG_DisableClockGatingFeature ((uint16_t) 0x261) 403#define PPSMC_MSG_IsDeviceRunning ((uint16_t) 0x262) 404#define PPSMC_MSG_LoadMetaData ((uint16_t) 0x263) 405#define PPSMC_MSG_TMON_AutoCaliberate_Enable ((uint16_t) 0x264) 406#define PPSMC_MSG_TMON_AutoCaliberate_Disable ((uint16_t) 0x265) 407#define PPSMC_MSG_GetTelemetry1Slope ((uint16_t) 0x266) 408#define PPSMC_MSG_GetTelemetry1Offset ((uint16_t) 0x267) 409#define PPSMC_MSG_GetTelemetry2Slope ((uint16_t) 0x268) 410#define PPSMC_MSG_GetTelemetry2Offset ((uint16_t) 0x269) 411 412typedef uint16_t PPSMC_Msg; 413 414/* If the SMC firmware has an event status soft register this is what the individual bits mean.*/ 415#define PPSMC_EVENT_STATUS_THERMAL 0x00000001 416#define PPSMC_EVENT_STATUS_REGULATORHOT 0x00000002 417#define PPSMC_EVENT_STATUS_DC 0x00000004 418#define PPSMC_EVENT_STATUS_GPIO17 0x00000008 419 420 421#pragma pack(pop) 422#endif 423