Searched refs:xa (Results 251 - 275 of 969) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_4_sh_mask.h998 #define AZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
1099 #define AZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
1542 #define AZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
1643 #define AZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
2086 #define AZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
2187 #define AZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
2630 #define AZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
2731 #define AZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
3174 #define AZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
3275 #define AZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES__POWER_CONTROL__SHIFT 0xa
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H A Ddcn_3_1_6_sh_mask.h86 #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT 0xa
123 #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS__SHIFT 0xa
163 #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION__SHIFT 0xa
1345 #define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE__SHIFT 0xa
1411 #define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE__SHIFT 0xa
1730 #define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN__SHIFT 0xa
1864 #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT 0xa
1991 #define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE__SHIFT 0xa
2084 #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
2128 #define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
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H A Ddcn_3_1_2_sh_mask.h82 #define AZCONTROLLER0_INTERRUPT_CONTROL__STREAM_10_INTERRUPT_ENABLE__SHIFT 0xa
119 #define AZCONTROLLER0_INTERRUPT_STATUS__STREAM_10_INTERRUPT_STATUS__SHIFT 0xa
159 #define AZCONTROLLER0_STREAM_SYNCHRONIZATION__STREAM_10_SYNCHRONIZATION__SHIFT 0xa
808 #define DCCG_GATE_DISABLE_CNTL__DPPCLK_R_DCCG_GATE_DISABLE__SHIFT 0xa
874 #define DCCG_GATE_DISABLE_CNTL2__HDMICHARCLK2_GATE_DISABLE__SHIFT 0xa
1180 #define DSCCLK_DTO_CTRL__DSCCLK2_DTO_DB_EN__SHIFT 0xa
1314 #define DCCG_VSYNC_CNT_INT_CTRL__DCCG_VSYNC_CNT_OTG2_LATCH_MASK__SHIFT 0xa
1423 #define DCCG_GATE_DISABLE_CNTL3__SYMCLK32_ROOT_SE1_GATE_DISABLE__SHIFT 0xa
1519 #define DC_PERFMON0_PERFCOUNTER_STATE__PERFCOUNTER_STATE_SEL2__SHIFT 0xa
1563 #define DC_PERFMON0_PERFMON_CNTL2__PERFMON_RUN_ENABLE_STOP_SEL__SHIFT 0xa
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/linux-master/drivers/staging/sm750fb/
H A Dsm750_accel.h66 #define DE_CONTROL_COMMAND_HOST_WRITE_BOTTOM_UP (0xa << 16)
94 #define DE_CONTROL_SHORT_STROKE_DIR_0 (0xa << 24)
/linux-master/drivers/rtc/
H A Drtc-rp5c01.c30 RP5C01_10_MONTH = 0xa, /* MODE 00 */
34 RP5C01_12_24_SELECT = 0xa, /* MODE 01 */
/linux-master/tools/testing/selftests/powerpc/tm/
H A Dtm-unavailable.c76 * When failure handling occurs, CR0 is set to 0b1010 (0xa). Otherwise
80 return ((condition_reg >> 28) & 0xa) == 0xa;
258 /* 0x4 is a success and 0xa is a fail. See comment in is_failure(). */
/linux-master/drivers/staging/vt6656/
H A Ddevice.h151 #define MESSAGE_TYPE_WRITE_MISCFF 0xa
170 #define MESSAGE_REQUEST_RF_INIT2 0xa
/linux-master/drivers/net/wireless/ath/carl9170/
H A Dwlan.h155 #define AR9170_TXRX_PHY_RATE_OFDM_12M 0xa
172 #define AR9170_TXRX_PHY_RATE_HT_MCS10 0xa
/linux-master/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_5_sh_mask.h123 #define MMSCH_CNTL__MMSCH_DB_BUSY_INTR_EN__SHIFT 0xa
263 #define MMSCH_GPUIOV_CNTXT__CNTXT_OFFSET__SHIFT 0xa
455 #define UVD_JPEG_INT_EN__RST_ERR_EN__SHIFT 0xa
482 #define UVD_JPEG_INT_STAT__RST_ERR_INT__SHIFT 0xa
744 #define UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa
862 #define UVD_JRBC_ENC_STATUS__RB_TRAP_STATUS__SHIFT 0xa
1041 #define UVD_JMI_ENC_JPEG_VMID__SCALAR_RD_VMID__SHIFT 0xa
1200 #define UVD_JMI_DEC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa
1219 #define UVD_JMI_ENC_SWAP_CNTL__IB_MEM_RD_MC_SWAP__SHIFT 0xa
1358 #define JPEG_CGC_CTRL__DYN_OCLK_RAMP_EN__SHIFT 0xa
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H A Dvcn_1_0_sh_mask.h32 #define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 0xa
55 #define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 0xa
78 #define UVD_POWER_STATUS__JRBC_SNOOP_DIS__SHIFT 0xa
439 #define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
490 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa
758 #define UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa
815 #define UVD_CGC_GATE__LBSI__SHIFT 0xa
856 #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa
1074 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa
1200 #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa
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/linux-master/drivers/gpu/drm/nouveau/dispnv04/
H A Dtvmodesnv17.c57 0xd3, 0x4, 0xd4, 0x1, 0x2, 0x0, 0xa, 0x5,
69 0xc5, 0x4, 0xc5, 0x1, 0x2, 0x0, 0xa, 0x5,
81 0xc5, 0x4, 0xc5, 0x1, 0x2, 0x0, 0xa, 0x5,
93 0xd3, 0x4, 0xd4, 0x1, 0x2, 0x0, 0xa, 0x5,
105 0xc5, 0x4, 0xc5, 0x1, 0x2, 0x0, 0xa, 0x5,
117 0xcf, 0x4, 0xcf, 0x1, 0x2, 0x0, 0xa, 0x5,
129 0xcf, 0x4, 0xcf, 0x1, 0x2, 0x0, 0xa, 0x5,
141 0xd3, 0x4, 0xd4, 0x1, 0x2, 0x0, 0xa, 0x5,
/linux-master/drivers/gpu/drm/renesas/shmobile/
H A Dshmob_drm_regs.h45 #define LDMT1R_MIFTYP_RGB18 (0xa << 0)
57 #define LDMT1R_MIFTYP_SYS18 (0xa << 0)
/linux-master/drivers/input/touchscreen/
H A Degalax_ts.c148 static const u8 cmd[MAX_I2C_DATA_LEN] = { 0x03, 0x03, 0xa, 0x01, 0x41 };
229 0x3, 0x6, 0xa, 0x3, 0x36, 0x3f, 0x2, 0, 0, 0
/linux-master/drivers/scsi/
H A Dscsi_common.c294 buf[7] = 0xa;
328 ucp[1] = 0xa;
/linux-master/arch/alpha/lib/
H A Dev6-csum_ipv6_magic.S106 zapnot $18,0xa,$18 # U : 00000000DD00BB00
107 zap $4,0xa,$4 # U : U U L L : 0000000000CC00AA
/linux-master/drivers/ata/pata_parport/
H A Dfit3.c146 w2(0xc); w0(0); w2(0xa);
155 w2(0xc); w0(0xa); w2(0x8); w2(0xc);
/linux-master/drivers/gpu/drm/xe/
H A Dxe_device_types.h537 struct xarray xa; member in struct:xe_file::__anon838
545 struct xarray xa; member in struct:xe_file::__anon839
/linux-master/drivers/media/pci/intel/ipu6/
H A Dipu6-platform-buttress-regs.h88 #define BUTTRESS_PWR_STATE_IS_PWR_FSM_IS_RDY 0xa
107 #define BUTTRESS_PWR_STATE_PS_PWR_FSM_STOP_CLK_CYCLES2 0xa
/linux-master/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
H A Dhal_btc.c1012 btdm8723.ps_tdma_byte[1] = 0xa;
1013 btdm8723.ps_tdma_byte[2] = 0xa;
1075 btdm8723.ps_tdma_byte[1] = 0xa;
1076 btdm8723.ps_tdma_byte[2] = 0xa;
1103 btdm8723.ps_tdma_byte[1] = 0xa;
1104 btdm8723.ps_tdma_byte[2] = 0xa;
1197 btdm8723.ps_tdma_byte[1] = 0xa;
1198 btdm8723.ps_tdma_byte[2] = 0xa;
1226 btdm8723.ps_tdma_byte[1] = 0xa;
1227 btdm8723.ps_tdma_byte[2] = 0xa;
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/linux-master/drivers/crypto/intel/qat/qat_common/
H A Dqat_asym_algs.c85 dma_addr_t xa; member in struct:qat_dh_input_params::__anon237::__anon238
89 dma_addr_t xa; member in struct:qat_dh_input_params::__anon237::__anon239
105 char *xa; member in struct:qat_dh_ctx
233 if (unlikely(!ctx->xa))
265 qat_req->in.dh.in.xa = ctx->dma_xa;
270 qat_req->in.dh.in_g2.xa = ctx->dma_xa;
275 qat_req->in.dh.in.xa = ctx->dma_xa;
335 /* Mapping in.in.b or in.in_g2.xa is the same */
461 if (ctx->xa) {
462 memset(ctx->xa,
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/linux-master/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_1_0_sh_mask.h365 #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
700 #define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa
1067 #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
1479 #define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa
1570 #define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa
2041 #define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
2376 #define DAGB1_RD_TLB_CREDIT__TLB2__SHIFT 0xa
2743 #define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
3155 #define DAGB1_WR_TLB_CREDIT__TLB2__SHIFT 0xa
3246 #define DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT 0xa
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H A Dmmhub_9_4_1_sh_mask.h365 #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
702 #define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa
1069 #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
1483 #define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa
1574 #define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa
2040 #define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
2377 #define DAGB1_RD_TLB_CREDIT__TLB2__SHIFT 0xa
2744 #define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa
3158 #define DAGB1_WR_TLB_CREDIT__TLB2__SHIFT 0xa
3249 #define DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT 0xa
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/linux-master/drivers/pinctrl/mvebu/
H A Dpinctrl-kirkwood.c110 MPP_VAR_FUNCTION(0xa, "audio", "spdifo", V(0, 0, 0, 0, 1, 0, 0)),
117 MPP_VAR_FUNCTION(0xa, "audio", "rmclk", V(0, 0, 0, 0, 1, 0, 0)),
124 MPP_VAR_FUNCTION(0xa, "audio", "spdifi", V(0, 0, 0, 0, 1, 0, 0)),
146 MPP_VAR_FUNCTION(0xa, "sata1", "act", V(0, 0, 0, 0, 1, 0, 0)),
358 MPP_VAR_FUNCTION(0xa, "pex", "clkreq", V(0, 0, 0, 0, 1, 0, 0)),
/linux-master/drivers/gpu/drm/amd/include/asic_reg/sdma/
H A Dsdma_4_4_2_sh_mask.h105 #define SDMA_CONTEXT_REG_TYPE0__SDMA_GFX_IB_CNTL__SHIFT 0xa
138 #define SDMA_CONTEXT_REG_TYPE1__SDMA_GFX_WATERMARK__SHIFT 0xa
175 #define SDMA_CONTEXT_REG_TYPE2__SDMA_GFX_MIDCMD_DATA10__SHIFT 0xa
200 #define SDMA_PUB_REG_TYPE0__RESERVED_14_10__SHIFT 0xa
250 #define SDMA_PUB_REG_TYPE1__RESERVED_10_10__SHIFT 0xa
315 #define SDMA_PUB_REG_TYPE2__SDMA_RELAX_ORDERING_LUT__SHIFT 0xa
431 #define SDMA_STATUS_REG__EX_IDLE__SHIFT 0xa
494 #define SDMA_STATUS1_REG__CE_AFIFO_FULL__SHIFT 0xa
571 #define SDMA_PGFSM_CONFIG__P1_SELECT__SHIFT 0xa
618 #define SDMA_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT 0xa
[all...]
/linux-master/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_1_sh_mask.h68 #define MC_ARB_AGE_CNTL__RESET_WR_GROUP2__SHIFT 0xa
98 #define MC_ARB_RET_CREDITS2__ACP_RDRET_URG__SHIFT 0xa
138 #define MC_ARB_GECC2_STATUS__FED_CLEAR0__SHIFT 0xa
186 #define MC_ARB_GECC2_MISC__CWRD_REPLAY_AGAIN__SHIFT 0xa
284 #define MC_ARB_WCDR_2__DEBUG_1__SHIFT 0xa
314 #define MC_ARB_RTT_CNTL0__BREAK_ON_URGENTWR__SHIFT 0xa
394 #define MC_ARB_MISC2__TCCDL4_BANKBIT3_XOR_COLBIT8__SHIFT 0xa
472 #define MC_ARB_RAMCFG__RSV_2__SHIFT 0xa
512 #define MC_ARB_SQM_CNTL__SQM_RESERVE__SHIFT 0xa
558 #define MC_ARB_WTM_CNTL_RD__ALLOW_STUTTER_GRP7__SHIFT 0xa
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