Searched refs:x20 (Results 151 - 175 of 5856) sorted by relevance

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/linux-master/arch/mips/loongson64/
H A Dsmp.h29 #define BUF 0x20
/linux-master/arch/mips/include/asm/sn/
H A Dkldir.h12 #define KLDIR_OFF_COUNT 0x20
/linux-master/arch/arm/mach-s3c/
H A Dregs-usb-hsotg-phy-s3c64xx.h45 #define S3C_PHYTUNE S3C_HSOTG_PHYREG(0x20)
/linux-master/include/linux/
H A Dsmp_types.h19 CSD_TYPE_IRQ_WORK = 0x20,
/linux-master/include/linux/qed/
H A Drdma_common.h23 #define RDMA_RESP_RD_ATOMIC_ELM_SIZE (0x20)
/linux-master/arch/arm/mach-socfpga/
H A Dcore.h16 #define SOCFPGA_A10_RSTMGR_MODMPURST 0x20
/linux-master/include/uapi/linux/tc_act/
H A Dtc_skbedit.h18 #define SKBEDIT_F_INHERITDSFIELD 0x20
/linux-master/arch/parisc/include/asm/
H A Dled.h7 #define LED5 0x20
H A Deisa_eeprom.h41 #define HPEE_SLOT_INFO_VIRTUAL 0x20
59 #define HPEE_FUNCTION_INFO_HAVE_PORT_INIT 0x20
84 #define HPEE_MEMORY_SHARED 0x20
105 #define HPEE_IRQ_TRIG_LEVEL 0x20
124 #define HPEE_DMA_TIMING_TYPEB 0x20
/linux-master/sound/soc/codecs/
H A Des8316.h60 #define ES8316_CAL_HPLMV 0x20
105 #define ES8316_CLKMGR_CLKSW_BCLK_ON 0x20
109 #define ES8316_SERDATA1_BCLK_INV 0x20
117 #define ES8316_SERDATA2_ADCLRP 0x20
H A Dwm2000.h38 #define WM2000_STATUS_CAT_FREQ_COMPLETE 0x20
48 #define WM2000_MODE_CAT_FREQ_ENABLE 0x20
61 #define WM2000_ANC_ENG_CLR 0x20
/linux-master/drivers/gpu/drm/radeon/
H A Devergreen_smc.h59 #define EVERGREEN_SMC_FIRMWARE_HEADER_mcRegisterTable 0x20
/linux-master/arch/mips/include/asm/
H A Dhpet.h15 #define HPET_Tn_CFG(n) (0x100 + 0x20 * n)
16 #define HPET_Tn_CMP(n) (0x108 + 0x20 * n)
17 #define HPET_Tn_ROUTE(n) (0x110 + 0x20 * n)
/linux-master/arch/sparc/include/asm/
H A Dturbosparc.h84 for (addr = 0; addr < 0x4000; addr += 0x20)
92 for (addr = 0; addr < 0x4000; addr += 0x20)
100 for (addr = 0; addr < 0x4000; addr += 0x20) {
/linux-master/drivers/tty/serial/
H A Dip22zilog.h60 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
81 #define WT_RDY_RT 0x20 /* Wait/Ready on R/T */
94 #define AUTO_ENAB 0x20 /* Auto Enables */
113 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
130 #define Tx7 0x20 /* Tx 7 bits/character */
160 #define NRZI 0x20 /* NRZI mode */
176 #define RCTRxCP 0x20 /* Receive clock = TRxC pin */
191 #define SEARCH 0x20 /* Enter search mode */
203 #define CTSIE 0x20 /* CTS IE */
214 #define CTS 0x20 /* CT
[all...]
H A Dpmac_zilog.h139 #define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
160 #define WT_RDY_RT 0x20 /* W/Req reflects recv if 1, xmit if 0 */
173 #define AUTO_ENAB 0x20 /* Auto Enables */
193 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
210 #define Tx7 0x20 /* Tx 7 bits/character */
243 #define NRZI 0x20 /* NRZI mode */
259 #define RCTRxCP 0x20 /* Receive clock = TRxC pin */
274 #define SEARCH 0x20 /* Enter search mode */
288 #define CTSIE 0x20 /* CTS IE */
299 #define CTS 0x20 /* CT
[all...]
/linux-master/sound/pci/oxygen/
H A Dpcm1796.h19 #define PCM1796_FMT_24_RJUST 0x20
33 #define PCM1796_ATS_2 0x20
47 #define PCM1796_DSD 0x20
/linux-master/include/uapi/linux/
H A Dbpf_common.h24 #define BPF_ABS 0x20
34 #define BPF_MUL 0x20
46 #define BPF_JGT 0x20
/linux-master/tools/include/uapi/linux/
H A Dbpf_common.h24 #define BPF_ABS 0x20
34 #define BPF_MUL 0x20
46 #define BPF_JGT 0x20
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/privring/
H A Dgk20a.c31 nvkm_mask(device, 0x000200, 0x20, 0);
33 nvkm_mask(device, 0x000200, 0x20, 0x20);
/linux-master/arch/powerpc/sysdev/
H A Di8259.c44 outb(0x0C, 0x20); /* prepare for poll */
45 irq = inb(0x20) & 7;
65 outb(0x0B, 0x20); /* ISR register */
66 if(~inb(0x20) & 0x80)
85 outb(0x20, 0xA0); /* Non-specific EOI */
86 outb(0x20, 0x20); /* Non-specific EOI to cascade */
91 outb(0x20, 0x20); /* Non-specific EOI */
142 .start = 0x20,
[all...]
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_umr.h81 #define AMDGPU_DEBUGFS_REGS2_IOC_SET_STATE _IOWR(0x20, AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE, struct amdgpu_debugfs_regs2_iocdata)
82 #define AMDGPU_DEBUGFS_REGS2_IOC_SET_STATE_V2 _IOWR(0x20, AMDGPU_DEBUGFS_REGS2_CMD_SET_STATE_V2, struct amdgpu_debugfs_regs2_iocdata_v2)
85 #define AMDGPU_DEBUGFS_GPRWAVE_IOC_SET_STATE _IOWR(0x20, AMDGPU_DEBUGFS_GPRWAVE_CMD_SET_STATE, struct amdgpu_debugfs_gprwave_iocdata)
/linux-master/drivers/pinctrl/mediatek/
H A Dpinctrl-mt7981.c41 PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1),
42 PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1),
43 PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1),
44 PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1),
45 PIN_FIELD_BASE(6, 6, 4, 0x20, 0x10, 3, 1),
46 PIN_FIELD_BASE(7, 7, 4, 0x20, 0x10, 0, 1),
47 PIN_FIELD_BASE(8, 8, 4, 0x20, 0x10, 4, 1),
49 PIN_FIELD_BASE(9, 9, 5, 0x20, 0x10, 9, 1),
50 PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1),
52 PIN_FIELD_BASE(12, 12, 5, 0x20,
[all...]
/linux-master/drivers/gpu/drm/nouveau/nvkm/engine/pm/
H A Dnv40.c101 { 0x20, (const struct nvkm_specsig[]) {
104 { 0x20, (const struct nvkm_specsig[]) {
107 { 0x20, (const struct nvkm_specsig[]) {
110 { 0x20, (const struct nvkm_specsig[]) {
113 { 0x20, (const struct nvkm_specsig[]) {
/linux-master/arch/m68k/include/asm/
H A Dmac_via.h56 #define VIA1A_vHeadSel 0x20 /* Head select for IWM.
73 * (with 0x20 being 'disk head select')
108 #define VIA1B_vADBS2 0x20 /* ADB state input bit 1 (unused on IIfx) */
120 #define EVRB_SYSES 0x20 /* SYS_SESSION */
138 #define VIA2A_vIRQE 0x20 /* IRQ from slot $E */
163 #define VIA2B_vTfr0 0x20 /* Transfer mode bit 0 ack from NuBus */

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