1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef _IP22_ZILOG_H 3#define _IP22_ZILOG_H 4 5#include <asm/byteorder.h> 6 7struct zilog_channel { 8#ifdef __BIG_ENDIAN 9 volatile unsigned char unused0[3]; 10 volatile unsigned char control; 11 volatile unsigned char unused1[3]; 12 volatile unsigned char data; 13#else /* __LITTLE_ENDIAN */ 14 volatile unsigned char control; 15 volatile unsigned char unused0[3]; 16 volatile unsigned char data; 17 volatile unsigned char unused1[3]; 18#endif 19}; 20 21struct zilog_layout { 22 struct zilog_channel channelB; 23 struct zilog_channel channelA; 24}; 25 26#define NUM_ZSREGS 16 27 28/* Conversion routines to/from brg time constants from/to bits 29 * per second. 30 */ 31#define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2)) 32#define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2) 33 34/* The Zilog register set */ 35 36#define FLAG 0x7e 37 38/* Write Register 0 */ 39#define R0 0 /* Register selects */ 40#define R1 1 41#define R2 2 42#define R3 3 43#define R4 4 44#define R5 5 45#define R6 6 46#define R7 7 47#define R8 8 48#define R9 9 49#define R10 10 50#define R11 11 51#define R12 12 52#define R13 13 53#define R14 14 54#define R15 15 55 56#define NULLCODE 0 /* Null Code */ 57#define POINT_HIGH 0x8 /* Select upper half of registers */ 58#define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */ 59#define SEND_ABORT 0x18 /* HDLC Abort */ 60#define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */ 61#define RES_Tx_P 0x28 /* Reset TxINT Pending */ 62#define ERR_RES 0x30 /* Error Reset */ 63#define RES_H_IUS 0x38 /* Reset highest IUS */ 64 65#define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */ 66#define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */ 67#define RES_EOM_L 0xC0 /* Reset EOM latch */ 68 69/* Write Register 1 */ 70 71#define EXT_INT_ENAB 0x1 /* Ext Int Enable */ 72#define TxINT_ENAB 0x2 /* Tx Int Enable */ 73#define PAR_SPEC 0x4 /* Parity is special condition */ 74 75#define RxINT_DISAB 0 /* Rx Int Disable */ 76#define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */ 77#define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */ 78#define INT_ERR_Rx 0x18 /* Int on error only */ 79#define RxINT_MASK 0x18 80 81#define WT_RDY_RT 0x20 /* Wait/Ready on R/T */ 82#define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */ 83#define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */ 84 85/* Write Register #2 (Interrupt Vector) */ 86 87/* Write Register 3 */ 88 89#define RxENAB 0x1 /* Rx Enable */ 90#define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */ 91#define ADD_SM 0x4 /* Address Search Mode (SDLC) */ 92#define RxCRC_ENAB 0x8 /* Rx CRC Enable */ 93#define ENT_HM 0x10 /* Enter Hunt Mode */ 94#define AUTO_ENAB 0x20 /* Auto Enables */ 95#define Rx5 0x0 /* Rx 5 Bits/Character */ 96#define Rx7 0x40 /* Rx 7 Bits/Character */ 97#define Rx6 0x80 /* Rx 6 Bits/Character */ 98#define Rx8 0xc0 /* Rx 8 Bits/Character */ 99#define RxN_MASK 0xc0 100 101/* Write Register 4 */ 102 103#define PAR_ENAB 0x1 /* Parity Enable */ 104#define PAR_EVEN 0x2 /* Parity Even/Odd* */ 105 106#define SYNC_ENAB 0 /* Sync Modes Enable */ 107#define SB1 0x4 /* 1 stop bit/char */ 108#define SB15 0x8 /* 1.5 stop bits/char */ 109#define SB2 0xc /* 2 stop bits/char */ 110 111#define MONSYNC 0 /* 8 Bit Sync character */ 112#define BISYNC 0x10 /* 16 bit sync character */ 113#define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */ 114#define EXTSYNC 0x30 /* External Sync Mode */ 115 116#define X1CLK 0x0 /* x1 clock mode */ 117#define X16CLK 0x40 /* x16 clock mode */ 118#define X32CLK 0x80 /* x32 clock mode */ 119#define X64CLK 0xC0 /* x64 clock mode */ 120#define XCLK_MASK 0xC0 121 122/* Write Register 5 */ 123 124#define TxCRC_ENAB 0x1 /* Tx CRC Enable */ 125#define RTS 0x2 /* RTS */ 126#define SDLC_CRC 0x4 /* SDLC/CRC-16 */ 127#define TxENAB 0x8 /* Tx Enable */ 128#define SND_BRK 0x10 /* Send Break */ 129#define Tx5 0x0 /* Tx 5 bits (or less)/character */ 130#define Tx7 0x20 /* Tx 7 bits/character */ 131#define Tx6 0x40 /* Tx 6 bits/character */ 132#define Tx8 0x60 /* Tx 8 bits/character */ 133#define TxN_MASK 0x60 134#define DTR 0x80 /* DTR */ 135 136/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */ 137 138/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */ 139 140/* Write Register 8 (transmit buffer) */ 141 142/* Write Register 9 (Master interrupt control) */ 143#define VIS 1 /* Vector Includes Status */ 144#define NV 2 /* No Vector */ 145#define DLC 4 /* Disable Lower Chain */ 146#define MIE 8 /* Master Interrupt Enable */ 147#define STATHI 0x10 /* Status high */ 148#define NORESET 0 /* No reset on write to R9 */ 149#define CHRB 0x40 /* Reset channel B */ 150#define CHRA 0x80 /* Reset channel A */ 151#define FHWRES 0xc0 /* Force hardware reset */ 152 153/* Write Register 10 (misc control bits) */ 154#define BIT6 1 /* 6 bit/8bit sync */ 155#define LOOPMODE 2 /* SDLC Loop mode */ 156#define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */ 157#define MARKIDLE 8 /* Mark/flag on idle */ 158#define GAOP 0x10 /* Go active on poll */ 159#define NRZ 0 /* NRZ mode */ 160#define NRZI 0x20 /* NRZI mode */ 161#define FM1 0x40 /* FM1 (transition = 1) */ 162#define FM0 0x60 /* FM0 (transition = 0) */ 163#define CRCPS 0x80 /* CRC Preset I/O */ 164 165/* Write Register 11 (Clock Mode control) */ 166#define TRxCXT 0 /* TRxC = Xtal output */ 167#define TRxCTC 1 /* TRxC = Transmit clock */ 168#define TRxCBR 2 /* TRxC = BR Generator Output */ 169#define TRxCDP 3 /* TRxC = DPLL output */ 170#define TRxCOI 4 /* TRxC O/I */ 171#define TCRTxCP 0 /* Transmit clock = RTxC pin */ 172#define TCTRxCP 8 /* Transmit clock = TRxC pin */ 173#define TCBR 0x10 /* Transmit clock = BR Generator output */ 174#define TCDPLL 0x18 /* Transmit clock = DPLL output */ 175#define RCRTxCP 0 /* Receive clock = RTxC pin */ 176#define RCTRxCP 0x20 /* Receive clock = TRxC pin */ 177#define RCBR 0x40 /* Receive clock = BR Generator output */ 178#define RCDPLL 0x60 /* Receive clock = DPLL output */ 179#define RTxCX 0x80 /* RTxC Xtal/No Xtal */ 180 181/* Write Register 12 (lower byte of baud rate generator time constant) */ 182 183/* Write Register 13 (upper byte of baud rate generator time constant) */ 184 185/* Write Register 14 (Misc control bits) */ 186#define BRENAB 1 /* Baud rate generator enable */ 187#define BRSRC 2 /* Baud rate generator source */ 188#define DTRREQ 4 /* DTR/Request function */ 189#define AUTOECHO 8 /* Auto Echo */ 190#define LOOPBAK 0x10 /* Local loopback */ 191#define SEARCH 0x20 /* Enter search mode */ 192#define RMC 0x40 /* Reset missing clock */ 193#define DISDPLL 0x60 /* Disable DPLL */ 194#define SSBR 0x80 /* Set DPLL source = BR generator */ 195#define SSRTxC 0xa0 /* Set DPLL source = RTxC */ 196#define SFMM 0xc0 /* Set FM mode */ 197#define SNRZI 0xe0 /* Set NRZI mode */ 198 199/* Write Register 15 (external/status interrupt control) */ 200#define ZCIE 2 /* Zero count IE */ 201#define DCDIE 8 /* DCD IE */ 202#define SYNCIE 0x10 /* Sync/hunt IE */ 203#define CTSIE 0x20 /* CTS IE */ 204#define TxUIE 0x40 /* Tx Underrun/EOM IE */ 205#define BRKIE 0x80 /* Break/Abort IE */ 206 207 208/* Read Register 0 */ 209#define Rx_CH_AV 0x1 /* Rx Character Available */ 210#define ZCOUNT 0x2 /* Zero count */ 211#define Tx_BUF_EMP 0x4 /* Tx Buffer empty */ 212#define DCD 0x8 /* DCD */ 213#define SYNC 0x10 /* Sync/hunt */ 214#define CTS 0x20 /* CTS */ 215#define TxEOM 0x40 /* Tx underrun */ 216#define BRK_ABRT 0x80 /* Break/Abort */ 217 218/* Read Register 1 */ 219#define ALL_SNT 0x1 /* All sent */ 220/* Residue Data for 8 Rx bits/char programmed */ 221#define RES3 0x8 /* 0/3 */ 222#define RES4 0x4 /* 0/4 */ 223#define RES5 0xc /* 0/5 */ 224#define RES6 0x2 /* 0/6 */ 225#define RES7 0xa /* 0/7 */ 226#define RES8 0x6 /* 0/8 */ 227#define RES18 0xe /* 1/8 */ 228#define RES28 0x0 /* 2/8 */ 229/* Special Rx Condition Interrupts */ 230#define PAR_ERR 0x10 /* Parity error */ 231#define Rx_OVR 0x20 /* Rx Overrun Error */ 232#define CRC_ERR 0x40 /* CRC/Framing Error */ 233#define END_FR 0x80 /* End of Frame (SDLC) */ 234 235/* Read Register 2 (channel b only) - Interrupt vector */ 236#define CHB_Tx_EMPTY 0x00 237#define CHB_EXT_STAT 0x02 238#define CHB_Rx_AVAIL 0x04 239#define CHB_SPECIAL 0x06 240#define CHA_Tx_EMPTY 0x08 241#define CHA_EXT_STAT 0x0a 242#define CHA_Rx_AVAIL 0x0c 243#define CHA_SPECIAL 0x0e 244#define STATUS_MASK 0x0e 245 246/* Read Register 3 (interrupt pending register) ch a only */ 247#define CHBEXT 0x1 /* Channel B Ext/Stat IP */ 248#define CHBTxIP 0x2 /* Channel B Tx IP */ 249#define CHBRxIP 0x4 /* Channel B Rx IP */ 250#define CHAEXT 0x8 /* Channel A Ext/Stat IP */ 251#define CHATxIP 0x10 /* Channel A Tx IP */ 252#define CHARxIP 0x20 /* Channel A Rx IP */ 253 254/* Read Register 8 (receive data register) */ 255 256/* Read Register 10 (misc status bits) */ 257#define ONLOOP 2 /* On loop */ 258#define LOOPSEND 0x10 /* Loop sending */ 259#define CLK2MIS 0x40 /* Two clocks missing */ 260#define CLK1MIS 0x80 /* One clock missing */ 261 262/* Read Register 12 (lower byte of baud rate generator constant) */ 263 264/* Read Register 13 (upper byte of baud rate generator constant) */ 265 266/* Read Register 15 (value of WR 15) */ 267 268/* Misc macros */ 269#define ZS_CLEARERR(channel) do { writeb(ERR_RES, &channel->control); \ 270 udelay(5); } while(0) 271 272#define ZS_CLEARSTAT(channel) do { writeb(RES_EXT_INT, &channel->control); \ 273 udelay(5); } while(0) 274 275#define ZS_CLEARFIFO(channel) do { readb(&channel->data); \ 276 udelay(2); \ 277 readb(&channel->data); \ 278 udelay(2); \ 279 readb(&channel->data); \ 280 udelay(2); } while(0) 281 282#endif /* _IP22_ZILOG_H */ 283