1// SPDX-License-Identifier: GPL-2.0 2/* 3 * The MT7981 driver based on Linux generic pinctrl binding. 4 * 5 * Copyright (C) 2020 MediaTek Inc. 6 * Author: Sam Shih <sam.shih@mediatek.com> 7 */ 8 9#include "pinctrl-moore.h" 10 11#define MT7981_PIN(_number, _name) \ 12 MTK_PIN(_number, _name, 0, _number, DRV_GRP4) 13 14#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \ 15 PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ 16 _x_bits, 32, 0) 17 18#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, _x_bits) \ 19 PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ 20 _x_bits, 32, 1) 21 22static const struct mtk_pin_field_calc mt7981_pin_mode_range[] = { 23 PIN_FIELD(0, 56, 0x300, 0x10, 0, 4), 24}; 25 26static const struct mtk_pin_field_calc mt7981_pin_dir_range[] = { 27 PIN_FIELD(0, 56, 0x0, 0x10, 0, 1), 28}; 29 30static const struct mtk_pin_field_calc mt7981_pin_di_range[] = { 31 PIN_FIELD(0, 56, 0x200, 0x10, 0, 1), 32}; 33 34static const struct mtk_pin_field_calc mt7981_pin_do_range[] = { 35 PIN_FIELD(0, 56, 0x100, 0x10, 0, 1), 36}; 37 38static const struct mtk_pin_field_calc mt7981_pin_ies_range[] = { 39 PIN_FIELD_BASE(0, 0, 1, 0x10, 0x10, 1, 1), 40 PIN_FIELD_BASE(1, 1, 1, 0x10, 0x10, 0, 1), 41 PIN_FIELD_BASE(2, 2, 5, 0x20, 0x10, 6, 1), 42 PIN_FIELD_BASE(3, 3, 4, 0x20, 0x10, 6, 1), 43 PIN_FIELD_BASE(4, 4, 4, 0x20, 0x10, 2, 1), 44 PIN_FIELD_BASE(5, 5, 4, 0x20, 0x10, 1, 1), 45 PIN_FIELD_BASE(6, 6, 4, 0x20, 0x10, 3, 1), 46 PIN_FIELD_BASE(7, 7, 4, 0x20, 0x10, 0, 1), 47 PIN_FIELD_BASE(8, 8, 4, 0x20, 0x10, 4, 1), 48 49 PIN_FIELD_BASE(9, 9, 5, 0x20, 0x10, 9, 1), 50 PIN_FIELD_BASE(10, 10, 5, 0x20, 0x10, 8, 1), 51 PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1), 52 PIN_FIELD_BASE(12, 12, 5, 0x20, 0x10, 7, 1), 53 PIN_FIELD_BASE(13, 13, 5, 0x20, 0x10, 11, 1), 54 55 PIN_FIELD_BASE(14, 14, 4, 0x20, 0x10, 8, 1), 56 57 PIN_FIELD_BASE(15, 15, 2, 0x20, 0x10, 0, 1), 58 PIN_FIELD_BASE(16, 16, 2, 0x20, 0x10, 1, 1), 59 PIN_FIELD_BASE(17, 17, 2, 0x20, 0x10, 5, 1), 60 PIN_FIELD_BASE(18, 18, 2, 0x20, 0x10, 4, 1), 61 PIN_FIELD_BASE(19, 19, 2, 0x20, 0x10, 2, 1), 62 PIN_FIELD_BASE(20, 20, 2, 0x20, 0x10, 3, 1), 63 PIN_FIELD_BASE(21, 21, 2, 0x20, 0x10, 6, 1), 64 PIN_FIELD_BASE(22, 22, 2, 0x20, 0x10, 7, 1), 65 PIN_FIELD_BASE(23, 23, 2, 0x20, 0x10, 10, 1), 66 PIN_FIELD_BASE(24, 24, 2, 0x20, 0x10, 9, 1), 67 PIN_FIELD_BASE(25, 25, 2, 0x20, 0x10, 8, 1), 68 69 PIN_FIELD_BASE(26, 26, 5, 0x20, 0x10, 0, 1), 70 PIN_FIELD_BASE(27, 27, 5, 0x20, 0x10, 4, 1), 71 PIN_FIELD_BASE(28, 28, 5, 0x20, 0x10, 3, 1), 72 PIN_FIELD_BASE(29, 29, 5, 0x20, 0x10, 1, 1), 73 PIN_FIELD_BASE(30, 30, 5, 0x20, 0x10, 2, 1), 74 PIN_FIELD_BASE(31, 31, 5, 0x20, 0x10, 5, 1), 75 76 PIN_FIELD_BASE(32, 32, 1, 0x10, 0x10, 2, 1), 77 PIN_FIELD_BASE(33, 33, 1, 0x10, 0x10, 3, 1), 78 79 PIN_FIELD_BASE(34, 34, 4, 0x20, 0x10, 5, 1), 80 PIN_FIELD_BASE(35, 35, 4, 0x20, 0x10, 7, 1), 81 82 PIN_FIELD_BASE(36, 36, 3, 0x10, 0x10, 2, 1), 83 PIN_FIELD_BASE(37, 37, 3, 0x10, 0x10, 3, 1), 84 PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 0, 1), 85 PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 1, 1), 86 87 PIN_FIELD_BASE(40, 40, 7, 0x30, 0x10, 1, 1), 88 PIN_FIELD_BASE(41, 41, 7, 0x30, 0x10, 0, 1), 89 PIN_FIELD_BASE(42, 42, 7, 0x30, 0x10, 9, 1), 90 PIN_FIELD_BASE(43, 43, 7, 0x30, 0x10, 7, 1), 91 PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1), 92 PIN_FIELD_BASE(45, 45, 7, 0x30, 0x10, 3, 1), 93 PIN_FIELD_BASE(46, 46, 7, 0x30, 0x10, 4, 1), 94 PIN_FIELD_BASE(47, 47, 7, 0x30, 0x10, 5, 1), 95 PIN_FIELD_BASE(48, 48, 7, 0x30, 0x10, 6, 1), 96 PIN_FIELD_BASE(49, 49, 7, 0x30, 0x10, 2, 1), 97 98 PIN_FIELD_BASE(50, 50, 6, 0x10, 0x10, 0, 1), 99 PIN_FIELD_BASE(51, 51, 6, 0x10, 0x10, 2, 1), 100 PIN_FIELD_BASE(52, 52, 6, 0x10, 0x10, 3, 1), 101 PIN_FIELD_BASE(53, 53, 6, 0x10, 0x10, 4, 1), 102 PIN_FIELD_BASE(54, 54, 6, 0x10, 0x10, 5, 1), 103 PIN_FIELD_BASE(55, 55, 6, 0x10, 0x10, 6, 1), 104 PIN_FIELD_BASE(56, 56, 6, 0x10, 0x10, 1, 1), 105}; 106 107static const struct mtk_pin_field_calc mt7981_pin_smt_range[] = { 108 PIN_FIELD_BASE(0, 0, 1, 0x60, 0x10, 1, 1), 109 PIN_FIELD_BASE(1, 1, 1, 0x60, 0x10, 0, 1), 110 PIN_FIELD_BASE(2, 2, 5, 0x90, 0x10, 6, 1), 111 PIN_FIELD_BASE(3, 3, 4, 0x80, 0x10, 6, 1), 112 PIN_FIELD_BASE(4, 4, 4, 0x80, 0x10, 2, 1), 113 PIN_FIELD_BASE(5, 5, 4, 0x80, 0x10, 1, 1), 114 PIN_FIELD_BASE(6, 6, 4, 0x80, 0x10, 3, 1), 115 PIN_FIELD_BASE(7, 7, 4, 0x80, 0x10, 0, 1), 116 PIN_FIELD_BASE(8, 8, 4, 0x80, 0x10, 4, 1), 117 118 PIN_FIELD_BASE(9, 9, 5, 0x90, 0x10, 9, 1), 119 PIN_FIELD_BASE(10, 10, 5, 0x90, 0x10, 8, 1), 120 PIN_FIELD_BASE(11, 11, 5, 0x90, 0x10, 10, 1), 121 PIN_FIELD_BASE(12, 12, 5, 0x90, 0x10, 7, 1), 122 PIN_FIELD_BASE(13, 13, 5, 0x90, 0x10, 11, 1), 123 124 PIN_FIELD_BASE(14, 14, 4, 0x80, 0x10, 8, 1), 125 126 PIN_FIELD_BASE(15, 15, 2, 0x90, 0x10, 0, 1), 127 PIN_FIELD_BASE(16, 16, 2, 0x90, 0x10, 1, 1), 128 PIN_FIELD_BASE(17, 17, 2, 0x90, 0x10, 5, 1), 129 PIN_FIELD_BASE(18, 18, 2, 0x90, 0x10, 4, 1), 130 PIN_FIELD_BASE(19, 19, 2, 0x90, 0x10, 2, 1), 131 PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1), 132 PIN_FIELD_BASE(21, 21, 2, 0x90, 0x10, 6, 1), 133 PIN_FIELD_BASE(22, 22, 2, 0x90, 0x10, 7, 1), 134 PIN_FIELD_BASE(23, 23, 2, 0x90, 0x10, 10, 1), 135 PIN_FIELD_BASE(24, 24, 2, 0x90, 0x10, 9, 1), 136 PIN_FIELD_BASE(25, 25, 2, 0x90, 0x10, 8, 1), 137 138 PIN_FIELD_BASE(26, 26, 5, 0x90, 0x10, 0, 1), 139 PIN_FIELD_BASE(27, 27, 5, 0x90, 0x10, 4, 1), 140 PIN_FIELD_BASE(28, 28, 5, 0x90, 0x10, 3, 1), 141 PIN_FIELD_BASE(29, 29, 5, 0x90, 0x10, 1, 1), 142 PIN_FIELD_BASE(30, 30, 5, 0x90, 0x10, 2, 1), 143 PIN_FIELD_BASE(31, 31, 5, 0x90, 0x10, 5, 1), 144 145 PIN_FIELD_BASE(32, 32, 1, 0x60, 0x10, 2, 1), 146 PIN_FIELD_BASE(33, 33, 1, 0x60, 0x10, 3, 1), 147 148 PIN_FIELD_BASE(34, 34, 4, 0x80, 0x10, 5, 1), 149 PIN_FIELD_BASE(35, 35, 4, 0x80, 0x10, 7, 1), 150 151 PIN_FIELD_BASE(36, 36, 3, 0x60, 0x10, 2, 1), 152 PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 3, 1), 153 PIN_FIELD_BASE(38, 38, 3, 0x60, 0x10, 0, 1), 154 PIN_FIELD_BASE(39, 39, 3, 0x60, 0x10, 1, 1), 155 156 PIN_FIELD_BASE(40, 40, 7, 0x70, 0x10, 1, 1), 157 PIN_FIELD_BASE(41, 41, 7, 0x70, 0x10, 0, 1), 158 PIN_FIELD_BASE(42, 42, 7, 0x70, 0x10, 9, 1), 159 PIN_FIELD_BASE(43, 43, 7, 0x70, 0x10, 7, 1), 160 PIN_FIELD_BASE(44, 44, 7, 0x30, 0x10, 8, 1), 161 PIN_FIELD_BASE(45, 45, 7, 0x70, 0x10, 3, 1), 162 PIN_FIELD_BASE(46, 46, 7, 0x70, 0x10, 4, 1), 163 PIN_FIELD_BASE(47, 47, 7, 0x70, 0x10, 5, 1), 164 PIN_FIELD_BASE(48, 48, 7, 0x70, 0x10, 6, 1), 165 PIN_FIELD_BASE(49, 49, 7, 0x70, 0x10, 2, 1), 166 167 PIN_FIELD_BASE(50, 50, 6, 0x50, 0x10, 0, 1), 168 PIN_FIELD_BASE(51, 51, 6, 0x50, 0x10, 2, 1), 169 PIN_FIELD_BASE(52, 52, 6, 0x50, 0x10, 3, 1), 170 PIN_FIELD_BASE(53, 53, 6, 0x50, 0x10, 4, 1), 171 PIN_FIELD_BASE(54, 54, 6, 0x50, 0x10, 5, 1), 172 PIN_FIELD_BASE(55, 55, 6, 0x50, 0x10, 6, 1), 173 PIN_FIELD_BASE(56, 56, 6, 0x50, 0x10, 1, 1), 174}; 175 176static const struct mtk_pin_field_calc mt7981_pin_pu_range[] = { 177 PIN_FIELD_BASE(40, 40, 7, 0x50, 0x10, 1, 1), 178 PIN_FIELD_BASE(41, 41, 7, 0x50, 0x10, 0, 1), 179 PIN_FIELD_BASE(42, 42, 7, 0x50, 0x10, 9, 1), 180 PIN_FIELD_BASE(43, 43, 7, 0x50, 0x10, 7, 1), 181 PIN_FIELD_BASE(44, 44, 7, 0x50, 0x10, 8, 1), 182 PIN_FIELD_BASE(45, 45, 7, 0x50, 0x10, 3, 1), 183 PIN_FIELD_BASE(46, 46, 7, 0x50, 0x10, 4, 1), 184 PIN_FIELD_BASE(47, 47, 7, 0x50, 0x10, 5, 1), 185 PIN_FIELD_BASE(48, 48, 7, 0x50, 0x10, 6, 1), 186 PIN_FIELD_BASE(49, 49, 7, 0x50, 0x10, 2, 1), 187 188 PIN_FIELD_BASE(50, 50, 6, 0x30, 0x10, 0, 1), 189 PIN_FIELD_BASE(51, 51, 6, 0x30, 0x10, 2, 1), 190 PIN_FIELD_BASE(52, 52, 6, 0x30, 0x10, 3, 1), 191 PIN_FIELD_BASE(53, 53, 6, 0x30, 0x10, 4, 1), 192 PIN_FIELD_BASE(54, 54, 6, 0x30, 0x10, 5, 1), 193 PIN_FIELD_BASE(55, 55, 6, 0x30, 0x10, 6, 1), 194 PIN_FIELD_BASE(56, 56, 6, 0x30, 0x10, 1, 1), 195}; 196 197static const struct mtk_pin_field_calc mt7981_pin_pd_range[] = { 198 PIN_FIELD_BASE(40, 40, 7, 0x40, 0x10, 1, 1), 199 PIN_FIELD_BASE(41, 41, 7, 0x40, 0x10, 0, 1), 200 PIN_FIELD_BASE(42, 42, 7, 0x40, 0x10, 9, 1), 201 PIN_FIELD_BASE(43, 43, 7, 0x40, 0x10, 7, 1), 202 PIN_FIELD_BASE(44, 44, 7, 0x40, 0x10, 8, 1), 203 PIN_FIELD_BASE(45, 45, 7, 0x40, 0x10, 3, 1), 204 PIN_FIELD_BASE(46, 46, 7, 0x40, 0x10, 4, 1), 205 PIN_FIELD_BASE(47, 47, 7, 0x40, 0x10, 5, 1), 206 PIN_FIELD_BASE(48, 48, 7, 0x40, 0x10, 6, 1), 207 PIN_FIELD_BASE(49, 49, 7, 0x40, 0x10, 2, 1), 208 209 PIN_FIELD_BASE(50, 50, 6, 0x20, 0x10, 0, 1), 210 PIN_FIELD_BASE(51, 51, 6, 0x20, 0x10, 2, 1), 211 PIN_FIELD_BASE(52, 52, 6, 0x20, 0x10, 3, 1), 212 PIN_FIELD_BASE(53, 53, 6, 0x20, 0x10, 4, 1), 213 PIN_FIELD_BASE(54, 54, 6, 0x20, 0x10, 5, 1), 214 PIN_FIELD_BASE(55, 55, 6, 0x20, 0x10, 6, 1), 215 PIN_FIELD_BASE(56, 56, 6, 0x20, 0x10, 1, 1), 216}; 217 218static const struct mtk_pin_field_calc mt7981_pin_drv_range[] = { 219 PIN_FIELD_BASE(0, 0, 1, 0x00, 0x10, 3, 3), 220 PIN_FIELD_BASE(1, 1, 1, 0x00, 0x10, 0, 3), 221 222 PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 18, 3), 223 224 PIN_FIELD_BASE(3, 3, 4, 0x00, 0x10, 18, 1), 225 PIN_FIELD_BASE(4, 4, 4, 0x00, 0x10, 6, 1), 226 PIN_FIELD_BASE(5, 5, 4, 0x00, 0x10, 3, 3), 227 PIN_FIELD_BASE(6, 6, 4, 0x00, 0x10, 9, 3), 228 PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 0, 3), 229 PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 12, 3), 230 231 PIN_FIELD_BASE(9, 9, 5, 0x00, 0x10, 27, 3), 232 PIN_FIELD_BASE(10, 10, 5, 0x00, 0x10, 24, 3), 233 PIN_FIELD_BASE(11, 11, 5, 0x00, 0x10, 0, 3), 234 PIN_FIELD_BASE(12, 12, 5, 0x00, 0x10, 21, 3), 235 PIN_FIELD_BASE(13, 13, 5, 0x00, 0x10, 3, 3), 236 237 PIN_FIELD_BASE(14, 14, 4, 0x00, 0x10, 27, 3), 238 239 PIN_FIELD_BASE(15, 15, 2, 0x00, 0x10, 0, 3), 240 PIN_FIELD_BASE(16, 16, 2, 0x00, 0x10, 3, 3), 241 PIN_FIELD_BASE(17, 17, 2, 0x00, 0x10, 15, 3), 242 PIN_FIELD_BASE(18, 18, 2, 0x00, 0x10, 12, 3), 243 PIN_FIELD_BASE(19, 19, 2, 0x00, 0x10, 6, 3), 244 PIN_FIELD_BASE(20, 20, 2, 0x00, 0x10, 9, 3), 245 PIN_FIELD_BASE(21, 21, 2, 0x00, 0x10, 18, 3), 246 PIN_FIELD_BASE(22, 22, 2, 0x00, 0x10, 21, 3), 247 PIN_FIELD_BASE(23, 23, 2, 0x00, 0x10, 0, 3), 248 PIN_FIELD_BASE(24, 24, 2, 0x00, 0x10, 27, 3), 249 PIN_FIELD_BASE(25, 25, 2, 0x00, 0x10, 24, 3), 250 251 PIN_FIELD_BASE(26, 26, 5, 0x00, 0x10, 0, 3), 252 PIN_FIELD_BASE(27, 27, 5, 0x00, 0x10, 12, 3), 253 PIN_FIELD_BASE(28, 28, 5, 0x00, 0x10, 9, 3), 254 PIN_FIELD_BASE(29, 29, 5, 0x00, 0x10, 3, 3), 255 PIN_FIELD_BASE(30, 30, 5, 0x00, 0x10, 6, 3), 256 PIN_FIELD_BASE(31, 31, 5, 0x00, 0x10, 15, 3), 257 258 PIN_FIELD_BASE(32, 32, 1, 0x00, 0x10, 9, 3), 259 PIN_FIELD_BASE(33, 33, 1, 0x00, 0x10, 12, 3), 260 261 PIN_FIELD_BASE(34, 34, 4, 0x00, 0x10, 15, 3), 262 PIN_FIELD_BASE(35, 35, 4, 0x00, 0x10, 21, 3), 263 264 PIN_FIELD_BASE(36, 36, 3, 0x00, 0x10, 6, 3), 265 PIN_FIELD_BASE(37, 37, 3, 0x00, 0x10, 9, 3), 266 PIN_FIELD_BASE(38, 38, 3, 0x00, 0x10, 0, 3), 267 PIN_FIELD_BASE(39, 39, 3, 0x00, 0x10, 3, 3), 268 269 PIN_FIELD_BASE(40, 40, 7, 0x00, 0x10, 3, 3), 270 PIN_FIELD_BASE(41, 41, 7, 0x00, 0x10, 0, 3), 271 PIN_FIELD_BASE(42, 42, 7, 0x00, 0x10, 27, 3), 272 PIN_FIELD_BASE(43, 43, 7, 0x00, 0x10, 21, 3), 273 PIN_FIELD_BASE(44, 44, 7, 0x00, 0x10, 24, 3), 274 PIN_FIELD_BASE(45, 45, 7, 0x00, 0x10, 9, 3), 275 PIN_FIELD_BASE(46, 46, 7, 0x00, 0x10, 12, 3), 276 PIN_FIELD_BASE(47, 47, 7, 0x00, 0x10, 15, 3), 277 PIN_FIELD_BASE(48, 48, 7, 0x00, 0x10, 18, 3), 278 PIN_FIELD_BASE(49, 49, 7, 0x00, 0x10, 6, 3), 279 280 PIN_FIELD_BASE(50, 50, 6, 0x00, 0x10, 0, 3), 281 PIN_FIELD_BASE(51, 51, 6, 0x00, 0x10, 6, 3), 282 PIN_FIELD_BASE(52, 52, 6, 0x00, 0x10, 9, 3), 283 PIN_FIELD_BASE(53, 53, 6, 0x00, 0x10, 12, 3), 284 PIN_FIELD_BASE(54, 54, 6, 0x00, 0x10, 15, 3), 285 PIN_FIELD_BASE(55, 55, 6, 0x00, 0x10, 18, 3), 286 PIN_FIELD_BASE(56, 56, 6, 0x00, 0x10, 3, 3), 287}; 288 289static const struct mtk_pin_field_calc mt7981_pin_pupd_range[] = { 290 PIN_FIELD_BASE(0, 0, 1, 0x20, 0x10, 1, 1), 291 PIN_FIELD_BASE(1, 1, 1, 0x20, 0x10, 0, 1), 292 PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 6, 1), 293 PIN_FIELD_BASE(3, 3, 4, 0x30, 0x10, 6, 1), 294 PIN_FIELD_BASE(4, 4, 4, 0x30, 0x10, 2, 1), 295 PIN_FIELD_BASE(5, 5, 4, 0x30, 0x10, 1, 1), 296 PIN_FIELD_BASE(6, 6, 4, 0x30, 0x10, 3, 1), 297 PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 0, 1), 298 PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 4, 1), 299 300 PIN_FIELD_BASE(9, 9, 5, 0x30, 0x10, 9, 1), 301 PIN_FIELD_BASE(10, 10, 5, 0x30, 0x10, 8, 1), 302 PIN_FIELD_BASE(11, 11, 5, 0x30, 0x10, 10, 1), 303 PIN_FIELD_BASE(12, 12, 5, 0x30, 0x10, 7, 1), 304 PIN_FIELD_BASE(13, 13, 5, 0x30, 0x10, 11, 1), 305 306 PIN_FIELD_BASE(14, 14, 4, 0x30, 0x10, 8, 1), 307 308 PIN_FIELD_BASE(15, 15, 2, 0x30, 0x10, 0, 1), 309 PIN_FIELD_BASE(16, 16, 2, 0x30, 0x10, 1, 1), 310 PIN_FIELD_BASE(17, 17, 2, 0x30, 0x10, 5, 1), 311 PIN_FIELD_BASE(18, 18, 2, 0x30, 0x10, 4, 1), 312 PIN_FIELD_BASE(19, 19, 2, 0x30, 0x10, 2, 1), 313 PIN_FIELD_BASE(20, 20, 2, 0x90, 0x10, 3, 1), 314 PIN_FIELD_BASE(21, 21, 2, 0x30, 0x10, 6, 1), 315 PIN_FIELD_BASE(22, 22, 2, 0x30, 0x10, 7, 1), 316 PIN_FIELD_BASE(23, 23, 2, 0x30, 0x10, 10, 1), 317 PIN_FIELD_BASE(24, 24, 2, 0x30, 0x10, 9, 1), 318 PIN_FIELD_BASE(25, 25, 2, 0x30, 0x10, 8, 1), 319 320 PIN_FIELD_BASE(26, 26, 5, 0x30, 0x10, 0, 1), 321 PIN_FIELD_BASE(27, 27, 5, 0x30, 0x10, 4, 1), 322 PIN_FIELD_BASE(28, 28, 5, 0x30, 0x10, 3, 1), 323 PIN_FIELD_BASE(29, 29, 5, 0x30, 0x10, 1, 1), 324 PIN_FIELD_BASE(30, 30, 5, 0x30, 0x10, 2, 1), 325 PIN_FIELD_BASE(31, 31, 5, 0x30, 0x10, 5, 1), 326 327 PIN_FIELD_BASE(32, 32, 1, 0x20, 0x10, 2, 1), 328 PIN_FIELD_BASE(33, 33, 1, 0x20, 0x10, 3, 1), 329 330 PIN_FIELD_BASE(34, 34, 4, 0x30, 0x10, 5, 1), 331 PIN_FIELD_BASE(35, 35, 4, 0x30, 0x10, 7, 1), 332 333 PIN_FIELD_BASE(36, 36, 3, 0x20, 0x10, 2, 1), 334 PIN_FIELD_BASE(37, 37, 3, 0x20, 0x10, 3, 1), 335 PIN_FIELD_BASE(38, 38, 3, 0x20, 0x10, 0, 1), 336 PIN_FIELD_BASE(39, 39, 3, 0x20, 0x10, 1, 1), 337}; 338 339static const struct mtk_pin_field_calc mt7981_pin_r0_range[] = { 340 PIN_FIELD_BASE(0, 0, 1, 0x30, 0x10, 1, 1), 341 PIN_FIELD_BASE(1, 1, 1, 0x30, 0x10, 0, 1), 342 PIN_FIELD_BASE(2, 2, 5, 0x40, 0x10, 6, 1), 343 PIN_FIELD_BASE(3, 3, 4, 0x40, 0x10, 6, 1), 344 PIN_FIELD_BASE(4, 4, 4, 0x40, 0x10, 2, 1), 345 PIN_FIELD_BASE(5, 5, 4, 0x40, 0x10, 1, 1), 346 PIN_FIELD_BASE(6, 6, 4, 0x40, 0x10, 3, 1), 347 PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 0, 1), 348 PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1), 349 350 PIN_FIELD_BASE(9, 9, 5, 0x40, 0x10, 9, 1), 351 PIN_FIELD_BASE(10, 10, 5, 0x40, 0x10, 8, 1), 352 PIN_FIELD_BASE(11, 11, 5, 0x40, 0x10, 10, 1), 353 PIN_FIELD_BASE(12, 12, 5, 0x40, 0x10, 7, 1), 354 PIN_FIELD_BASE(13, 13, 5, 0x40, 0x10, 11, 1), 355 356 PIN_FIELD_BASE(14, 14, 4, 0x40, 0x10, 8, 1), 357 358 PIN_FIELD_BASE(15, 15, 2, 0x40, 0x10, 0, 1), 359 PIN_FIELD_BASE(16, 16, 2, 0x40, 0x10, 1, 1), 360 PIN_FIELD_BASE(17, 17, 2, 0x40, 0x10, 5, 1), 361 PIN_FIELD_BASE(18, 18, 2, 0x40, 0x10, 4, 1), 362 PIN_FIELD_BASE(19, 19, 2, 0x40, 0x10, 2, 1), 363 PIN_FIELD_BASE(20, 20, 2, 0x40, 0x10, 3, 1), 364 PIN_FIELD_BASE(21, 21, 2, 0x40, 0x10, 6, 1), 365 PIN_FIELD_BASE(22, 22, 2, 0x40, 0x10, 7, 1), 366 PIN_FIELD_BASE(23, 23, 2, 0x40, 0x10, 10, 1), 367 PIN_FIELD_BASE(24, 24, 2, 0x40, 0x10, 9, 1), 368 PIN_FIELD_BASE(25, 25, 2, 0x40, 0x10, 8, 1), 369 370 PIN_FIELD_BASE(26, 26, 5, 0x40, 0x10, 0, 1), 371 PIN_FIELD_BASE(27, 27, 5, 0x40, 0x10, 4, 1), 372 PIN_FIELD_BASE(28, 28, 5, 0x40, 0x10, 3, 1), 373 PIN_FIELD_BASE(29, 29, 5, 0x40, 0x10, 1, 1), 374 PIN_FIELD_BASE(30, 30, 5, 0x40, 0x10, 2, 1), 375 PIN_FIELD_BASE(31, 31, 5, 0x40, 0x10, 5, 1), 376 377 PIN_FIELD_BASE(32, 32, 1, 0x30, 0x10, 2, 1), 378 PIN_FIELD_BASE(33, 33, 1, 0x30, 0x10, 3, 1), 379 380 PIN_FIELD_BASE(34, 34, 4, 0x40, 0x10, 5, 1), 381 PIN_FIELD_BASE(35, 35, 4, 0x40, 0x10, 7, 1), 382 383 PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 2, 1), 384 PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 3, 1), 385 PIN_FIELD_BASE(38, 38, 3, 0x30, 0x10, 0, 1), 386 PIN_FIELD_BASE(39, 39, 3, 0x30, 0x10, 1, 1), 387}; 388 389static const struct mtk_pin_field_calc mt7981_pin_r1_range[] = { 390 PIN_FIELD_BASE(0, 0, 1, 0x40, 0x10, 1, 1), 391 PIN_FIELD_BASE(1, 1, 1, 0x40, 0x10, 0, 1), 392 PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 6, 1), 393 PIN_FIELD_BASE(3, 3, 4, 0x50, 0x10, 6, 1), 394 PIN_FIELD_BASE(4, 4, 4, 0x50, 0x10, 2, 1), 395 PIN_FIELD_BASE(5, 5, 4, 0x50, 0x10, 1, 1), 396 PIN_FIELD_BASE(6, 6, 4, 0x50, 0x10, 3, 1), 397 PIN_FIELD_BASE(7, 7, 4, 0x50, 0x10, 0, 1), 398 PIN_FIELD_BASE(8, 8, 4, 0x50, 0x10, 4, 1), 399 400 PIN_FIELD_BASE(9, 9, 5, 0x50, 0x10, 9, 1), 401 PIN_FIELD_BASE(10, 10, 5, 0x50, 0x10, 8, 1), 402 PIN_FIELD_BASE(11, 11, 5, 0x50, 0x10, 10, 1), 403 PIN_FIELD_BASE(12, 12, 5, 0x50, 0x10, 7, 1), 404 PIN_FIELD_BASE(13, 13, 5, 0x50, 0x10, 11, 1), 405 406 PIN_FIELD_BASE(14, 14, 4, 0x50, 0x10, 8, 1), 407 408 PIN_FIELD_BASE(15, 15, 2, 0x50, 0x10, 0, 1), 409 PIN_FIELD_BASE(16, 16, 2, 0x50, 0x10, 1, 1), 410 PIN_FIELD_BASE(17, 17, 2, 0x50, 0x10, 5, 1), 411 PIN_FIELD_BASE(18, 18, 2, 0x50, 0x10, 4, 1), 412 PIN_FIELD_BASE(19, 19, 2, 0x50, 0x10, 2, 1), 413 PIN_FIELD_BASE(20, 20, 2, 0x50, 0x10, 3, 1), 414 PIN_FIELD_BASE(21, 21, 2, 0x50, 0x10, 6, 1), 415 PIN_FIELD_BASE(22, 22, 2, 0x50, 0x10, 7, 1), 416 PIN_FIELD_BASE(23, 23, 2, 0x50, 0x10, 10, 1), 417 PIN_FIELD_BASE(24, 24, 2, 0x50, 0x10, 9, 1), 418 PIN_FIELD_BASE(25, 25, 2, 0x50, 0x10, 8, 1), 419 420 PIN_FIELD_BASE(26, 26, 5, 0x50, 0x10, 0, 1), 421 PIN_FIELD_BASE(27, 27, 5, 0x50, 0x10, 4, 1), 422 PIN_FIELD_BASE(28, 28, 5, 0x50, 0x10, 3, 1), 423 PIN_FIELD_BASE(29, 29, 5, 0x50, 0x10, 1, 1), 424 PIN_FIELD_BASE(30, 30, 5, 0x50, 0x10, 2, 1), 425 PIN_FIELD_BASE(31, 31, 5, 0x50, 0x10, 5, 1), 426 427 PIN_FIELD_BASE(32, 32, 1, 0x40, 0x10, 2, 1), 428 PIN_FIELD_BASE(33, 33, 1, 0x40, 0x10, 3, 1), 429 430 PIN_FIELD_BASE(34, 34, 4, 0x50, 0x10, 5, 1), 431 PIN_FIELD_BASE(35, 35, 4, 0x50, 0x10, 7, 1), 432 433 PIN_FIELD_BASE(36, 36, 3, 0x40, 0x10, 2, 1), 434 PIN_FIELD_BASE(37, 37, 3, 0x40, 0x10, 3, 1), 435 PIN_FIELD_BASE(38, 38, 3, 0x40, 0x10, 0, 1), 436 PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1), 437}; 438 439static const unsigned int mt7981_pull_type[] = { 440 MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ 441 MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ 442 MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ 443 MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/ 444 MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/ 445 MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ 446 MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/ 447 MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/ 448 MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/ 449 MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ 450 MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ 451 MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ 452 MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ 453 MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ 454 MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ 455 MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ 456 MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ 457 MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ 458 MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ 459 MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ 460 MTK_PULL_PU_PD_TYPE,/*40*/ MTK_PULL_PU_PD_TYPE,/*41*/ 461 MTK_PULL_PU_PD_TYPE,/*42*/ MTK_PULL_PU_PD_TYPE,/*43*/ 462 MTK_PULL_PU_PD_TYPE,/*44*/ MTK_PULL_PU_PD_TYPE,/*45*/ 463 MTK_PULL_PU_PD_TYPE,/*46*/ MTK_PULL_PU_PD_TYPE,/*47*/ 464 MTK_PULL_PU_PD_TYPE,/*48*/ MTK_PULL_PU_PD_TYPE,/*49*/ 465 MTK_PULL_PU_PD_TYPE,/*50*/ MTK_PULL_PU_PD_TYPE,/*51*/ 466 MTK_PULL_PU_PD_TYPE,/*52*/ MTK_PULL_PU_PD_TYPE,/*53*/ 467 MTK_PULL_PU_PD_TYPE,/*54*/ MTK_PULL_PU_PD_TYPE,/*55*/ 468 MTK_PULL_PU_PD_TYPE,/*56*/ 469}; 470 471static const struct mtk_pin_reg_calc mt7981_reg_cals[] = { 472 [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range), 473 [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range), 474 [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range), 475 [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7981_pin_do_range), 476 [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7981_pin_smt_range), 477 [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7981_pin_ies_range), 478 [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7981_pin_pu_range), 479 [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7981_pin_pd_range), 480 [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7981_pin_drv_range), 481 [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7981_pin_pupd_range), 482 [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7981_pin_r0_range), 483 [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7981_pin_r1_range), 484}; 485 486static const struct mtk_pin_desc mt7981_pins[] = { 487 MT7981_PIN(0, "GPIO_WPS"), 488 MT7981_PIN(1, "GPIO_RESET"), 489 MT7981_PIN(2, "SYS_WATCHDOG"), 490 MT7981_PIN(3, "PCIE_PERESET_N"), 491 MT7981_PIN(4, "JTAG_JTDO"), 492 MT7981_PIN(5, "JTAG_JTDI"), 493 MT7981_PIN(6, "JTAG_JTMS"), 494 MT7981_PIN(7, "JTAG_JTCLK"), 495 MT7981_PIN(8, "JTAG_JTRST_N"), 496 MT7981_PIN(9, "WO_JTAG_JTDO"), 497 MT7981_PIN(10, "WO_JTAG_JTDI"), 498 MT7981_PIN(11, "WO_JTAG_JTMS"), 499 MT7981_PIN(12, "WO_JTAG_JTCLK"), 500 MT7981_PIN(13, "WO_JTAG_JTRST_N"), 501 MT7981_PIN(14, "USB_VBUS"), 502 MT7981_PIN(15, "PWM0"), 503 MT7981_PIN(16, "SPI0_CLK"), 504 MT7981_PIN(17, "SPI0_MOSI"), 505 MT7981_PIN(18, "SPI0_MISO"), 506 MT7981_PIN(19, "SPI0_CS"), 507 MT7981_PIN(20, "SPI0_HOLD"), 508 MT7981_PIN(21, "SPI0_WP"), 509 MT7981_PIN(22, "SPI1_CLK"), 510 MT7981_PIN(23, "SPI1_MOSI"), 511 MT7981_PIN(24, "SPI1_MISO"), 512 MT7981_PIN(25, "SPI1_CS"), 513 MT7981_PIN(26, "SPI2_CLK"), 514 MT7981_PIN(27, "SPI2_MOSI"), 515 MT7981_PIN(28, "SPI2_MISO"), 516 MT7981_PIN(29, "SPI2_CS"), 517 MT7981_PIN(30, "SPI2_HOLD"), 518 MT7981_PIN(31, "SPI2_WP"), 519 MT7981_PIN(32, "UART0_RXD"), 520 MT7981_PIN(33, "UART0_TXD"), 521 MT7981_PIN(34, "PCIE_CLK_REQ"), 522 MT7981_PIN(35, "PCIE_WAKE_N"), 523 MT7981_PIN(36, "SMI_MDC"), 524 MT7981_PIN(37, "SMI_MDIO"), 525 MT7981_PIN(38, "GBE_INT"), 526 MT7981_PIN(39, "GBE_RESET"), 527 MT7981_PIN(40, "WF_DIG_RESETB"), 528 MT7981_PIN(41, "WF_CBA_RESETB"), 529 MT7981_PIN(42, "WF_XO_REQ"), 530 MT7981_PIN(43, "WF_TOP_CLK"), 531 MT7981_PIN(44, "WF_TOP_DATA"), 532 MT7981_PIN(45, "WF_HB1"), 533 MT7981_PIN(46, "WF_HB2"), 534 MT7981_PIN(47, "WF_HB3"), 535 MT7981_PIN(48, "WF_HB4"), 536 MT7981_PIN(49, "WF_HB0"), 537 MT7981_PIN(50, "WF_HB0_B"), 538 MT7981_PIN(51, "WF_HB5"), 539 MT7981_PIN(52, "WF_HB6"), 540 MT7981_PIN(53, "WF_HB7"), 541 MT7981_PIN(54, "WF_HB8"), 542 MT7981_PIN(55, "WF_HB9"), 543 MT7981_PIN(56, "WF_HB10"), 544}; 545 546/* List all groups consisting of these pins dedicated to the enablement of 547 * certain hardware block and the corresponding mode for all of the pins. 548 * The hardware probably has multiple combinations of these pinouts. 549 */ 550 551/* WA_AICE */ 552static int mt7981_wa_aice1_pins[] = { 0, 1, }; 553static int mt7981_wa_aice1_funcs[] = { 2, 2, }; 554 555static int mt7981_wa_aice2_pins[] = { 0, 1, }; 556static int mt7981_wa_aice2_funcs[] = { 3, 3, }; 557 558static int mt7981_wa_aice3_pins[] = { 28, 29, }; 559static int mt7981_wa_aice3_funcs[] = { 3, 3, }; 560 561static int mt7981_wm_aice1_pins[] = { 9, 10, }; 562static int mt7981_wm_aice1_funcs[] = { 2, 2, }; 563 564static int mt7981_wm_aice2_pins[] = { 30, 31, }; 565static int mt7981_wm_aice2_funcs[] = { 5, 5, }; 566 567/* WM_UART */ 568static int mt7981_wm_uart_0_pins[] = { 0, 1, }; 569static int mt7981_wm_uart_0_funcs[] = { 5, 5, }; 570 571static int mt7981_wm_uart_1_pins[] = { 20, 21, }; 572static int mt7981_wm_uart_1_funcs[] = { 4, 4, }; 573 574static int mt7981_wm_uart_2_pins[] = { 30, 31, }; 575static int mt7981_wm_uart_2_funcs[] = { 3, 3, }; 576 577/* DFD */ 578static int mt7981_dfd_pins[] = { 0, 1, 4, 5, }; 579static int mt7981_dfd_funcs[] = { 5, 5, 6, 6, }; 580 581/* SYS_WATCHDOG */ 582static int mt7981_watchdog_pins[] = { 2, }; 583static int mt7981_watchdog_funcs[] = { 1, }; 584 585static int mt7981_watchdog1_pins[] = { 13, }; 586static int mt7981_watchdog1_funcs[] = { 5, }; 587 588/* PCIE_PERESET_N */ 589static int mt7981_pcie_pereset_pins[] = { 3, }; 590static int mt7981_pcie_pereset_funcs[] = { 1, }; 591 592/* JTAG */ 593static int mt7981_jtag_pins[] = { 4, 5, 6, 7, 8, }; 594static int mt7981_jtag_funcs[] = { 1, 1, 1, 1, 1, }; 595 596/* WM_JTAG */ 597static int mt7981_wm_jtag_0_pins[] = { 4, 5, 6, 7, 8, }; 598static int mt7981_wm_jtag_0_funcs[] = { 2, 2, 2, 2, 2, }; 599 600static int mt7981_wm_jtag_1_pins[] = { 20, 21, 22, 23, 24, }; 601static int mt7981_wm_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; 602 603/* WO0_JTAG */ 604static int mt7981_wo0_jtag_0_pins[] = { 9, 10, 11, 12, 13, }; 605static int mt7981_wo0_jtag_0_funcs[] = { 1, 1, 1, 1, 1, }; 606 607static int mt7981_wo0_jtag_1_pins[] = { 25, 26, 27, 28, 29, }; 608static int mt7981_wo0_jtag_1_funcs[] = { 5, 5, 5, 5, 5, }; 609 610/* UART2 */ 611static int mt7981_uart2_0_pins[] = { 4, 5, 6, 7, }; 612static int mt7981_uart2_0_funcs[] = { 3, 3, 3, 3, }; 613 614static int mt7981_uart2_0_tx_rx_pins[] = { 4, 5, }; 615static int mt7981_uart2_0_tx_rx_funcs[] = { 3, 3, }; 616 617/* GBE_LED0 */ 618static int mt7981_gbe_led0_pins[] = { 8, }; 619static int mt7981_gbe_led0_funcs[] = { 3, }; 620 621/* PTA_EXT */ 622static int mt7981_pta_ext_0_pins[] = { 4, 5, 6, }; 623static int mt7981_pta_ext_0_funcs[] = { 4, 4, 4, }; 624 625static int mt7981_pta_ext_1_pins[] = { 22, 23, 24, }; 626static int mt7981_pta_ext_1_funcs[] = { 4, 4, 4, }; 627 628/* PWM2 */ 629static int mt7981_pwm2_pins[] = { 7, }; 630static int mt7981_pwm2_funcs[] = { 4, }; 631 632/* NET_WO0_UART_TXD */ 633static int mt7981_net_wo0_uart_txd_0_pins[] = { 8, }; 634static int mt7981_net_wo0_uart_txd_0_funcs[] = { 4, }; 635 636static int mt7981_net_wo0_uart_txd_1_pins[] = { 14, }; 637static int mt7981_net_wo0_uart_txd_1_funcs[] = { 3, }; 638 639static int mt7981_net_wo0_uart_txd_2_pins[] = { 15, }; 640static int mt7981_net_wo0_uart_txd_2_funcs[] = { 4, }; 641 642/* SPI1 */ 643static int mt7981_spi1_0_pins[] = { 4, 5, 6, 7, }; 644static int mt7981_spi1_0_funcs[] = { 5, 5, 5, 5, }; 645 646/* I2C */ 647static int mt7981_i2c0_0_pins[] = { 6, 7, }; 648static int mt7981_i2c0_0_funcs[] = { 6, 6, }; 649 650static int mt7981_i2c0_1_pins[] = { 30, 31, }; 651static int mt7981_i2c0_1_funcs[] = { 4, 4, }; 652 653static int mt7981_i2c0_2_pins[] = { 36, 37, }; 654static int mt7981_i2c0_2_funcs[] = { 2, 2, }; 655 656static int mt7981_u2_phy_i2c_pins[] = { 30, 31, }; 657static int mt7981_u2_phy_i2c_funcs[] = { 6, 6, }; 658 659static int mt7981_u3_phy_i2c_pins[] = { 32, 33, }; 660static int mt7981_u3_phy_i2c_funcs[] = { 3, 3, }; 661 662static int mt7981_sgmii1_phy_i2c_pins[] = { 32, 33, }; 663static int mt7981_sgmii1_phy_i2c_funcs[] = { 2, 2, }; 664 665static int mt7981_sgmii0_phy_i2c_pins[] = { 32, 33, }; 666static int mt7981_sgmii0_phy_i2c_funcs[] = { 5, 5, }; 667 668/* DFD_NTRST */ 669static int mt7981_dfd_ntrst_pins[] = { 8, }; 670static int mt7981_dfd_ntrst_funcs[] = { 6, }; 671 672/* PWM0 */ 673static int mt7981_pwm0_0_pins[] = { 13, }; 674static int mt7981_pwm0_0_funcs[] = { 2, }; 675 676static int mt7981_pwm0_1_pins[] = { 15, }; 677static int mt7981_pwm0_1_funcs[] = { 1, }; 678 679/* PWM1 */ 680static int mt7981_pwm1_0_pins[] = { 14, }; 681static int mt7981_pwm1_0_funcs[] = { 2, }; 682 683static int mt7981_pwm1_1_pins[] = { 15, }; 684static int mt7981_pwm1_1_funcs[] = { 3, }; 685 686/* GBE_LED1 */ 687static int mt7981_gbe_led1_pins[] = { 13, }; 688static int mt7981_gbe_led1_funcs[] = { 3, }; 689 690/* PCM */ 691static int mt7981_pcm_pins[] = { 9, 10, 11, 12, 13, 25 }; 692static int mt7981_pcm_funcs[] = { 4, 4, 4, 4, 4, 4, }; 693 694/* UDI */ 695static int mt7981_udi_pins[] = { 9, 10, 11, 12, 13, }; 696static int mt7981_udi_funcs[] = { 6, 6, 6, 6, 6, }; 697 698/* DRV_VBUS */ 699static int mt7981_drv_vbus_pins[] = { 14, }; 700static int mt7981_drv_vbus_funcs[] = { 1, }; 701 702/* EMMC */ 703static int mt7981_emmc_reset_pins[] = { 15, }; 704static int mt7981_emmc_reset_funcs[] = { 2, }; 705 706static int mt7981_emmc_4_pins[] = { 16, 17, 18, 19, 24, 25, }; 707static int mt7981_emmc_4_funcs[] = { 2, 2, 2, 2, 2, 2, }; 708 709static int mt7981_emmc_8_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; 710static int mt7981_emmc_8_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; 711 712static int mt7981_emmc_45_pins[] = { 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, }; 713static int mt7981_emmc_45_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; 714 715/* SNFI */ 716static int mt7981_snfi_pins[] = { 16, 17, 18, 19, 20, 21, }; 717static int mt7981_snfi_funcs[] = { 3, 3, 3, 3, 3, 3, }; 718 719/* SPI0 */ 720static int mt7981_spi0_pins[] = { 16, 17, 18, 19, }; 721static int mt7981_spi0_funcs[] = { 1, 1, 1, 1, }; 722 723/* SPI0 */ 724static int mt7981_spi0_wp_hold_pins[] = { 20, 21, }; 725static int mt7981_spi0_wp_hold_funcs[] = { 1, 1, }; 726 727/* SPI1 */ 728static int mt7981_spi1_1_pins[] = { 22, 23, 24, 25, }; 729static int mt7981_spi1_1_funcs[] = { 1, 1, 1, 1, }; 730 731/* SPI2 */ 732static int mt7981_spi2_pins[] = { 26, 27, 28, 29, }; 733static int mt7981_spi2_funcs[] = { 1, 1, 1, 1, }; 734 735/* SPI2 */ 736static int mt7981_spi2_wp_hold_pins[] = { 30, 31, }; 737static int mt7981_spi2_wp_hold_funcs[] = { 1, 1, }; 738 739/* UART1 */ 740static int mt7981_uart1_0_pins[] = { 16, 17, 18, 19, }; 741static int mt7981_uart1_0_funcs[] = { 4, 4, 4, 4, }; 742 743static int mt7981_uart1_1_pins[] = { 26, 27, 28, 29, }; 744static int mt7981_uart1_1_funcs[] = { 2, 2, 2, 2, }; 745 746static int mt7981_uart1_2_pins[] = { 9, 10, }; 747static int mt7981_uart1_2_funcs[] = { 2, 2, }; 748 749static int mt7981_uart1_3_pins[] = { 26, 27, }; 750static int mt7981_uart1_3_funcs[] = { 2, 2, }; 751 752/* UART2 */ 753static int mt7981_uart2_1_pins[] = { 22, 23, 24, 25, }; 754static int mt7981_uart2_1_funcs[] = { 3, 3, 3, 3, }; 755 756/* UART0 */ 757static int mt7981_uart0_pins[] = { 32, 33, }; 758static int mt7981_uart0_funcs[] = { 1, 1, }; 759 760/* PCIE_CLK_REQ */ 761static int mt7981_pcie_clk_pins[] = { 34, }; 762static int mt7981_pcie_clk_funcs[] = { 2, }; 763 764/* PCIE_WAKE_N */ 765static int mt7981_pcie_wake_pins[] = { 35, }; 766static int mt7981_pcie_wake_funcs[] = { 2, }; 767 768/* MDC_MDIO */ 769static int mt7981_smi_mdc_mdio_pins[] = { 36, 37, }; 770static int mt7981_smi_mdc_mdio_funcs[] = { 1, 1, }; 771 772static int mt7981_gbe_ext_mdc_mdio_pins[] = { 36, 37, }; 773static int mt7981_gbe_ext_mdc_mdio_funcs[] = { 3, 3, }; 774 775/* WF0_MODE1 */ 776static int mt7981_wf0_mode1_pins[] = { 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56 }; 777static int mt7981_wf0_mode1_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; 778 779/* WF0_MODE3 */ 780static int mt7981_wf0_mode3_pins[] = { 45, 46, 47, 48, 49, 51 }; 781static int mt7981_wf0_mode3_funcs[] = { 2, 2, 2, 2, 2, 2 }; 782 783/* WF2G_LED */ 784static int mt7981_wf2g_led0_pins[] = { 30, }; 785static int mt7981_wf2g_led0_funcs[] = { 2, }; 786 787static int mt7981_wf2g_led1_pins[] = { 34, }; 788static int mt7981_wf2g_led1_funcs[] = { 1, }; 789 790/* WF5G_LED */ 791static int mt7981_wf5g_led0_pins[] = { 31, }; 792static int mt7981_wf5g_led0_funcs[] = { 2, }; 793 794static int mt7981_wf5g_led1_pins[] = { 35, }; 795static int mt7981_wf5g_led1_funcs[] = { 1, }; 796 797/* MT7531_INT */ 798static int mt7981_mt7531_int_pins[] = { 38, }; 799static int mt7981_mt7531_int_funcs[] = { 1, }; 800 801/* ANT_SEL */ 802static int mt7981_ant_sel_pins[] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 34, 35 }; 803static int mt7981_ant_sel_funcs[] = { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 }; 804 805static const struct group_desc mt7981_groups[] = { 806 /* @GPIO(0,1): WA_AICE(2) */ 807 PINCTRL_PIN_GROUP("wa_aice1", mt7981_wa_aice1), 808 /* @GPIO(0,1): WA_AICE(3) */ 809 PINCTRL_PIN_GROUP("wa_aice2", mt7981_wa_aice2), 810 /* @GPIO(0,1): WM_UART(5) */ 811 PINCTRL_PIN_GROUP("wm_uart_0", mt7981_wm_uart_0), 812 /* @GPIO(0,1,4,5): DFD(6) */ 813 PINCTRL_PIN_GROUP("dfd", mt7981_dfd), 814 /* @GPIO(2): SYS_WATCHDOG(1) */ 815 PINCTRL_PIN_GROUP("watchdog", mt7981_watchdog), 816 /* @GPIO(3): PCIE_PERESET_N(1) */ 817 PINCTRL_PIN_GROUP("pcie_pereset", mt7981_pcie_pereset), 818 /* @GPIO(4,8) JTAG(1) */ 819 PINCTRL_PIN_GROUP("jtag", mt7981_jtag), 820 /* @GPIO(4,8) WM_JTAG(2) */ 821 PINCTRL_PIN_GROUP("wm_jtag_0", mt7981_wm_jtag_0), 822 /* @GPIO(9,13) WO0_JTAG(1) */ 823 PINCTRL_PIN_GROUP("wo0_jtag_0", mt7981_wo0_jtag_0), 824 /* @GPIO(4,7) WM_JTAG(3) */ 825 PINCTRL_PIN_GROUP("uart2_0", mt7981_uart2_0), 826 /* @GPIO(4,5) WM_JTAG(4) */ 827 PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7981_uart2_0_tx_rx), 828 /* @GPIO(8) GBE_LED0(3) */ 829 PINCTRL_PIN_GROUP("gbe_led0", mt7981_gbe_led0), 830 /* @GPIO(4,6) PTA_EXT(4) */ 831 PINCTRL_PIN_GROUP("pta_ext_0", mt7981_pta_ext_0), 832 /* @GPIO(7) PWM2(4) */ 833 PINCTRL_PIN_GROUP("pwm2", mt7981_pwm2), 834 /* @GPIO(8) NET_WO0_UART_TXD(4) */ 835 PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7981_net_wo0_uart_txd_0), 836 /* @GPIO(4,7) SPI1(5) */ 837 PINCTRL_PIN_GROUP("spi1_0", mt7981_spi1_0), 838 /* @GPIO(6,7) I2C(5) */ 839 PINCTRL_PIN_GROUP("i2c0_0", mt7981_i2c0_0), 840 /* @GPIO(0,1,4,5): DFD_NTRST(6) */ 841 PINCTRL_PIN_GROUP("dfd_ntrst", mt7981_dfd_ntrst), 842 /* @GPIO(9,10): WM_AICE(2) */ 843 PINCTRL_PIN_GROUP("wm_aice1", mt7981_wm_aice1), 844 /* @GPIO(13): PWM0(2) */ 845 PINCTRL_PIN_GROUP("pwm0_0", mt7981_pwm0_0), 846 /* @GPIO(15): PWM0(1) */ 847 PINCTRL_PIN_GROUP("pwm0_1", mt7981_pwm0_1), 848 /* @GPIO(14): PWM1(2) */ 849 PINCTRL_PIN_GROUP("pwm1_0", mt7981_pwm1_0), 850 /* @GPIO(15): PWM1(3) */ 851 PINCTRL_PIN_GROUP("pwm1_1", mt7981_pwm1_1), 852 /* @GPIO(14) NET_WO0_UART_TXD(3) */ 853 PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7981_net_wo0_uart_txd_1), 854 /* @GPIO(15) NET_WO0_UART_TXD(4) */ 855 PINCTRL_PIN_GROUP("net_wo0_uart_txd_2", mt7981_net_wo0_uart_txd_2), 856 /* @GPIO(13) GBE_LED0(3) */ 857 PINCTRL_PIN_GROUP("gbe_led1", mt7981_gbe_led1), 858 /* @GPIO(9,13) PCM(4) */ 859 PINCTRL_PIN_GROUP("pcm", mt7981_pcm), 860 /* @GPIO(13): SYS_WATCHDOG1(5) */ 861 PINCTRL_PIN_GROUP("watchdog1", mt7981_watchdog1), 862 /* @GPIO(9,13) UDI(4) */ 863 PINCTRL_PIN_GROUP("udi", mt7981_udi), 864 /* @GPIO(14) DRV_VBUS(1) */ 865 PINCTRL_PIN_GROUP("drv_vbus", mt7981_drv_vbus), 866 /* @GPIO(15): EMMC_RSTB(2) */ 867 PINCTRL_PIN_GROUP("emmc_reset", mt7981_emmc_reset), 868 /* @GPIO(16,17,18,19,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */ 869 PINCTRL_PIN_GROUP("emmc_4", mt7981_emmc_4), 870 /* @GPIO(16,17,18,19,20,21,22,23,24,25): EMMC_DATx, EMMC_CLK, EMMC_CMD */ 871 PINCTRL_PIN_GROUP("emmc_8", mt7981_emmc_8), 872 /* @GPIO(15,25): EMMC(2) */ 873 PINCTRL_PIN_GROUP("emmc_45", mt7981_emmc_45), 874 /* @GPIO(16,21): SNFI(3) */ 875 PINCTRL_PIN_GROUP("snfi", mt7981_snfi), 876 /* @GPIO(16,19): SPI0(1) */ 877 PINCTRL_PIN_GROUP("spi0", mt7981_spi0), 878 /* @GPIO(20,21): SPI0(1) */ 879 PINCTRL_PIN_GROUP("spi0_wp_hold", mt7981_spi0_wp_hold), 880 /* @GPIO(22,25) SPI1(1) */ 881 PINCTRL_PIN_GROUP("spi1_1", mt7981_spi1_1), 882 /* @GPIO(26,29): SPI2(1) */ 883 PINCTRL_PIN_GROUP("spi2", mt7981_spi2), 884 /* @GPIO(30,31): SPI0(1) */ 885 PINCTRL_PIN_GROUP("spi2_wp_hold", mt7981_spi2_wp_hold), 886 /* @GPIO(16,19): UART1(4) */ 887 PINCTRL_PIN_GROUP("uart1_0", mt7981_uart1_0), 888 /* @GPIO(26,29): UART1(2) */ 889 PINCTRL_PIN_GROUP("uart1_1", mt7981_uart1_1), 890 /* @GPIO(9,10): UART1(2) */ 891 PINCTRL_PIN_GROUP("uart1_2", mt7981_uart1_2), 892 /* @GPIO(26,27): UART1(2) */ 893 PINCTRL_PIN_GROUP("uart1_3", mt7981_uart1_3), 894 /* @GPIO(22,25): UART1(3) */ 895 PINCTRL_PIN_GROUP("uart2_1", mt7981_uart2_1), 896 /* @GPIO(22,24) PTA_EXT(4) */ 897 PINCTRL_PIN_GROUP("pta_ext_1", mt7981_pta_ext_1), 898 /* @GPIO(20,21): WM_UART(4) */ 899 PINCTRL_PIN_GROUP("wm_aurt_1", mt7981_wm_uart_1), 900 /* @GPIO(30,31): WM_UART(3) */ 901 PINCTRL_PIN_GROUP("wm_aurt_2", mt7981_wm_uart_2), 902 /* @GPIO(20,24) WM_JTAG(5) */ 903 PINCTRL_PIN_GROUP("wm_jtag_1", mt7981_wm_jtag_1), 904 /* @GPIO(25,29) WO0_JTAG(5) */ 905 PINCTRL_PIN_GROUP("wo0_jtag_1", mt7981_wo0_jtag_1), 906 /* @GPIO(28,29): WA_AICE(3) */ 907 PINCTRL_PIN_GROUP("wa_aice3", mt7981_wa_aice3), 908 /* @GPIO(30,31): WM_AICE(5) */ 909 PINCTRL_PIN_GROUP("wm_aice2", mt7981_wm_aice2), 910 /* @GPIO(30,31): I2C(4) */ 911 PINCTRL_PIN_GROUP("i2c0_1", mt7981_i2c0_1), 912 /* @GPIO(30,31): I2C(6) */ 913 PINCTRL_PIN_GROUP("u2_phy_i2c", mt7981_u2_phy_i2c), 914 /* @GPIO(32,33): I2C(1) */ 915 PINCTRL_PIN_GROUP("uart0", mt7981_uart0), 916 /* @GPIO(32,33): I2C(2) */ 917 PINCTRL_PIN_GROUP("sgmii1_phy_i2c", mt7981_sgmii1_phy_i2c), 918 /* @GPIO(32,33): I2C(3) */ 919 PINCTRL_PIN_GROUP("u3_phy_i2c", mt7981_u3_phy_i2c), 920 /* @GPIO(32,33): I2C(5) */ 921 PINCTRL_PIN_GROUP("sgmii0_phy_i2c", mt7981_sgmii0_phy_i2c), 922 /* @GPIO(34): PCIE_CLK_REQ(2) */ 923 PINCTRL_PIN_GROUP("pcie_clk", mt7981_pcie_clk), 924 /* @GPIO(35): PCIE_WAKE_N(2) */ 925 PINCTRL_PIN_GROUP("pcie_wake", mt7981_pcie_wake), 926 /* @GPIO(36,37): I2C(2) */ 927 PINCTRL_PIN_GROUP("i2c0_2", mt7981_i2c0_2), 928 /* @GPIO(36,37): MDC_MDIO(1) */ 929 PINCTRL_PIN_GROUP("smi_mdc_mdio", mt7981_smi_mdc_mdio), 930 /* @GPIO(36,37): MDC_MDIO(3) */ 931 PINCTRL_PIN_GROUP("gbe_ext_mdc_mdio", mt7981_gbe_ext_mdc_mdio), 932 /* @GPIO(69,85): WF0_MODE1(1) */ 933 PINCTRL_PIN_GROUP("wf0_mode1", mt7981_wf0_mode1), 934 /* @GPIO(74,80): WF0_MODE3(3) */ 935 PINCTRL_PIN_GROUP("wf0_mode3", mt7981_wf0_mode3), 936 /* @GPIO(30): WF2G_LED(2) */ 937 PINCTRL_PIN_GROUP("wf2g_led0", mt7981_wf2g_led0), 938 /* @GPIO(34): WF2G_LED(1) */ 939 PINCTRL_PIN_GROUP("wf2g_led1", mt7981_wf2g_led1), 940 /* @GPIO(31): WF5G_LED(2) */ 941 PINCTRL_PIN_GROUP("wf5g_led0", mt7981_wf5g_led0), 942 /* @GPIO(35): WF5G_LED(1) */ 943 PINCTRL_PIN_GROUP("wf5g_led1", mt7981_wf5g_led1), 944 /* @GPIO(38): MT7531_INT(1) */ 945 PINCTRL_PIN_GROUP("mt7531_int", mt7981_mt7531_int), 946 /* @GPIO(14,15,26,17,18,19,20,21,22,23,24,25,34,35): ANT_SEL(1) */ 947 PINCTRL_PIN_GROUP("ant_sel", mt7981_ant_sel), 948}; 949 950/* Joint those groups owning the same capability in user point of view which 951 * allows that people tend to use through the device tree. 952 */ 953static const char *mt7981_wa_aice_groups[] = { "wa_aice1", "wa_aice2", "wm_aice1_1", 954 "wa_aice3", "wm_aice1_2", }; 955static const char *mt7981_uart_groups[] = { "net_wo0_uart_txd_0", "net_wo0_uart_txd_1", 956 "net_wo0_uart_txd_2", "uart0", "uart1_0", "uart1_1", "uart1_2", "uart1_3", "uart2_0", 957 "uart2_0_tx_rx", "uart2_1", "wm_uart_0", "wm_aurt_1", "wm_aurt_2", }; 958static const char *mt7981_dfd_groups[] = { "dfd", "dfd_ntrst", }; 959static const char *mt7981_wdt_groups[] = { "watchdog", "watchdog1", }; 960static const char *mt7981_pcie_groups[] = { "pcie_pereset", "pcie_clk", "pcie_wake", }; 961static const char *mt7981_jtag_groups[] = { "jtag", "wm_jtag_0", "wo0_jtag_0", 962 "wo0_jtag_1", "wm_jtag_1", }; 963static const char *mt7981_led_groups[] = { "gbe_led0", "gbe_led1", "wf2g_led0", 964 "wf2g_led1", "wf5g_led0", "wf5g_led1", }; 965static const char *mt7981_pta_groups[] = { "pta_ext_0", "pta_ext_1", }; 966static const char *mt7981_pwm_groups[] = { "pwm2", "pwm0_0", "pwm0_1", 967 "pwm1_0", "pwm1_1", }; 968static const char *mt7981_spi_groups[] = { "spi1_0", "spi0", "spi0_wp_hold", "spi1_1", "spi2", 969 "spi2_wp_hold", }; 970static const char *mt7981_i2c_groups[] = { "i2c0_0", "i2c0_1", "u2_phy_i2c", 971 "sgmii1_phy_i2c", "u3_phy_i2c", "sgmii0_phy_i2c", "i2c0_2", }; 972static const char *mt7981_pcm_groups[] = { "pcm", }; 973static const char *mt7981_udi_groups[] = { "udi", }; 974static const char *mt7981_usb_groups[] = { "drv_vbus", }; 975static const char *mt7981_flash_groups[] = { "emmc_reset", "emmc_4", "emmc_8", "emmc_45", "snfi", }; 976static const char *mt7981_ethernet_groups[] = { "smi_mdc_mdio", "gbe_ext_mdc_mdio", 977 "wf0_mode1", "wf0_mode3", "mt7531_int", }; 978static const char *mt7981_ant_groups[] = { "ant_sel", }; 979 980static const struct function_desc mt7981_functions[] = { 981 {"wa_aice", mt7981_wa_aice_groups, ARRAY_SIZE(mt7981_wa_aice_groups)}, 982 {"dfd", mt7981_dfd_groups, ARRAY_SIZE(mt7981_dfd_groups)}, 983 {"jtag", mt7981_jtag_groups, ARRAY_SIZE(mt7981_jtag_groups)}, 984 {"pta", mt7981_pta_groups, ARRAY_SIZE(mt7981_pta_groups)}, 985 {"pcm", mt7981_pcm_groups, ARRAY_SIZE(mt7981_pcm_groups)}, 986 {"udi", mt7981_udi_groups, ARRAY_SIZE(mt7981_udi_groups)}, 987 {"usb", mt7981_usb_groups, ARRAY_SIZE(mt7981_usb_groups)}, 988 {"ant", mt7981_ant_groups, ARRAY_SIZE(mt7981_ant_groups)}, 989 {"eth", mt7981_ethernet_groups, ARRAY_SIZE(mt7981_ethernet_groups)}, 990 {"i2c", mt7981_i2c_groups, ARRAY_SIZE(mt7981_i2c_groups)}, 991 {"led", mt7981_led_groups, ARRAY_SIZE(mt7981_led_groups)}, 992 {"pwm", mt7981_pwm_groups, ARRAY_SIZE(mt7981_pwm_groups)}, 993 {"spi", mt7981_spi_groups, ARRAY_SIZE(mt7981_spi_groups)}, 994 {"uart", mt7981_uart_groups, ARRAY_SIZE(mt7981_uart_groups)}, 995 {"watchdog", mt7981_wdt_groups, ARRAY_SIZE(mt7981_wdt_groups)}, 996 {"flash", mt7981_flash_groups, ARRAY_SIZE(mt7981_flash_groups)}, 997 {"pcie", mt7981_pcie_groups, ARRAY_SIZE(mt7981_pcie_groups)}, 998}; 999 1000static const struct mtk_eint_hw mt7981_eint_hw = { 1001 .port_mask = 7, 1002 .ports = 7, 1003 .ap_num = ARRAY_SIZE(mt7981_pins), 1004 .db_cnt = 16, 1005}; 1006 1007static const char * const mt7981_pinctrl_register_base_names[] = { 1008 "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", 1009 "iocfg_lb", "iocfg_bl", "iocfg_tm", "iocfg_tl", 1010}; 1011 1012static struct mtk_pin_soc mt7981_data = { 1013 .reg_cal = mt7981_reg_cals, 1014 .pins = mt7981_pins, 1015 .npins = ARRAY_SIZE(mt7981_pins), 1016 .grps = mt7981_groups, 1017 .ngrps = ARRAY_SIZE(mt7981_groups), 1018 .funcs = mt7981_functions, 1019 .nfuncs = ARRAY_SIZE(mt7981_functions), 1020 .eint_hw = &mt7981_eint_hw, 1021 .gpio_m = 0, 1022 .ies_present = false, 1023 .base_names = mt7981_pinctrl_register_base_names, 1024 .nbase_names = ARRAY_SIZE(mt7981_pinctrl_register_base_names), 1025 .bias_disable_set = mtk_pinconf_bias_disable_set, 1026 .bias_disable_get = mtk_pinconf_bias_disable_get, 1027 .bias_set = mtk_pinconf_bias_set, 1028 .bias_get = mtk_pinconf_bias_get, 1029 .pull_type = mt7981_pull_type, 1030 .bias_set_combo = mtk_pinconf_bias_set_combo, 1031 .bias_get_combo = mtk_pinconf_bias_get_combo, 1032 .drive_set = mtk_pinconf_drive_set_rev1, 1033 .drive_get = mtk_pinconf_drive_get_rev1, 1034 .adv_pull_get = mtk_pinconf_adv_pull_get, 1035 .adv_pull_set = mtk_pinconf_adv_pull_set, 1036}; 1037 1038static const struct of_device_id mt7981_pinctrl_of_match[] = { 1039 { .compatible = "mediatek,mt7981-pinctrl", }, 1040 {} 1041}; 1042 1043static int mt7981_pinctrl_probe(struct platform_device *pdev) 1044{ 1045 return mtk_moore_pinctrl_probe(pdev, &mt7981_data); 1046} 1047 1048static struct platform_driver mt7981_pinctrl_driver = { 1049 .driver = { 1050 .name = "mt7981-pinctrl", 1051 .of_match_table = mt7981_pinctrl_of_match, 1052 }, 1053 .probe = mt7981_pinctrl_probe, 1054}; 1055 1056static int __init mt7981_pinctrl_init(void) 1057{ 1058 return platform_driver_register(&mt7981_pinctrl_driver); 1059} 1060arch_initcall(mt7981_pinctrl_init); 1061