Searched refs:x1 (Results 76 - 100 of 5701) sorted by relevance

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/linux-master/scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/
H A Dmvebu-icu.h12 #define ICU_GRP_SR 0x1
/linux-master/drivers/ipack/devices/
H A Dscc2698.h86 #define MR1_CHRL_6_BITS (0x1 << 0)
89 #define MR1_PARITY_EVEN (0x1 << 2)
92 #define MR1_PARITY_FORCE (0x1 << 3)
96 #define MR1_ERROR_BLOCK (0x1 << 5)
98 #define MR1_RxINT_FFULL (0x1 << 6)
99 #define MR1_RxRTS_CONTROL_ON (0x1 << 7)
104 #define MR2_CTS_ENABLE_TX_ON (0x1 << 4)
106 #define MR2_TxRTS_CONTROL_ON (0x1 << 5)
109 #define MR2_CH_MODE_ECHO (0x1 << 6)
113 #define CR_ENABLE_RX (0x1 <<
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/linux-master/drivers/gpu/drm/amd/include/asic_reg/pwr/
H A Dpwr_10_0_sh_mask.h26 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
/linux-master/include/uapi/linux/netfilter/
H A Dxt_NFLOG.h7 #define XT_NFLOG_DEFAULT_GROUP 0x1
10 #define XT_NFLOG_MASK 0x1
13 #define XT_NFLOG_F_COPY_LEN 0x1
/linux-master/sound/soc/codecs/
H A Dda7213.h153 #define DA7213_SWITCH_EN_MAX 0x1
156 #define DA7213_PLL_SRM_LOCK (0x1 << 1)
159 #define DA7213_SR_8000 (0x1 << 0)
172 #define DA7213_BIAS_EN (0x1 << 3)
173 #define DA7213_VMID_EN (0x1 << 7)
177 #define DA7213_PLL_INDIV_9_TO_18_MHZ (0x1 << 2)
181 #define DA7213_PLL_MCLK_SQR_EN (0x1 << 4)
182 #define DA7213_PLL_32K_MODE (0x1 << 5)
183 #define DA7213_PLL_SRM_EN (0x1 << 6)
184 #define DA7213_PLL_EN (0x1 <<
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H A Drt5663.h223 #define RT5663_EN_DAC_HPO_MASK (0x1 << 14)
226 #define RT5663_EN_DAC_HPO_EN (0x1 << 14)
237 #define RT5663_IN1_DF_MASK (0x1 << 15)
241 #define RT5663_CBJ_DET_MASK (0x1 << 15)
244 #define RT5663_CBJ_DET_EN (0x1 << 15)
245 #define RT5663_DET_TYPE_MASK (0x1 << 12)
248 #define RT5663_DET_TYPE_QFN (0x1 << 12)
249 #define RT5663_VREF_BIAS_MASK (0x1 << 6)
252 #define RT5663_VREF_BIAS_REG (0x1 << 6)
255 #define RT5663_RECMIX1L_BST1_CBJ (0x1 <<
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H A Drt1019.h40 #define RT1019_AUTO_BITS_SEL_MASK (0x1 << 5)
41 #define RT1019_AUTO_BITS_SEL_AUTO (0x1 << 5)
43 #define RT1019_AUTO_CLK_SEL_MASK (0x1 << 4)
44 #define RT1019_AUTO_CLK_SEL_AUTO (0x1 << 4)
48 #define RT1019_CLK_SYS_PRE_SEL_MASK (0x1 << 7)
51 #define RT1019_CLK_SYS_PRE_SEL_PLL (0x1 << 7)
52 #define RT1019_PLL_SRC_MASK (0x1 << 4)
55 #define RT1019_PLL_SRC_SEL_RC (0x1 << 4)
58 #define RT1019_SEL_FIFO_DIV2 (0x1 << 2)
68 #define RT1019_SYS_DA_OSR_DIV2 (0x1 <<
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H A Drt1015.h188 #define RT1015_PLL_SEL_MASK (0x1 << 13)
191 #define RT1015_PLL_SEL_BCLK (0x1 << 13)
199 #define RT1015_PLL_M_BP (0x1 << 11)
206 #define RT1015_PLL_BPK_MASK (0x1 << 5)
213 #define RT1015_EN_BCLK_DET_MASK (0x1 << 15)
214 #define RT1015_EN_BCLK_DET (0x1 << 15)
220 #define RT1015_ID_VERB 0x1
225 #define RT1015_MONO_R_CHANNEL (0x1 << 4)
233 #define RT1015_DAC_CLK (0x1 << 13)
237 #define RT1015_DAC_MUTE_MASK (0x1 << 1
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H A Drt1011.h307 #define RT1011_FS_SYS_PRE_BCLK (0x1 << 14)
310 #define RT1011_PLL1_SRC_MASK (0x1 << 13)
313 #define RT1011_PLL1_SRC_BCLK (0x1 << 13)
314 #define RT1011_PLL2_SRC_MASK (0x1 << 12)
317 #define RT1011_PLL2_SRC_RCCLK (0x1 << 12)
328 #define RT1011_PLL1_BPM_MASK (0x1 << 11)
330 #define RT1011_PLL1_BPM (0x1 << 11)
335 #define RT1011_PLL2_BPK_MASK (0x1 << 5)
337 #define RT1011_PLL2_BPK (0x1 << 5)
342 #define RT1011_EN_MCLK_DET_MASK (0x1 << 1
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H A Dda7219.h125 #define DA7219_SWITCH_EN_MAX 0x1
162 #define DA7219_I2C_TIMEOUT_EN_MASK (0x1 << 0)
166 #define DA7219_CIF_I2C_WRITE_MODE_MASK (0x1 << 0)
168 #define DA7219_CIF_REG_SOFT_RESET_MASK (0x1 << 7)
172 #define DA7219_SR_24_48_MASK (0x1 << 0)
197 #define DA7219_PLL_INDIV_4_5_TO_9_MHZ (0x1 << 2)
202 #define DA7219_PLL_MCLK_SQR_EN_MASK (0x1 << 5)
206 #define DA7219_PLL_MODE_NORMAL (0x1 << 6)
226 #define DA7219_PLL_SRM_STS_MCLK (0x1 << 4)
227 #define DA7219_PLL_SRM_STS_SRM_LOCK (0x1 <<
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/linux-master/arch/arm64/kvm/hyp/
H A Dentry.S26 // x1-x17: clobbered by macros
29 adr_this_cpu x1, kvm_hyp_ctxt, x2
32 save_callee_saved_regs x1
35 save_sp_el0 x1, x2
45 mrs x1, isr_el1
46 cbz x1, 1f
51 set_loaded_vcpu x0, x1, x2
56 mte_switch_to_guest x29, x1, x2
63 ptrauth_switch_to_guest x29, x0, x1, x2
69 ldp x0, x1, [x2
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/linux-master/drivers/extcon/
H A Dextcon-sm5502.h86 #define SM5502_REG_CONTROL_MASK_INT_MASK (0x1 << SM5502_REG_CONTROL_MASK_INT_SHIFT)
87 #define SM5502_REG_CONTROL_WAIT_MASK (0x1 << SM5502_REG_CONTROL_WAIT_SHIFT)
88 #define SM5502_REG_CONTROL_MANUAL_SW_MASK (0x1 << SM5502_REG_CONTROL_MANUAL_SW_SHIFT)
89 #define SM5502_REG_CONTROL_RAW_DATA_MASK (0x1 << SM5502_REG_CONTROL_RAW_DATA_SHIFT)
90 #define SM5502_REG_CONTROL_SW_OPEN_MASK (0x1 << SM5502_REG_CONTROL_SW_OPEN_SHIFT)
95 #define SM5504_REG_CONTROL_CHGTYP_MASK (0x1 << SM5504_REG_CONTROL_CHGTYP_SHIFT)
96 #define SM5504_REG_CONTROL_USBCHDEN_MASK (0x1 << SM5504_REG_CONTROL_USBCHDEN_SHIFT)
97 #define SM5504_REG_CONTROL_ADC_EN_MASK (0x1 << SM5504_REG_CONTROL_ADC_EN_SHIFT)
107 #define SM5502_REG_INTM1_ATTACH_MASK (0x1 << SM5502_REG_INTM1_ATTACH_SHIFT)
108 #define SM5502_REG_INTM1_DETACH_MASK (0x1 << SM5502_REG_INTM1_DETACH_SHIF
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/linux-master/drivers/soc/samsung/
H A Dexynos5420-pmu.c42 { EXYNOS5_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
43 { EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
44 { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
49 { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
50 { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} },
51 { EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} },
52 { EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} },
53 { EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1,
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/linux-master/drivers/pinctrl/sunxi/
H A Dpinctrl-sun8i-a23.c27 SUNXI_FUNCTION(0x1, "gpio_out"),
33 SUNXI_FUNCTION(0x1, "gpio_out"),
39 SUNXI_FUNCTION(0x1, "gpio_out"),
45 SUNXI_FUNCTION(0x1, "gpio_out"),
51 SUNXI_FUNCTION(0x1, "gpio_out"),
56 SUNXI_FUNCTION(0x1, "gpio_out"),
61 SUNXI_FUNCTION(0x1, "gpio_out"),
66 SUNXI_FUNCTION(0x1, "gpio_out"),
72 SUNXI_FUNCTION(0x1, "gpio_out"),
77 SUNXI_FUNCTION(0x1, "gpio_ou
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H A Dpinctrl-sun8i-a83t.c26 SUNXI_FUNCTION(0x1, "gpio_out"),
32 SUNXI_FUNCTION(0x1, "gpio_out"),
38 SUNXI_FUNCTION(0x1, "gpio_out"),
44 SUNXI_FUNCTION(0x1, "gpio_out"),
50 SUNXI_FUNCTION(0x1, "gpio_out"),
56 SUNXI_FUNCTION(0x1, "gpio_out"),
62 SUNXI_FUNCTION(0x1, "gpio_out"),
68 SUNXI_FUNCTION(0x1, "gpio_out"),
74 SUNXI_FUNCTION(0x1, "gpio_out"),
80 SUNXI_FUNCTION(0x1, "gpio_ou
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H A Dpinctrl-sun6i-a31.c23 SUNXI_FUNCTION(0x1, "gpio_out"),
31 SUNXI_FUNCTION(0x1, "gpio_out"),
39 SUNXI_FUNCTION(0x1, "gpio_out"),
47 SUNXI_FUNCTION(0x1, "gpio_out"),
55 SUNXI_FUNCTION(0x1, "gpio_out"),
63 SUNXI_FUNCTION(0x1, "gpio_out"),
71 SUNXI_FUNCTION(0x1, "gpio_out"),
79 SUNXI_FUNCTION(0x1, "gpio_out"),
87 SUNXI_FUNCTION(0x1, "gpio_out"),
94 SUNXI_FUNCTION(0x1, "gpio_ou
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H A Dpinctrl-sun50i-a64.c25 SUNXI_FUNCTION(0x1, "gpio_out"),
31 SUNXI_FUNCTION(0x1, "gpio_out"),
38 SUNXI_FUNCTION(0x1, "gpio_out"),
45 SUNXI_FUNCTION(0x1, "gpio_out"),
53 SUNXI_FUNCTION(0x1, "gpio_out"),
60 SUNXI_FUNCTION(0x1, "gpio_out"),
67 SUNXI_FUNCTION(0x1, "gpio_out"),
74 SUNXI_FUNCTION(0x1, "gpio_out"),
81 SUNXI_FUNCTION(0x1, "gpio_out"),
86 SUNXI_FUNCTION(0x1, "gpio_ou
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/linux-master/drivers/net/ethernet/qlogic/qed/
H A Dqed_hsi.h322 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1
324 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1
326 #define CORE_TX_BD_DATA_START_BD_MASK 0x1
328 #define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1
330 #define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1
332 #define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1
334 #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1
336 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1
340 #define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1
342 #define CORE_TX_BD_DATA_IP_LEN_MASK 0x1
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/linux-master/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dpsoc_global_conf_masks.h28 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1
32 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1
52 #define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_MASK 0x1
56 #define PSOC_GLOBAL_CONF_PRSTN_VAL_MASK 0x1
60 #define PSOC_GLOBAL_CONF_PCIE_EN_MASK_MASK 0x1
64 #define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_MASK 0x1
68 #define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_MASK 0x1
78 #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_MASK 0x1
98 #define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_MASK 0x1
102 #define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_MASK 0x1
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/linux-master/drivers/net/ethernet/intel/iavf/
H A Diavf_register.h14 #define IAVF_VF_ARQLEN1_ARQVFE_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQVFE_SHIFT)
16 #define IAVF_VF_ARQLEN1_ARQOVFL_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQOVFL_SHIFT)
18 #define IAVF_VF_ARQLEN1_ARQCRIT_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQCRIT_SHIFT)
20 #define IAVF_VF_ARQLEN1_ARQENABLE_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQENABLE_SHIFT)
27 #define IAVF_VF_ATQLEN1_ATQVFE_MASK IAVF_MASK(0x1, IAVF_VF_ATQLEN1_ATQVFE_SHIFT)
29 #define IAVF_VF_ATQLEN1_ATQOVFL_MASK IAVF_MASK(0x1, IAVF_VF_ATQLEN1_ATQOVFL_SHIFT)
31 #define IAVF_VF_ATQLEN1_ATQCRIT_MASK IAVF_MASK(0x1, IAVF_VF_ATQLEN1_ATQCRIT_SHIFT)
33 #define IAVF_VF_ATQLEN1_ATQENABLE_MASK IAVF_MASK(0x1, IAVF_VF_ATQLEN1_ATQENABLE_SHIFT)
40 #define IAVF_VFINT_DYN_CTL01_INTENA_MASK IAVF_MASK(0x1, IAVF_VFINT_DYN_CTL01_INTENA_SHIFT)
45 #define IAVF_VFINT_DYN_CTLN1_INTENA_MASK IAVF_MASK(0x1, IAVF_VFINT_DYN_CTLN1_INTENA_SHIF
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/linux-master/sound/soc/mediatek/mt2701/
H A Dmt2701-reg.h94 #define AFE_DAIBT_CON0_DAIBT_EN (0x1 << 0)
95 #define AFE_DAIBT_CON0_BT_FUNC_EN (0x1 << 1)
96 #define AFE_DAIBT_CON0_BT_FUNC_RDY (0x1 << 3)
97 #define AFE_DAIBT_CON0_BT_WIDE_MODE_EN (0x1 << 9)
98 #define AFE_DAIBT_CON0_MRG_USE (0x1 << 12)
104 #define AFE_MRGIF_CON_MRG_EN (0x1 << 0)
105 #define AFE_MRGIF_CON_MRG_I2S_EN (0x1 << 16)
116 #define AFE_DAC_CON0_AFE_ON (0x1 << 0)
119 #define AFE_MEMIF_PBUF_SIZE_DLM_MASK (0x1 << 29)
121 #define AFE_MEMIF_PBUF_SIZE_FULL_INTERLEAVE (0x1 << 2
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/linux-master/sound/ppc/
H A Dawacs.h37 #define MASK_CNTLERR (0x1 << 11) /* Error */
38 #define MASK_PORTCHG (0x1 << 12) /* Port Change */
39 #define MASK_IEE (0x1 << 13) /* Enable Interrupt on Error */
40 #define MASK_IEPC (0x1 << 14) /* Enable Interrupt on Port Change */
45 #define MASK_NEWECMD (0x1 << 24) /* Lock: don't write to reg when 1 */
56 #define MASK_ADDR1 (0x1 << 12) /* Expanded Data Mode Address 1 */
77 #define MASK_GAINLINE (0x1 << 8) /* Disable Mic preamp */
79 #define MASK_MUX_CD (0x1 << 9) /* Select CD in MUX */
80 #define MASK_MUX_MIC (0x1 << 10) /* Select Mic in MUX */
81 #define MASK_MUX_AUDIN (0x1 << 1
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/linux-master/sound/soc/mediatek/mt8192/
H A Dmt8192-afe-clk.h45 #define APLL12_DIV0_PDN_MASK 0x1
46 #define APLL12_DIV0_PDN_MASK_SFT (0x1 << 0)
48 #define APLL12_DIV1_PDN_MASK 0x1
49 #define APLL12_DIV1_PDN_MASK_SFT (0x1 << 1)
51 #define APLL12_DIV2_PDN_MASK 0x1
52 #define APLL12_DIV2_PDN_MASK_SFT (0x1 << 2)
54 #define APLL12_DIV3_PDN_MASK 0x1
55 #define APLL12_DIV3_PDN_MASK_SFT (0x1 << 3)
57 #define APLL12_DIV4_PDN_MASK 0x1
58 #define APLL12_DIV4_PDN_MASK_SFT (0x1 <<
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/linux-master/drivers/pinctrl/berlin/
H A Dberlin-bg2q.c22 BERLIN_PINCTRL_FUNCTION(0x1, "mmc"),
37 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
45 BERLIN_PINCTRL_FUNCTION(0x1, "sd0"),
52 BERLIN_PINCTRL_FUNCTION(0x1, "twsi0"),
56 BERLIN_PINCTRL_FUNCTION(0x1, "twsi1"),
61 BERLIN_PINCTRL_FUNCTION(0x1, "gpio")),
64 BERLIN_PINCTRL_FUNCTION(0x1, "gpio"),
68 BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS2n */
74 BERLIN_PINCTRL_FUNCTION(0x1, "spi1"), /* SS3n */
81 BERLIN_PINCTRL_FUNCTION(0x1, "gpi
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/linux-master/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_2_enum.h29 CRTC_CONTROL_CRTC_START_POINT_CNTL_DP = 0x1,
33 CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP = 0x1,
37 CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT= 0x1,
43 CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE = 0x1,
47 CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE = 0x1,
51 CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE = 0x1,
55 CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE = 0x1,
59 CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE = 0x1,
63 CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE = 0x1,
67 CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE= 0x1,
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