11590Srgrimes// SPDX-License-Identifier: GPL-2.0 2221807Sstas// 31590Srgrimes// rt1015.h -- RT1015 ALSA SoC audio amplifier driver 41590Srgrimes// 51590Srgrimes// Copyright 2019 Realtek Semiconductor Corp. 61590Srgrimes// Author: Jack Yu <jack.yu@realtek.com> 71590Srgrimes// 81590Srgrimes// This program is free software; you can redistribute it and/or modify 91590Srgrimes// it under the terms of the GNU General Public License version 2 as 101590Srgrimes// published by the Free Software Foundation. 111590Srgrimes// 121590Srgrimes 131590Srgrimes#ifndef __RT1015_H__ 141590Srgrimes#define __RT1015_H__ 151590Srgrimes#include <sound/rt1015.h> 161590Srgrimes 171590Srgrimes#define RT1015_DEVICE_ID_VAL 0x1011 181590Srgrimes#define RT1015_DEVICE_ID_VAL2 0x1015 191590Srgrimes 201590Srgrimes#define RT1015_RESET 0x0000 211590Srgrimes#define RT1015_CLK2 0x0004 221590Srgrimes#define RT1015_CLK3 0x0006 231590Srgrimes#define RT1015_PLL1 0x000a 241590Srgrimes#define RT1015_PLL2 0x000c 251590Srgrimes#define RT1015_DUM_RW1 0x000e 261590Srgrimes#define RT1015_DUM_RW2 0x0010 271590Srgrimes#define RT1015_DUM_RW3 0x0012 281590Srgrimes#define RT1015_DUM_RW4 0x0014 291590Srgrimes#define RT1015_DUM_RW5 0x0016 301590Srgrimes#define RT1015_DUM_RW6 0x0018 3199112Sobrien#define RT1015_CLK_DET 0x0020 3299112Sobrien#define RT1015_SIL_DET 0x0022 331590Srgrimes#define RT1015_CUSTOMER_ID 0x0076 341590Srgrimes#define RT1015_PCODE_FWVER 0x0078 351590Srgrimes#define RT1015_VER_ID 0x007a 361590Srgrimes#define RT1015_VENDOR_ID 0x007c 371590Srgrimes#define RT1015_DEVICE_ID 0x007d 381590Srgrimes#define RT1015_PAD_DRV1 0x00f0 391590Srgrimes#define RT1015_PAD_DRV2 0x00f2 407726Sdg#define RT1015_GAT_BOOST 0x00f3 411590Srgrimes#define RT1015_PRO_ALT 0x00f4 421590Srgrimes#define RT1015_OSCK_STA 0x00f6 431590Srgrimes#define RT1015_MAN_I2C 0x0100 44221807Sstas#define RT1015_DAC1 0x0102 451590Srgrimes#define RT1015_DAC2 0x0104 4627272Scharnier#define RT1015_DAC3 0x0106 47221807Sstas#define RT1015_ADC1 0x010c 4823693Speter#define RT1015_ADC2 0x010e 491590Srgrimes#define RT1015_TDM_MASTER 0x0111 50221816Simp#define RT1015_TDM_TCON 0x0112 511590Srgrimes#define RT1015_TDM1_1 0x0114 521590Srgrimes#define RT1015_TDM1_2 0x0116 53179828Skib#define RT1015_TDM1_3 0x0118 541590Srgrimes#define RT1015_TDM1_4 0x011a 5523693Speter#define RT1015_TDM1_5 0x011c 5648463Sru#define RT1015_MIXER1 0x0300 571590Srgrimes#define RT1015_MIXER2 0x0302 58221807Sstas#define RT1015_ANA_PROTECT1 0x0311 5958125Sgreen#define RT1015_ANA_CTRL_SEQ1 0x0313 60227239Sed#define RT1015_ANA_CTRL_SEQ2 0x0314 61227239Sed#define RT1015_VBAT_DET_DEB 0x031a 62227239Sed#define RT1015_VBAT_VOLT_DET1 0x031c 63227239Sed#define RT1015_VBAT_VOLT_DET2 0x031d 64227239Sed#define RT1015_VBAT_TEST_OUT1 0x031e 65227239Sed#define RT1015_VBAT_TEST_OUT2 0x031f 66227239Sed#define RT1015_VBAT_PROT_ATT 0x0320 671590Srgrimes#define RT1015_VBAT_DET_CODE 0x0321 68221807Sstas#define RT1015_PWR1 0x0322 69221807Sstas#define RT1015_PWR4 0x0328 70221807Sstas#define RT1015_PWR5 0x0329 71221807Sstas#define RT1015_PWR6 0x032a 72221807Sstas#define RT1015_PWR7 0x032b 73221807Sstas#define RT1015_PWR8 0x032c 741590Srgrimes#define RT1015_PWR9 0x032d 75227239Sed#define RT1015_CLASSD_SEQ 0x032e 76227239Sed#define RT1015_SMART_BST_CTRL1 0x0330 771590Srgrimes#define RT1015_SMART_BST_CTRL2 0x0332 78221807Sstas#define RT1015_ANA_CTRL1 0x0334 79221807Sstas#define RT1015_ANA_CTRL2 0x0336 80221807Sstas#define RT1015_PWR_STATE_CTRL 0x0338 81221807Sstas#define RT1015_MONO_DYNA_CTRL 0x04fa 82221807Sstas#define RT1015_MONO_DYNA_CTRL1 0x04fc 83221807Sstas#define RT1015_MONO_DYNA_CTRL2 0x04fe 84221807Sstas#define RT1015_MONO_DYNA_CTRL3 0x0500 85221807Sstas#define RT1015_MONO_DYNA_CTRL4 0x0502 86221807Sstas#define RT1015_MONO_DYNA_CTRL5 0x0504 87250223Sjhb#define RT1015_SPK_VOL 0x0506 88250223Sjhb#define RT1015_SHORT_DETTOP1 0x0508 89233760Sjhb#define RT1015_SHORT_DETTOP2 0x050a 90233760Sjhb#define RT1015_SPK_DC_DETECT1 0x0519 91221807Sstas#define RT1015_SPK_DC_DETECT2 0x051a 92221807Sstas#define RT1015_SPK_DC_DETECT3 0x051b 93221807Sstas#define RT1015_SPK_DC_DETECT4 0x051d 94221807Sstas#define RT1015_SPK_DC_DETECT5 0x051f 95221807Sstas#define RT1015_BAT_RPO_STEP1 0x0536 961590Srgrimes#define RT1015_BAT_RPO_STEP2 0x0538 9717808Speter#define RT1015_BAT_RPO_STEP3 0x053a 98221807Sstas#define RT1015_BAT_RPO_STEP4 0x053c 991590Srgrimes#define RT1015_BAT_RPO_STEP5 0x053d 100221807Sstas#define RT1015_BAT_RPO_STEP6 0x053e 10193427Sdwmalone#define RT1015_BAT_RPO_STEP7 0x053f 102221807Sstas#define RT1015_BAT_RPO_STEP8 0x0540 1031590Srgrimes#define RT1015_BAT_RPO_STEP9 0x0541 104221807Sstas#define RT1015_BAT_RPO_STEP10 0x0542 1051590Srgrimes#define RT1015_BAT_RPO_STEP11 0x0543 1061590Srgrimes#define RT1015_BAT_RPO_STEP12 0x0544 107167367Semaste#define RT1015_SPREAD_SPEC1 0x0568 1081590Srgrimes#define RT1015_SPREAD_SPEC2 0x056a 10959029Sgreen#define RT1015_PAD_STATUS 0x1000 1101590Srgrimes#define RT1015_PADS_PULLING_CTRL1 0x1002 1111590Srgrimes#define RT1015_PADS_DRIVING 0x1006 1121590Srgrimes#define RT1015_SYS_RST1 0x1007 1131590Srgrimes#define RT1015_SYS_RST2 0x1009 1141590Srgrimes#define RT1015_SYS_GATING1 0x100a 1151590Srgrimes#define RT1015_TEST_MODE1 0x100c 1161590Srgrimes#define RT1015_TEST_MODE2 0x100d 1171590Srgrimes#define RT1015_TIMING_CTRL1 0x100e 1181590Srgrimes#define RT1015_PLL_INT 0x1010 1191590Srgrimes#define RT1015_TEST_OUT1 0x1020 12059029Sgreen#define RT1015_DC_CALIB_CLSD1 0x1200 12159029Sgreen#define RT1015_DC_CALIB_CLSD2 0x1202 12259029Sgreen#define RT1015_DC_CALIB_CLSD3 0x1204 1231590Srgrimes#define RT1015_DC_CALIB_CLSD4 0x1206 1241590Srgrimes#define RT1015_DC_CALIB_CLSD5 0x1208 1251590Srgrimes#define RT1015_DC_CALIB_CLSD6 0x120a 1261590Srgrimes#define RT1015_DC_CALIB_CLSD7 0x120c 1271590Srgrimes#define RT1015_DC_CALIB_CLSD8 0x120e 1281590Srgrimes#define RT1015_DC_CALIB_CLSD9 0x1210 1291590Srgrimes#define RT1015_DC_CALIB_CLSD10 0x1212 13027311Scharnier#define RT1015_CLSD_INTERNAL1 0x1300 1311590Srgrimes#define RT1015_CLSD_INTERNAL2 0x1302 1321590Srgrimes#define RT1015_CLSD_INTERNAL3 0x1304 1331590Srgrimes#define RT1015_CLSD_INTERNAL4 0x1305 1341590Srgrimes#define RT1015_CLSD_INTERNAL5 0x1306 1351590Srgrimes#define RT1015_CLSD_INTERNAL6 0x1308 1361590Srgrimes#define RT1015_CLSD_INTERNAL7 0x130a 1371590Srgrimes#define RT1015_CLSD_INTERNAL8 0x130c 1381590Srgrimes#define RT1015_CLSD_INTERNAL9 0x130e 13927272Scharnier#define RT1015_CLSD_OCP_CTRL 0x130f 14027272Scharnier#define RT1015_VREF_LV 0x1310 1411590Srgrimes#define RT1015_MBIAS1 0x1312 1421590Srgrimes#define RT1015_MBIAS2 0x1314 1431590Srgrimes#define RT1015_MBIAS3 0x1316 1441590Srgrimes#define RT1015_MBIAS4 0x1318 1451590Srgrimes#define RT1015_VREF_LV1 0x131a 1461590Srgrimes#define RT1015_S_BST_TIMING_INTER1 0x1322 1471590Srgrimes#define RT1015_S_BST_TIMING_INTER2 0x1323 1481590Srgrimes#define RT1015_S_BST_TIMING_INTER3 0x1324 1491590Srgrimes#define RT1015_S_BST_TIMING_INTER4 0x1325 1501590Srgrimes#define RT1015_S_BST_TIMING_INTER5 0x1326 1511590Srgrimes#define RT1015_S_BST_TIMING_INTER6 0x1327 1521590Srgrimes#define RT1015_S_BST_TIMING_INTER7 0x1328 1531590Srgrimes#define RT1015_S_BST_TIMING_INTER8 0x1329 1541590Srgrimes#define RT1015_S_BST_TIMING_INTER9 0x132a 1551590Srgrimes#define RT1015_S_BST_TIMING_INTER10 0x132b 1561590Srgrimes#define RT1015_S_BST_TIMING_INTER11 0x1330 157228992Suqs#define RT1015_S_BST_TIMING_INTER12 0x1331 1581590Srgrimes#define RT1015_S_BST_TIMING_INTER13 0x1332 1591590Srgrimes#define RT1015_S_BST_TIMING_INTER14 0x1333 1601590Srgrimes#define RT1015_S_BST_TIMING_INTER15 0x1334 1618874Srgrimes#define RT1015_S_BST_TIMING_INTER16 0x1335 1621590Srgrimes#define RT1015_S_BST_TIMING_INTER17 0x1336 1631590Srgrimes#define RT1015_S_BST_TIMING_INTER18 0x1337 1641590Srgrimes#define RT1015_S_BST_TIMING_INTER19 0x1338 1651590Srgrimes#define RT1015_S_BST_TIMING_INTER20 0x1339 1661590Srgrimes#define RT1015_S_BST_TIMING_INTER21 0x133a 1671590Srgrimes#define RT1015_S_BST_TIMING_INTER22 0x133b 16897946Sdes#define RT1015_S_BST_TIMING_INTER23 0x133c 169221807Sstas#define RT1015_S_BST_TIMING_INTER24 0x133d 17097946Sdes#define RT1015_S_BST_TIMING_INTER25 0x133e 171221807Sstas#define RT1015_S_BST_TIMING_INTER26 0x133f 172221807Sstas#define RT1015_S_BST_TIMING_INTER27 0x1340 173221807Sstas#define RT1015_S_BST_TIMING_INTER28 0x1341 174221807Sstas#define RT1015_S_BST_TIMING_INTER29 0x1342 175221807Sstas#define RT1015_S_BST_TIMING_INTER30 0x1343 176221807Sstas#define RT1015_S_BST_TIMING_INTER31 0x1344 17797946Sdes#define RT1015_S_BST_TIMING_INTER32 0x1345 178221807Sstas#define RT1015_S_BST_TIMING_INTER33 0x1346 179221807Sstas#define RT1015_S_BST_TIMING_INTER34 0x1347 180221807Sstas#define RT1015_S_BST_TIMING_INTER35 0x1348 18197946Sdes#define RT1015_S_BST_TIMING_INTER36 0x1349 18297946Sdes 18397946Sdes/* 0x0004 */ 18497946Sdes#define RT1015_CLK_SYS_PRE_SEL_MASK (0x3 << 14) 18597946Sdes#define RT1015_CLK_SYS_PRE_SEL_SFT 14 18697946Sdes#define RT1015_CLK_SYS_PRE_SEL_MCLK (0x0 << 14) 18797946Sdes#define RT1015_CLK_SYS_PRE_SEL_PLL (0x2 << 14) 18897946Sdes#define RT1015_PLL_SEL_MASK (0x1 << 13) 18997946Sdes#define RT1015_PLL_SEL_SFT 13 19097946Sdes#define RT1015_PLL_SEL_PLL_SRC2 (0x0 << 13) 19197946Sdes#define RT1015_PLL_SEL_BCLK (0x1 << 13) 1921590Srgrimes#define RT1015_FS_PD_MASK (0x7 << 4) 193221807Sstas#define RT1015_FS_PD_SFT 4 1941590Srgrimes 195221807Sstas/* 0x000a */ 196221807Sstas#define RT1015_PLL_M_MAX 0xf 1971590Srgrimes#define RT1015_PLL_M_MASK (RT1015_PLL_M_MAX << 12) 198221807Sstas#define RT1015_PLL_M_SFT 12 1991590Srgrimes#define RT1015_PLL_M_BP (0x1 << 11) 200221807Sstas#define RT1015_PLL_M_BP_SFT 11 201221807Sstas#define RT1015_PLL_N_MAX 0x1ff 202221807Sstas#define RT1015_PLL_N_MASK (RT1015_PLL_N_MAX << 0) 2031590Srgrimes#define RT1015_PLL_N_SFT 0 2041590Srgrimes 20597946Sdes/* 0x000c */ 206221807Sstas#define RT1015_PLL_BPK_MASK (0x1 << 5) 20797946Sdes#define RT1015_PLL_BPK (0x0 << 5) 208221807Sstas#define RT1015_PLL_K_MAX 0x1f 209221807Sstas#define RT1015_PLL_K_MASK (RT1015_PLL_K_MAX) 210221807Sstas#define RT1015_PLL_K_SFT 0 211221807Sstas 212221807Sstas/* 0x0020 */ 21397946Sdes#define RT1015_EN_BCLK_DET_MASK (0x1 << 15) 214221807Sstas#define RT1015_EN_BCLK_DET (0x1 << 15) 215221807Sstas#define RT1015_DIS_BCLK_DET (0x0 << 15) 216221807Sstas 21797946Sdes/* 0x007a */ 218221807Sstas#define RT1015_ID_MASK 0xff 219221807Sstas#define RT1015_ID_VERA 0x0 2201590Srgrimes#define RT1015_ID_VERB 0x1 221221807Sstas 222221807Sstas/* 0x00f2 */ 223221807Sstas#define RT1015_MONO_LR_SEL_MASK (0x3 << 4) 224221807Sstas#define RT1015_MONO_L_CHANNEL (0x0 << 4) 225140958Sphk#define RT1015_MONO_R_CHANNEL (0x1 << 4) 226140958Sphk#define RT1015_MONO_LR_MIX_CHANNEL (0x2 << 4) 227221807Sstas 228221807Sstas/* 0x0102 */ 229221807Sstas#define RT1015_DAC_VOL_MASK (0x7f << 9) 23059029Sgreen#define RT1015_DAC_VOL_SFT 9 231221807Sstas 232221807Sstas/* 0x0104 */ 233221807Sstas#define RT1015_DAC_CLK (0x1 << 13) 234221807Sstas#define RT1015_DAC_CLK_BIT 13 235221807Sstas 23659029Sgreen/* 0x0106 */ 237221807Sstas#define RT1015_DAC_MUTE_MASK (0x1 << 15) 238221807Sstas#define RT1015_DA_MUTE_SFT 15 239232233Spluknet#define RT1015_DVOL_MUTE_FLAG_SFT 12 240232233Spluknet 24159029Sgreen/* 0x0111 */ 242232233Spluknet#define RT1015_TCON_TDM_MS_MASK (0x1 << 14) 243221807Sstas#define RT1015_TCON_TDM_MS_SFT 14 244221807Sstas#define RT1015_TCON_TDM_MS_S (0x0 << 14) 24559029Sgreen#define RT1015_TCON_TDM_MS_M (0x1 << 14) 2461590Srgrimes#define RT1015_I2S_DL_MASK (0x7 << 8) 247232233Spluknet#define RT1015_I2S_DL_SFT 8 248232233Spluknet#define RT1015_I2S_DL_16 (0x0 << 8) 249235602Sgleb#define RT1015_I2S_DL_20 (0x1 << 8) 250232233Spluknet#define RT1015_I2S_DL_24 (0x2 << 8) 251232233Spluknet#define RT1015_I2S_DL_8 (0x3 << 8) 2521590Srgrimes#define RT1015_I2S_M_DF_MASK (0x7 << 0) 2531590Srgrimes#define RT1015_I2S_M_DF_SFT 0 2541590Srgrimes#define RT1015_I2S_M_DF_I2S (0x0) 2551590Srgrimes#define RT1015_I2S_M_DF_LEFT (0x1) 2561590Srgrimes#define RT1015_I2S_M_DF_PCM_A (0x2) 2571590Srgrimes#define RT1015_I2S_M_DF_PCM_B (0x3) 25853133Sgreen#define RT1015_I2S_M_DF_PCM_A_N (0x6) 259221807Sstas#define RT1015_I2S_M_DF_PCM_B_N (0x7) 26053133Sgreen 261221807Sstas/* TDM_tcon Setting (0x0112) */ 262221807Sstas#define RT1015_I2S_TCON_DF_MASK (0x7 << 13) 263221807Sstas#define RT1015_I2S_TCON_DF_SFT 13 264221807Sstas#define RT1015_I2S_TCON_DF_I2S (0x0 << 13) 265221807Sstas#define RT1015_I2S_TCON_DF_LEFT (0x1 << 13) 266221807Sstas#define RT1015_I2S_TCON_DF_PCM_A (0x2 << 13) 267221807Sstas#define RT1015_I2S_TCON_DF_PCM_B (0x3 << 13) 268221807Sstas#define RT1015_I2S_TCON_DF_PCM_A_N (0x6 << 13) 269221807Sstas#define RT1015_I2S_TCON_DF_PCM_B_N (0x7 << 13) 270221807Sstas#define RT1015_TCON_BCLK_SEL_MASK (0x3 << 10) 271221807Sstas#define RT1015_TCON_BCLK_SEL_SFT 10 272221807Sstas#define RT1015_TCON_BCLK_SEL_32FS (0x0 << 10) 273221807Sstas#define RT1015_TCON_BCLK_SEL_64FS (0x1 << 10) 274221807Sstas#define RT1015_TCON_BCLK_SEL_128FS (0x2 << 10) 275221807Sstas#define RT1015_TCON_BCLK_SEL_256FS (0x3 << 10) 276116780Sjmg#define RT1015_TCON_CH_LEN_MASK (0x3 << 5) 277221807Sstas#define RT1015_TCON_CH_LEN_SFT 5 2781590Srgrimes#define RT1015_TCON_CH_LEN_16B (0x0 << 5) 279221807Sstas#define RT1015_TCON_CH_LEN_20B (0x1 << 5) 280221807Sstas#define RT1015_TCON_CH_LEN_24B (0x2 << 5) 281221807Sstas#define RT1015_TCON_CH_LEN_32B (0x3 << 5) 282221807Sstas#define RT1015_TCON_BCLK_MST_MASK (0x1 << 4) 283221807Sstas#define RT1015_TCON_BCLK_MST_SFT 4 284221807Sstas#define RT1015_TCON_BCLK_MST_INV (0x1 << 4) 285221807Sstas 2861590Srgrimes/* TDM1 Setting-1 (0x0114) */ 287221807Sstas#define RT1015_TDM_INV_BCLK_MASK (0x1 << 15) 288221807Sstas#define RT1015_TDM_INV_BCLK_SFT 15 2891590Srgrimes#define RT1015_TDM_INV_BCLK (0x1 << 15) 290221807Sstas#define RT1015_I2S_CH_TX_MASK (0x3 << 10) 291221807Sstas#define RT1015_I2S_CH_TX_SFT 10 2921590Srgrimes#define RT1015_I2S_TX_2CH (0x0 << 10) 293221807Sstas#define RT1015_I2S_TX_4CH (0x1 << 10) 294221807Sstas#define RT1015_I2S_TX_6CH (0x2 << 10) 2951590Srgrimes#define RT1015_I2S_TX_8CH (0x3 << 10) 296233760Sjhb#define RT1015_I2S_CH_RX_MASK (0x3 << 8) 297233760Sjhb#define RT1015_I2S_CH_RX_SFT 8 298233760Sjhb#define RT1015_I2S_RX_2CH (0x0 << 8) 299250223Sjhb#define RT1015_I2S_RX_4CH (0x1 << 8) 300250223Sjhb#define RT1015_I2S_RX_6CH (0x2 << 8) 301250223Sjhb#define RT1015_I2S_RX_8CH (0x3 << 8) 302221807Sstas#define RT1015_I2S_LR_CH_SEL_MASK (0x1 << 7) 303221807Sstas#define RT1015_I2S_LR_CH_SEL_SFT 7 304221807Sstas#define RT1015_I2S_LEFT_CH_SEL (0x0 << 7) 305221807Sstas#define RT1015_I2S_RIGHT_CH_SEL (0x1 << 7) 306221807Sstas#define RT1015_I2S_CH_TX_LEN_MASK (0x7 << 4) 3071590Srgrimes#define RT1015_I2S_CH_TX_LEN_SFT 4 308221807Sstas#define RT1015_I2S_CH_TX_LEN_16B (0x0 << 4) 309221807Sstas#define RT1015_I2S_CH_TX_LEN_20B (0x1 << 4) 31017808Speter#define RT1015_I2S_CH_TX_LEN_24B (0x2 << 4) 31117808Speter#define RT1015_I2S_CH_TX_LEN_32B (0x3 << 4) 31217808Speter#define RT1015_I2S_CH_TX_LEN_8B (0x4 << 4) 313221807Sstas#define RT1015_I2S_CH_RX_LEN_MASK (0x7 << 0) 314221807Sstas#define RT1015_I2S_CH_RX_LEN_SFT 0 3151590Srgrimes#define RT1015_I2S_CH_RX_LEN_16B (0x0 << 0) 31693427Sdwmalone#define RT1015_I2S_CH_RX_LEN_20B (0x1 << 0) 3171590Srgrimes#define RT1015_I2S_CH_RX_LEN_24B (0x2 << 0) 318221807Sstas#define RT1015_I2S_CH_RX_LEN_32B (0x3 << 0) 3191590Srgrimes#define RT1015_I2S_CH_RX_LEN_8B (0x4 << 0) 3201590Srgrimes 3211590Srgrimes/* TDM1 Setting-4 (0x011a) */ 3221590Srgrimes#define RT1015_TDM_I2S_TX_L_DAC1_1_MASK (0x7 << 12) 3231590Srgrimes#define RT1015_TDM_I2S_TX_R_DAC1_1_MASK (0x7 << 8) 324221807Sstas#define RT1015_TDM_I2S_TX_L_DAC1_1_SFT 12 325221807Sstas#define RT1015_TDM_I2S_TX_R_DAC1_1_SFT 8 326221807Sstas 327221807Sstas/* 0x0330 */ 328221807Sstas#define RT1015_ABST_AUTO_EN_MASK (0x1 << 13) 329221807Sstas#define RT1015_ABST_AUTO_MODE (0x1 << 13) 3301590Srgrimes#define RT1015_ABST_REG_MODE (0x0 << 13) 331221807Sstas#define RT1015_ABST_FIX_TGT_MASK (0x1 << 12) 332221807Sstas#define RT1015_ABST_FIX_TGT_EN (0x1 << 12) 333221807Sstas#define RT1015_ABST_FIX_TGT_DIS (0x0 << 12) 334221807Sstas#define RT1015_BYPASS_SWR_REG_MASK (0x1 << 7) 3351590Srgrimes#define RT1015_BYPASS_SWRREG_BYPASS (0x1 << 7) 336221807Sstas#define RT1015_BYPASS_SWRREG_PASS (0x0 << 7) 337221807Sstas 3381590Srgrimes/* 0x0322 */ 339221807Sstas#define RT1015_PWR_LDO2 (0x1 << 15) 3401590Srgrimes#define RT1015_PWR_LDO2_BIT 15 3418874Srgrimes#define RT1015_PWR_DAC (0x1 << 14) 3421590Srgrimes#define RT1015_PWR_DAC_BIT 14 3431590Srgrimes#define RT1015_PWR_INTCLK (0x1 << 13) 3441590Srgrimes#define RT1015_PWR_INTCLK_BIT 13 3451590Srgrimes#define RT1015_PWR_ISENSE (0x1 << 12) 3461590Srgrimes#define RT1015_PWR_ISENSE_BIT 12 3471590Srgrimes#define RT1015_PWR_VSENSE (0x1 << 10) 3481590Srgrimes#define RT1015_PWR_VSENSE_BIT 10 3491590Srgrimes#define RT1015_PWR_PLL (0x1 << 9) 3501590Srgrimes#define RT1015_PWR_PLL_BIT 9 3511590Srgrimes#define RT1015_PWR_BG_1_2 (0x1 << 8) 352221807Sstas#define RT1015_PWR_BG_1_2_BIT 8 3531590Srgrimes#define RT1015_PWR_MBIAS_BG (0x1 << 7) 35457345Sshin#define RT1015_PWR_MBIAS_BG_BIT 7 355221807Sstas#define RT1015_PWR_VBAT (0x1 << 6) 356221807Sstas#define RT1015_PWR_VBAT_BIT 6 357221807Sstas#define RT1015_PWR_MBIAS (0x1 << 4) 358221807Sstas#define RT1015_PWR_MBIAS_BIT 4 359221807Sstas#define RT1015_PWR_ADCV (0x1 << 3) 360221807Sstas#define RT1015_PWR_ADCV_BIT 3 361221807Sstas#define RT1015_PWR_MIXERV (0x1 << 2) 362221807Sstas#define RT1015_PWR_MIXERV_BIT 2 363221807Sstas#define RT1015_PWR_SUMV (0x1 << 1) 3641590Srgrimes#define RT1015_PWR_SUMV_BIT 1 365221807Sstas#define RT1015_PWR_VREFLV (0x1 << 0) 366221807Sstas#define RT1015_PWR_VREFLV_BIT 0 3671590Srgrimes 3681590Srgrimes/* 0x0324 */ 3691590Srgrimes#define RT1015_PWR_BASIC (0x1 << 15) 370221807Sstas#define RT1015_PWR_BASIC_BIT 15 371221807Sstas#define RT1015_PWR_SD (0x1 << 14) 372221807Sstas#define RT1015_PWR_SD_BIT 14 3731590Srgrimes#define RT1015_PWR_IBIAS (0x1 << 13) 3741590Srgrimes#define RT1015_PWR_IBIAS_BIT 13 3751590Srgrimes#define RT1015_PWR_VCM (0x1 << 11) 376221807Sstas#define RT1015_PWR_VCM_BIT 11 3771590Srgrimes 3781590Srgrimes/* 0x0328 */ 379221807Sstas#define RT1015_PWR_SWR (0x1 << 12) 3801590Srgrimes#define RT1015_PWR_SWR_BIT 12 3811590Srgrimes 38280355Smjacob/* 0x0519 */ 383221807Sstas#define RT1015_EN_CLA_D_DC_DET_MASK (0x1 << 12) 384221807Sstas#define RT1015_EN_CLA_D_DC_DET (0x1 << 12) 3851590Srgrimes#define RT1015_DIS_CLA_D_DC_DET (0x0 << 12) 3861590Srgrimes 3871590Srgrimes/* 0x1300 */ 3881590Srgrimes#define RT1015_PWR_CLSD (0x1 << 12) 389221807Sstas#define RT1015_PWR_CLSD_BIT 12 3901590Srgrimes 3911590Srgrimes/* 0x007a */ 3921590Srgrimes#define RT1015_ID_MASK 0xff 393221807Sstas#define RT1015_ID_VERA 0x0 394221807Sstas#define RT1015_ID_VERB 0x1 395181905Sed 396221807Sstas/* System Clock Source */ 397221807Sstasenum { 398221807Sstas RT1015_SCLK_S_MCLK, 39953133Sgreen RT1015_SCLK_S_PLL, 400221807Sstas}; 401221807Sstas 402221807Sstas/* PLL1 Source */ 403221807Sstasenum { 404181905Sed RT1015_PLL_S_MCLK, 405221807Sstas RT1015_PLL_S_BCLK, 406221807Sstas}; 407221807Sstas 408221807Sstasenum { 409181905Sed RT1015_AIF1, 410221807Sstas RT1015_AIFS, 411221807Sstas}; 412221807Sstas 413221807Sstasenum { 414221807Sstas RT1015_VERA, 415221807Sstas RT1015_VERB, 416221807Sstas}; 417221807Sstas 418221807Sstasenum { 419221807Sstas BYPASS, 420221807Sstas ADAPTIVE, 421181905Sed FIXED_ADAPTIVE, 422181905Sed}; 423221807Sstas 424225847Sedenum { 425181905Sed RT1015_Enable_Boost = 0, 426221807Sstas RT1015_Bypass_Boost, 427181905Sed}; 428221807Sstas 429181905Sedenum { 430181905Sed RT1015_HW_28 = 0, 431221807Sstas RT1015_HW_29, 432250223Sjhb}; 433250223Sjhb 434250223Sjhbstruct rt1015_priv { 435250223Sjhb struct snd_soc_component *component; 436250223Sjhb struct rt1015_platform_data pdata; 437250223Sjhb struct regmap *regmap; 438250223Sjhb int sysclk; 439250223Sjhb int sysclk_src; 440250223Sjhb int pll_src; 441250223Sjhb int pll_in; 442250223Sjhb int pll_out; 443250223Sjhb int boost_mode; 444250223Sjhb int bypass_boost; 445250223Sjhb int dac_is_used; 446250223Sjhb int cali_done; 447250223Sjhb}; 448250223Sjhb 449250223Sjhb#endif /* __RT1015_H__ */ 450250223Sjhb