1/* 2 * Allwinner A64 SoCs pinctrl driver. 3 * 4 * Copyright (C) 2016 - ARM Ltd. 5 * Author: Andre Przywara <andre.przywara@arm.com> 6 * 7 * Based on pinctrl-sun7i-a20.c, which is: 8 * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com> 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 */ 14 15#include <linux/module.h> 16#include <linux/platform_device.h> 17#include <linux/of.h> 18#include <linux/pinctrl/pinctrl.h> 19 20#include "pinctrl-sunxi.h" 21 22static const struct sunxi_desc_pin a64_pins[] = { 23 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), 24 SUNXI_FUNCTION(0x0, "gpio_in"), 25 SUNXI_FUNCTION(0x1, "gpio_out"), 26 SUNXI_FUNCTION(0x2, "uart2"), /* TX */ 27 SUNXI_FUNCTION(0x4, "jtag"), /* MS0 */ 28 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* EINT0 */ 29 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), 30 SUNXI_FUNCTION(0x0, "gpio_in"), 31 SUNXI_FUNCTION(0x1, "gpio_out"), 32 SUNXI_FUNCTION(0x2, "uart2"), /* RX */ 33 SUNXI_FUNCTION(0x4, "jtag"), /* CK0 */ 34 SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */ 35 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* EINT1 */ 36 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), 37 SUNXI_FUNCTION(0x0, "gpio_in"), 38 SUNXI_FUNCTION(0x1, "gpio_out"), 39 SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ 40 SUNXI_FUNCTION(0x4, "jtag"), /* DO0 */ 41 SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */ 42 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* EINT2 */ 43 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), 44 SUNXI_FUNCTION(0x0, "gpio_in"), 45 SUNXI_FUNCTION(0x1, "gpio_out"), 46 SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ 47 SUNXI_FUNCTION(0x3, "i2s0"), /* MCLK */ 48 SUNXI_FUNCTION(0x4, "jtag"), /* DI0 */ 49 SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */ 50 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* EINT3 */ 51 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), 52 SUNXI_FUNCTION(0x0, "gpio_in"), 53 SUNXI_FUNCTION(0x1, "gpio_out"), 54 SUNXI_FUNCTION(0x2, "aif2"), /* SYNC */ 55 SUNXI_FUNCTION(0x3, "i2s0"), /* SYNC */ 56 SUNXI_FUNCTION(0x5, "sim"), /* CLK */ 57 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* EINT4 */ 58 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), 59 SUNXI_FUNCTION(0x0, "gpio_in"), 60 SUNXI_FUNCTION(0x1, "gpio_out"), 61 SUNXI_FUNCTION(0x2, "aif2"), /* BCLK */ 62 SUNXI_FUNCTION(0x3, "i2s0"), /* BCLK */ 63 SUNXI_FUNCTION(0x5, "sim"), /* DATA */ 64 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* EINT5 */ 65 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), 66 SUNXI_FUNCTION(0x0, "gpio_in"), 67 SUNXI_FUNCTION(0x1, "gpio_out"), 68 SUNXI_FUNCTION(0x2, "aif2"), /* DOUT */ 69 SUNXI_FUNCTION(0x3, "i2s0"), /* DOUT */ 70 SUNXI_FUNCTION(0x5, "sim"), /* RST */ 71 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* EINT6 */ 72 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), 73 SUNXI_FUNCTION(0x0, "gpio_in"), 74 SUNXI_FUNCTION(0x1, "gpio_out"), 75 SUNXI_FUNCTION(0x2, "aif2"), /* DIN */ 76 SUNXI_FUNCTION(0x3, "i2s0"), /* DIN */ 77 SUNXI_FUNCTION(0x5, "sim"), /* DET */ 78 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* EINT7 */ 79 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), 80 SUNXI_FUNCTION(0x0, "gpio_in"), 81 SUNXI_FUNCTION(0x1, "gpio_out"), 82 SUNXI_FUNCTION(0x4, "uart0"), /* TX */ 83 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* EINT8 */ 84 SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), 85 SUNXI_FUNCTION(0x0, "gpio_in"), 86 SUNXI_FUNCTION(0x1, "gpio_out"), 87 SUNXI_FUNCTION(0x4, "uart0"), /* RX */ 88 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* EINT9 */ 89 /* Hole */ 90 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), 91 SUNXI_FUNCTION(0x0, "gpio_in"), 92 SUNXI_FUNCTION(0x1, "gpio_out"), 93 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */ 94 SUNXI_FUNCTION(0x4, "spi0")), /* MOSI */ 95 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), 96 SUNXI_FUNCTION(0x0, "gpio_in"), 97 SUNXI_FUNCTION(0x1, "gpio_out"), 98 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */ 99 SUNXI_FUNCTION(0x3, "mmc2"), /* DS */ 100 SUNXI_FUNCTION(0x4, "spi0")), /* MISO */ 101 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), 102 SUNXI_FUNCTION(0x0, "gpio_in"), 103 SUNXI_FUNCTION(0x1, "gpio_out"), 104 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */ 105 SUNXI_FUNCTION(0x4, "spi0")), /* SCK */ 106 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), 107 SUNXI_FUNCTION(0x0, "gpio_in"), 108 SUNXI_FUNCTION(0x1, "gpio_out"), 109 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */ 110 SUNXI_FUNCTION(0x4, "spi0")), /* CS */ 111 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), 112 SUNXI_FUNCTION(0x0, "gpio_in"), 113 SUNXI_FUNCTION(0x1, "gpio_out"), 114 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */ 115 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), 116 SUNXI_FUNCTION(0x0, "gpio_in"), 117 SUNXI_FUNCTION(0x1, "gpio_out"), 118 SUNXI_FUNCTION(0x2, "nand0"), /* NRE# */ 119 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */ 120 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), 121 SUNXI_FUNCTION(0x0, "gpio_in"), 122 SUNXI_FUNCTION(0x1, "gpio_out"), 123 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */ 124 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */ 125 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), 126 SUNXI_FUNCTION(0x0, "gpio_in"), 127 SUNXI_FUNCTION(0x1, "gpio_out"), 128 SUNXI_FUNCTION(0x2, "nand0")), /* NRB1 */ 129 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), 130 SUNXI_FUNCTION(0x0, "gpio_in"), 131 SUNXI_FUNCTION(0x1, "gpio_out"), 132 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */ 133 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */ 134 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), 135 SUNXI_FUNCTION(0x0, "gpio_in"), 136 SUNXI_FUNCTION(0x1, "gpio_out"), 137 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */ 138 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */ 139 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), 140 SUNXI_FUNCTION(0x0, "gpio_in"), 141 SUNXI_FUNCTION(0x1, "gpio_out"), 142 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */ 143 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */ 144 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), 145 SUNXI_FUNCTION(0x0, "gpio_in"), 146 SUNXI_FUNCTION(0x1, "gpio_out"), 147 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */ 148 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */ 149 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), 150 SUNXI_FUNCTION(0x0, "gpio_in"), 151 SUNXI_FUNCTION(0x1, "gpio_out"), 152 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */ 153 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ 154 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), 155 SUNXI_FUNCTION(0x0, "gpio_in"), 156 SUNXI_FUNCTION(0x1, "gpio_out"), 157 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */ 158 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ 159 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), 160 SUNXI_FUNCTION(0x0, "gpio_in"), 161 SUNXI_FUNCTION(0x1, "gpio_out"), 162 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */ 163 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ 164 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), 165 SUNXI_FUNCTION(0x0, "gpio_in"), 166 SUNXI_FUNCTION(0x1, "gpio_out"), 167 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */ 168 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ 169 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), 170 SUNXI_FUNCTION(0x0, "gpio_in"), 171 SUNXI_FUNCTION(0x1, "gpio_out"), 172 SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */ 173 SUNXI_FUNCTION(0x3, "mmc2")), /* RST */ 174 /* Hole */ 175 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), 176 SUNXI_FUNCTION(0x0, "gpio_in"), 177 SUNXI_FUNCTION(0x1, "gpio_out"), 178 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ 179 SUNXI_FUNCTION(0x3, "uart3"), /* TX */ 180 SUNXI_FUNCTION(0x4, "spi1"), /* CS */ 181 SUNXI_FUNCTION(0x5, "ccir")), /* CLK */ 182 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), 183 SUNXI_FUNCTION(0x0, "gpio_in"), 184 SUNXI_FUNCTION(0x1, "gpio_out"), 185 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ 186 SUNXI_FUNCTION(0x3, "uart3"), /* RX */ 187 SUNXI_FUNCTION(0x4, "spi1"), /* CLK */ 188 SUNXI_FUNCTION(0x5, "ccir")), /* DE */ 189 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), 190 SUNXI_FUNCTION(0x0, "gpio_in"), 191 SUNXI_FUNCTION(0x1, "gpio_out"), 192 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ 193 SUNXI_FUNCTION(0x3, "uart4"), /* TX */ 194 SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */ 195 SUNXI_FUNCTION(0x5, "ccir")), /* HSYNC */ 196 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), 197 SUNXI_FUNCTION(0x0, "gpio_in"), 198 SUNXI_FUNCTION(0x1, "gpio_out"), 199 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ 200 SUNXI_FUNCTION(0x3, "uart4"), /* RX */ 201 SUNXI_FUNCTION(0x4, "spi1"), /* MISO */ 202 SUNXI_FUNCTION(0x5, "ccir")), /* VSYNC */ 203 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), 204 SUNXI_FUNCTION(0x0, "gpio_in"), 205 SUNXI_FUNCTION(0x1, "gpio_out"), 206 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ 207 SUNXI_FUNCTION(0x3, "uart4"), /* RTS */ 208 SUNXI_FUNCTION(0x5, "ccir")), /* D0 */ 209 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), 210 SUNXI_FUNCTION(0x0, "gpio_in"), 211 SUNXI_FUNCTION(0x1, "gpio_out"), 212 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ 213 SUNXI_FUNCTION(0x3, "uart4"), /* CTS */ 214 SUNXI_FUNCTION(0x5, "ccir")), /* D1 */ 215 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), 216 SUNXI_FUNCTION(0x0, "gpio_in"), 217 SUNXI_FUNCTION(0x1, "gpio_out"), 218 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ 219 SUNXI_FUNCTION(0x5, "ccir")), /* D2 */ 220 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), 221 SUNXI_FUNCTION(0x0, "gpio_in"), 222 SUNXI_FUNCTION(0x1, "gpio_out"), 223 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ 224 SUNXI_FUNCTION(0x5, "ccir")), /* D3 */ 225 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), 226 SUNXI_FUNCTION(0x0, "gpio_in"), 227 SUNXI_FUNCTION(0x1, "gpio_out"), 228 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ 229 SUNXI_FUNCTION(0x4, "emac"), /* ERXD3 */ 230 SUNXI_FUNCTION(0x5, "ccir")), /* D4 */ 231 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), 232 SUNXI_FUNCTION(0x0, "gpio_in"), 233 SUNXI_FUNCTION(0x1, "gpio_out"), 234 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ 235 SUNXI_FUNCTION(0x4, "emac"), /* ERXD2 */ 236 SUNXI_FUNCTION(0x5, "ccir")), /* D5 */ 237 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), 238 SUNXI_FUNCTION(0x0, "gpio_in"), 239 SUNXI_FUNCTION(0x1, "gpio_out"), 240 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ 241 SUNXI_FUNCTION(0x4, "emac")), /* ERXD1 */ 242 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), 243 SUNXI_FUNCTION(0x0, "gpio_in"), 244 SUNXI_FUNCTION(0x1, "gpio_out"), 245 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ 246 SUNXI_FUNCTION(0x4, "emac")), /* ERXD0 */ 247 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), 248 SUNXI_FUNCTION(0x0, "gpio_in"), 249 SUNXI_FUNCTION(0x1, "gpio_out"), 250 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ 251 SUNXI_FUNCTION(0x3, "lvds0"), /* VP0 */ 252 SUNXI_FUNCTION(0x4, "emac")), /* ERXCK */ 253 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), 254 SUNXI_FUNCTION(0x0, "gpio_in"), 255 SUNXI_FUNCTION(0x1, "gpio_out"), 256 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ 257 SUNXI_FUNCTION(0x3, "lvds0"), /* VN0 */ 258 SUNXI_FUNCTION(0x4, "emac")), /* ERXCTL */ 259 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), 260 SUNXI_FUNCTION(0x0, "gpio_in"), 261 SUNXI_FUNCTION(0x1, "gpio_out"), 262 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ 263 SUNXI_FUNCTION(0x3, "lvds0"), /* VP1 */ 264 SUNXI_FUNCTION(0x4, "emac")), /* ENULL */ 265 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), 266 SUNXI_FUNCTION(0x0, "gpio_in"), 267 SUNXI_FUNCTION(0x1, "gpio_out"), 268 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ 269 SUNXI_FUNCTION(0x3, "lvds0"), /* VN1 */ 270 SUNXI_FUNCTION(0x4, "emac"), /* ETXD3 */ 271 SUNXI_FUNCTION(0x5, "ccir")), /* D6 */ 272 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), 273 SUNXI_FUNCTION(0x0, "gpio_in"), 274 SUNXI_FUNCTION(0x1, "gpio_out"), 275 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ 276 SUNXI_FUNCTION(0x3, "lvds0"), /* VP2 */ 277 SUNXI_FUNCTION(0x4, "emac"), /* ETXD2 */ 278 SUNXI_FUNCTION(0x5, "ccir")), /* D7 */ 279 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), 280 SUNXI_FUNCTION(0x0, "gpio_in"), 281 SUNXI_FUNCTION(0x1, "gpio_out"), 282 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ 283 SUNXI_FUNCTION(0x3, "lvds0"), /* VN2 */ 284 SUNXI_FUNCTION(0x4, "emac")), /* ETXD1 */ 285 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), 286 SUNXI_FUNCTION(0x0, "gpio_in"), 287 SUNXI_FUNCTION(0x1, "gpio_out"), 288 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ 289 SUNXI_FUNCTION(0x3, "lvds0"), /* VPC */ 290 SUNXI_FUNCTION(0x4, "emac")), /* ETXD0 */ 291 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), 292 SUNXI_FUNCTION(0x0, "gpio_in"), 293 SUNXI_FUNCTION(0x1, "gpio_out"), 294 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ 295 SUNXI_FUNCTION(0x3, "lvds0"), /* VNC */ 296 SUNXI_FUNCTION(0x4, "emac")), /* ETXCK */ 297 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), 298 SUNXI_FUNCTION(0x0, "gpio_in"), 299 SUNXI_FUNCTION(0x1, "gpio_out"), 300 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ 301 SUNXI_FUNCTION(0x3, "lvds0"), /* VP3 */ 302 SUNXI_FUNCTION(0x4, "emac")), /* ETXCTL */ 303 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), 304 SUNXI_FUNCTION(0x0, "gpio_in"), 305 SUNXI_FUNCTION(0x1, "gpio_out"), 306 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ 307 SUNXI_FUNCTION(0x3, "lvds0"), /* VN3 */ 308 SUNXI_FUNCTION(0x4, "emac")), /* ECLKIN */ 309 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), 310 SUNXI_FUNCTION(0x0, "gpio_in"), 311 SUNXI_FUNCTION(0x1, "gpio_out"), 312 SUNXI_FUNCTION(0x2, "pwm"), /* PWM0 */ 313 SUNXI_FUNCTION(0x4, "emac")), /* EMDC */ 314 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), 315 SUNXI_FUNCTION(0x0, "gpio_in"), 316 SUNXI_FUNCTION(0x1, "gpio_out"), 317 SUNXI_FUNCTION(0x4, "emac")), /* EMDIO */ 318 SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), 319 SUNXI_FUNCTION(0x0, "gpio_in"), 320 SUNXI_FUNCTION(0x1, "gpio_out")), 321 /* Hole */ 322 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), 323 SUNXI_FUNCTION(0x0, "gpio_in"), 324 SUNXI_FUNCTION(0x1, "gpio_out"), 325 SUNXI_FUNCTION(0x2, "csi"), /* PCK */ 326 SUNXI_FUNCTION(0x4, "ts")), /* CLK */ 327 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), 328 SUNXI_FUNCTION(0x0, "gpio_in"), 329 SUNXI_FUNCTION(0x1, "gpio_out"), 330 SUNXI_FUNCTION(0x2, "csi"), /* CK */ 331 SUNXI_FUNCTION(0x4, "ts")), /* ERR */ 332 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), 333 SUNXI_FUNCTION(0x0, "gpio_in"), 334 SUNXI_FUNCTION(0x1, "gpio_out"), 335 SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ 336 SUNXI_FUNCTION(0x4, "ts")), /* SYNC */ 337 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), 338 SUNXI_FUNCTION(0x0, "gpio_in"), 339 SUNXI_FUNCTION(0x1, "gpio_out"), 340 SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ 341 SUNXI_FUNCTION(0x4, "ts")), /* DVLD */ 342 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), 343 SUNXI_FUNCTION(0x0, "gpio_in"), 344 SUNXI_FUNCTION(0x1, "gpio_out"), 345 SUNXI_FUNCTION(0x2, "csi"), /* D0 */ 346 SUNXI_FUNCTION(0x4, "ts")), /* D0 */ 347 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), 348 SUNXI_FUNCTION(0x0, "gpio_in"), 349 SUNXI_FUNCTION(0x1, "gpio_out"), 350 SUNXI_FUNCTION(0x2, "csi"), /* D1 */ 351 SUNXI_FUNCTION(0x4, "ts")), /* D1 */ 352 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), 353 SUNXI_FUNCTION(0x0, "gpio_in"), 354 SUNXI_FUNCTION(0x1, "gpio_out"), 355 SUNXI_FUNCTION(0x2, "csi"), /* D2 */ 356 SUNXI_FUNCTION(0x4, "ts")), /* D2 */ 357 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), 358 SUNXI_FUNCTION(0x0, "gpio_in"), 359 SUNXI_FUNCTION(0x1, "gpio_out"), 360 SUNXI_FUNCTION(0x2, "csi"), /* D3 */ 361 SUNXI_FUNCTION(0x4, "ts")), /* D3 */ 362 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), 363 SUNXI_FUNCTION(0x0, "gpio_in"), 364 SUNXI_FUNCTION(0x1, "gpio_out"), 365 SUNXI_FUNCTION(0x2, "csi"), /* D4 */ 366 SUNXI_FUNCTION(0x4, "ts")), /* D4 */ 367 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), 368 SUNXI_FUNCTION(0x0, "gpio_in"), 369 SUNXI_FUNCTION(0x1, "gpio_out"), 370 SUNXI_FUNCTION(0x2, "csi"), /* D5 */ 371 SUNXI_FUNCTION(0x4, "ts")), /* D5 */ 372 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), 373 SUNXI_FUNCTION(0x0, "gpio_in"), 374 SUNXI_FUNCTION(0x1, "gpio_out"), 375 SUNXI_FUNCTION(0x2, "csi"), /* D6 */ 376 SUNXI_FUNCTION(0x4, "ts")), /* D6 */ 377 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), 378 SUNXI_FUNCTION(0x0, "gpio_in"), 379 SUNXI_FUNCTION(0x1, "gpio_out"), 380 SUNXI_FUNCTION(0x2, "csi"), /* D7 */ 381 SUNXI_FUNCTION(0x4, "ts")), /* D7 */ 382 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), 383 SUNXI_FUNCTION(0x0, "gpio_in"), 384 SUNXI_FUNCTION(0x1, "gpio_out"), 385 SUNXI_FUNCTION(0x2, "csi")), /* SCK */ 386 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), 387 SUNXI_FUNCTION(0x0, "gpio_in"), 388 SUNXI_FUNCTION(0x1, "gpio_out"), 389 SUNXI_FUNCTION(0x2, "csi")), /* SDA */ 390 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), 391 SUNXI_FUNCTION(0x0, "gpio_in"), 392 SUNXI_FUNCTION(0x1, "gpio_out"), 393 SUNXI_FUNCTION(0x2, "pll"), /* LOCK_DBG */ 394 SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */ 395 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), 396 SUNXI_FUNCTION(0x0, "gpio_in"), 397 SUNXI_FUNCTION(0x1, "gpio_out"), 398 SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */ 399 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16), 400 SUNXI_FUNCTION(0x0, "gpio_in"), 401 SUNXI_FUNCTION(0x1, "gpio_out")), 402 SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17), 403 SUNXI_FUNCTION(0x0, "gpio_in"), 404 SUNXI_FUNCTION(0x1, "gpio_out")), 405 /* Hole */ 406 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), 407 SUNXI_FUNCTION(0x0, "gpio_in"), 408 SUNXI_FUNCTION(0x1, "gpio_out"), 409 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ 410 SUNXI_FUNCTION(0x3, "jtag")), /* MSI */ 411 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), 412 SUNXI_FUNCTION(0x0, "gpio_in"), 413 SUNXI_FUNCTION(0x1, "gpio_out"), 414 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ 415 SUNXI_FUNCTION(0x3, "jtag")), /* DI1 */ 416 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), 417 SUNXI_FUNCTION(0x0, "gpio_in"), 418 SUNXI_FUNCTION(0x1, "gpio_out"), 419 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ 420 SUNXI_FUNCTION(0x3, "uart0")), /* TX */ 421 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), 422 SUNXI_FUNCTION(0x0, "gpio_in"), 423 SUNXI_FUNCTION(0x1, "gpio_out"), 424 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ 425 SUNXI_FUNCTION(0x3, "jtag")), /* DO1 */ 426 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), 427 SUNXI_FUNCTION(0x0, "gpio_in"), 428 SUNXI_FUNCTION(0x1, "gpio_out"), 429 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ 430 SUNXI_FUNCTION(0x3, "uart0")), /* RX */ 431 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), 432 SUNXI_FUNCTION(0x0, "gpio_in"), 433 SUNXI_FUNCTION(0x1, "gpio_out"), 434 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ 435 SUNXI_FUNCTION(0x3, "jtag")), /* CK1 */ 436 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), 437 SUNXI_FUNCTION(0x0, "gpio_in"), 438 SUNXI_FUNCTION(0x1, "gpio_out")), 439 /* Hole */ 440 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), 441 SUNXI_FUNCTION(0x0, "gpio_in"), 442 SUNXI_FUNCTION(0x1, "gpio_out"), 443 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ 444 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* EINT0 */ 445 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), 446 SUNXI_FUNCTION(0x0, "gpio_in"), 447 SUNXI_FUNCTION(0x1, "gpio_out"), 448 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ 449 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* EINT1 */ 450 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), 451 SUNXI_FUNCTION(0x0, "gpio_in"), 452 SUNXI_FUNCTION(0x1, "gpio_out"), 453 SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ 454 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* EINT2 */ 455 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), 456 SUNXI_FUNCTION(0x0, "gpio_in"), 457 SUNXI_FUNCTION(0x1, "gpio_out"), 458 SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ 459 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* EINT3 */ 460 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), 461 SUNXI_FUNCTION(0x0, "gpio_in"), 462 SUNXI_FUNCTION(0x1, "gpio_out"), 463 SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ 464 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* EINT4 */ 465 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), 466 SUNXI_FUNCTION(0x0, "gpio_in"), 467 SUNXI_FUNCTION(0x1, "gpio_out"), 468 SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ 469 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* EINT5 */ 470 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), 471 SUNXI_FUNCTION(0x0, "gpio_in"), 472 SUNXI_FUNCTION(0x1, "gpio_out"), 473 SUNXI_FUNCTION(0x2, "uart1"), /* TX */ 474 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* EINT6 */ 475 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), 476 SUNXI_FUNCTION(0x0, "gpio_in"), 477 SUNXI_FUNCTION(0x1, "gpio_out"), 478 SUNXI_FUNCTION(0x2, "uart1"), /* RX */ 479 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* EINT7 */ 480 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), 481 SUNXI_FUNCTION(0x0, "gpio_in"), 482 SUNXI_FUNCTION(0x1, "gpio_out"), 483 SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ 484 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* EINT8 */ 485 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), 486 SUNXI_FUNCTION(0x0, "gpio_in"), 487 SUNXI_FUNCTION(0x1, "gpio_out"), 488 SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ 489 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* EINT9 */ 490 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), 491 SUNXI_FUNCTION(0x0, "gpio_in"), 492 SUNXI_FUNCTION(0x1, "gpio_out"), 493 SUNXI_FUNCTION(0x2, "aif3"), /* SYNC */ 494 SUNXI_FUNCTION(0x3, "i2s1"), /* SYNC */ 495 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* EINT10 */ 496 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), 497 SUNXI_FUNCTION(0x0, "gpio_in"), 498 SUNXI_FUNCTION(0x1, "gpio_out"), 499 SUNXI_FUNCTION(0x2, "aif3"), /* BCLK */ 500 SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */ 501 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* EINT11 */ 502 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), 503 SUNXI_FUNCTION(0x0, "gpio_in"), 504 SUNXI_FUNCTION(0x1, "gpio_out"), 505 SUNXI_FUNCTION(0x2, "aif3"), /* DOUT */ 506 SUNXI_FUNCTION(0x3, "i2s1"), /* DOUT */ 507 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* EINT12 */ 508 SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), 509 SUNXI_FUNCTION(0x0, "gpio_in"), 510 SUNXI_FUNCTION(0x1, "gpio_out"), 511 SUNXI_FUNCTION(0x2, "aif3"), /* DIN */ 512 SUNXI_FUNCTION(0x3, "i2s1"), /* DIN */ 513 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* EINT13 */ 514 /* Hole */ 515 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), 516 SUNXI_FUNCTION(0x0, "gpio_in"), 517 SUNXI_FUNCTION(0x1, "gpio_out"), 518 SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */ 519 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* EINT0 */ 520 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), 521 SUNXI_FUNCTION(0x0, "gpio_in"), 522 SUNXI_FUNCTION(0x1, "gpio_out"), 523 SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */ 524 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* EINT1 */ 525 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), 526 SUNXI_FUNCTION(0x0, "gpio_in"), 527 SUNXI_FUNCTION(0x1, "gpio_out"), 528 SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */ 529 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* EINT2 */ 530 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), 531 SUNXI_FUNCTION(0x0, "gpio_in"), 532 SUNXI_FUNCTION(0x1, "gpio_out"), 533 SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */ 534 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* EINT3 */ 535 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), 536 SUNXI_FUNCTION(0x0, "gpio_in"), 537 SUNXI_FUNCTION(0x1, "gpio_out"), 538 SUNXI_FUNCTION(0x2, "uart3"), /* TX */ 539 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* EINT4 */ 540 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), 541 SUNXI_FUNCTION(0x0, "gpio_in"), 542 SUNXI_FUNCTION(0x1, "gpio_out"), 543 SUNXI_FUNCTION(0x2, "uart3"), /* RX */ 544 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* EINT5 */ 545 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), 546 SUNXI_FUNCTION(0x0, "gpio_in"), 547 SUNXI_FUNCTION(0x1, "gpio_out"), 548 SUNXI_FUNCTION(0x2, "uart3"), /* RTS */ 549 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* EINT6 */ 550 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), 551 SUNXI_FUNCTION(0x0, "gpio_in"), 552 SUNXI_FUNCTION(0x1, "gpio_out"), 553 SUNXI_FUNCTION(0x2, "uart3"), /* CTS */ 554 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* EINT7 */ 555 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), 556 SUNXI_FUNCTION(0x0, "gpio_in"), 557 SUNXI_FUNCTION(0x1, "gpio_out"), 558 SUNXI_FUNCTION(0x2, "spdif"), /* OUT */ 559 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* EINT8 */ 560 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), 561 SUNXI_FUNCTION(0x0, "gpio_in"), 562 SUNXI_FUNCTION(0x1, "gpio_out"), 563 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* EINT9 */ 564 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10), 565 SUNXI_FUNCTION(0x0, "gpio_in"), 566 SUNXI_FUNCTION(0x1, "gpio_out"), 567 SUNXI_FUNCTION(0x2, "mic"), /* CLK */ 568 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* EINT10 */ 569 SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11), 570 SUNXI_FUNCTION(0x0, "gpio_in"), 571 SUNXI_FUNCTION(0x1, "gpio_out"), 572 SUNXI_FUNCTION(0x2, "mic"), /* DATA */ 573 SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* EINT11 */ 574}; 575 576static const struct sunxi_pinctrl_desc a64_pinctrl_data = { 577 .pins = a64_pins, 578 .npins = ARRAY_SIZE(a64_pins), 579 .irq_banks = 3, 580}; 581 582static int a64_pinctrl_probe(struct platform_device *pdev) 583{ 584 return sunxi_pinctrl_init(pdev, 585 &a64_pinctrl_data); 586} 587 588static const struct of_device_id a64_pinctrl_match[] = { 589 { .compatible = "allwinner,sun50i-a64-pinctrl", }, 590 {} 591}; 592 593static struct platform_driver a64_pinctrl_driver = { 594 .probe = a64_pinctrl_probe, 595 .driver = { 596 .name = "sun50i-a64-pinctrl", 597 .of_match_table = a64_pinctrl_match, 598 }, 599}; 600builtin_platform_driver(a64_pinctrl_driver); 601