Searched refs:wptr (Results 126 - 137 of 137) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ras.h615 unsigned int wptr; member in struct:ras_ih_data
H A Damdgpu_vcn.c1109 write_pos = plog->wptr;
1189 log_buf->wptr = log_buf->header_size;
H A Dgfx_v7_0.c2559 ring->wptr = 0;
2560 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2602 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2617 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
2618 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
2943 ring->wptr = 0;
2944 mqd->cp_hqd_pq_wptr = lower_32_bits(ring->wptr);
2981 /* disable wptr polling */
H A Damdgpu_ras.c2138 while (data->rptr != data->wptr) {
2185 memcpy(&data->ring[data->wptr], info->entry,
2189 data->wptr = (data->aligned_element_size +
2190 data->wptr) % data->ring_size;
2243 .wptr = 0,
/linux-master/fs/smb/server/
H A Dsmb2pdu.c3854 kstat = d_info->wptr;
3856 kstat = ksmbd_vfs_init_kstat(&d_info->wptr, ksmbd_kstat);
3998 d_info->wptr += next_entry_offset;
4114 ffdinfo = (struct file_full_directory_info *)d_info->wptr;
4125 fbdinfo = (struct file_both_directory_info *)d_info->wptr;
4136 fdinfo = (struct file_directory_info *)d_info->wptr;
4147 fninfo = (struct file_names_info *)d_info->wptr;
4158 dinfo = (struct file_id_full_dir_info *)d_info->wptr;
4169 fibdinfo = (struct file_id_both_directory_info *)d_info->wptr;
4180 posix_info = (struct smb2_posix_info *)d_info->wptr;
[all...]
/linux-master/drivers/gpu/drm/amd/display/dmub/inc/
H A Ddmub_cmd.h4995 uint32_t wptr = rb->wrpt; local
4997 while (rptr != wptr) {
/linux-master/drivers/scsi/qla2xxx/
H A Dqla_nx.c1952 __le16 __iomem *wptr; local
1956 wptr = &reg->mailbox_out[1];
1963 ha->mailbox_out[cnt] = rd_reg_word(wptr);
1964 wptr++;
H A Dqla_mr.c2847 __le32 __iomem *wptr; local
2857 wptr = &reg->mailbox17;
2860 ha->mailbox_out32[cnt] = rd_reg_dword(wptr);
2861 wptr++;
/linux-master/drivers/gpu/drm/radeon/
H A Dr100.c1095 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1192 ring->wptr = 0;
1193 WREG32(RADEON_CP_RB_WPTR, ring->wptr);
2996 seq_printf(m, "Ring wptr %u\n", r_wptr);
2998 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
3000 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
3694 u32 next_rptr = ring->wptr + 2 + 3;
H A Dradeon.h800 unsigned wptr; member in struct:radeon_ring
2679 ring->ring[ring->wptr++] = v;
2680 ring->wptr &= ring->ptr_mask;
/linux-master/drivers/net/ethernet/sun/
H A Dcassini.c4100 u32 wptr, rptr; local
4112 wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR);
4114 if ((val == 0) && (wptr != rptr)) {
4117 val, wptr, rptr);
/linux-master/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu.c43 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n",
70 uint32_t wptr; local
80 /* Make sure to wrap wptr if we need to */
81 wptr = get_wptr(ring);
88 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr);
234 * Periodically update shadow-wptr if needed, so that we
320 * Periodically update shadow-wptr if needed, so that we

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