Searched refs:val (Results 151 - 175 of 11023) sorted by relevance

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/linux-master/tools/testing/selftests/powerpc/dscr/
H A Ddscr_sysfs_thread_test.c15 static int test_thread_dscr(unsigned long val) argument
22 if (val != cur_dscr) {
24 sched_getcpu(), val, cur_dscr);
28 if (val != cur_dscr_usr) {
30 sched_getcpu(), val, cur_dscr_usr);
36 static int check_cpu_dscr_thread(unsigned long val) argument
47 if (test_thread_dscr(val))
/linux-master/tools/testing/selftests/bpf/progs/
H A Dbpf_iter_bpf_sk_storage_map.c25 __u32 *val = ctx->value; local
27 if (sk == NULL || val == NULL)
33 val_sum += *val;
35 *val += to_add_val;
44 __u32 *val = ctx->value; local
46 if (sk == NULL || val == NULL)
49 *(val + 1) = 0xdeadbeef;
/linux-master/tools/testing/selftests/kvm/x86_64/
H A Dhwcr_msr_test.c16 uint64_t val = BIT_ULL(bit); local
20 r = _vcpu_set_msr(vcpu, MSR_K7_HWCR, val);
21 TEST_ASSERT(val & ~legal ? !r : r == 1,
23 val, val & ~legal ? "fail" : "succeed");
26 TEST_ASSERT(actual == (val & valid),
28 bit, actual, (val & valid));
/linux-master/arch/powerpc/lib/
H A Dqspinlock.c105 static inline int decode_tail_cpu(u32 val) argument
107 return (val >> _Q_TAIL_CPU_OFFSET) - 1;
110 static inline int get_owner_cpu(u32 val) argument
112 return (val & _Q_OWNER_CPU_MASK) >> _Q_OWNER_CPU_OFFSET;
145 : "r" (&lock->val), "r"(tail), "r" (newval),
175 : "r" (&lock->val), "r" (tail), "r"(_Q_TAIL_CPU_MASK)
191 : "r" (&lock->val), "r" (_Q_MUST_Q_VAL)
207 : "r" (&lock->val), "r" (_Q_MUST_Q_VAL)
229 : "r" (&lock->val), "r"(old), "r" (new)
235 static __always_inline void seen_sleepy_owner(struct qspinlock *lock, u32 val) argument
284 __yield_to_locked_owner(struct qspinlock *lock, u32 val, bool paravirt, bool mustq) argument
337 yield_to_locked_owner(struct qspinlock *lock, u32 val, bool paravirt) argument
343 yield_head_to_locked_owner(struct qspinlock *lock, u32 val, bool paravirt) argument
353 propagate_sleepy(struct qnode *node, u32 val, bool paravirt) argument
392 u32 val = READ_ONCE(lock->val); local
442 steal_break(u32 val, int iters, bool paravirt, bool sleepy) argument
461 u32 val; local
530 u32 val, old, tail; local
733 steal_spins_set(void *data, u64 val) argument
768 steal_spins_get(void *data, u64 *val) argument
777 remote_steal_spins_set(void *data, u64 val) argument
784 remote_steal_spins_get(void *data, u64 *val) argument
793 head_spins_set(void *data, u64 val) argument
800 head_spins_get(void *data, u64 *val) argument
809 pv_yield_owner_set(void *data, u64 val) argument
816 pv_yield_owner_get(void *data, u64 *val) argument
825 pv_yield_allow_steal_set(void *data, u64 val) argument
832 pv_yield_allow_steal_get(void *data, u64 *val) argument
841 pv_spin_on_preempted_owner_set(void *data, u64 val) argument
848 pv_spin_on_preempted_owner_get(void *data, u64 *val) argument
857 pv_sleepy_lock_set(void *data, u64 val) argument
864 pv_sleepy_lock_get(void *data, u64 *val) argument
873 pv_sleepy_lock_sticky_set(void *data, u64 val) argument
880 pv_sleepy_lock_sticky_get(void *data, u64 *val) argument
889 pv_sleepy_lock_interval_ns_set(void *data, u64 val) argument
896 pv_sleepy_lock_interval_ns_get(void *data, u64 *val) argument
905 pv_sleepy_lock_factor_set(void *data, u64 val) argument
912 pv_sleepy_lock_factor_get(void *data, u64 *val) argument
921 pv_yield_prev_set(void *data, u64 val) argument
928 pv_yield_prev_get(void *data, u64 *val) argument
937 pv_yield_sleepy_owner_set(void *data, u64 val) argument
944 pv_yield_sleepy_owner_get(void *data, u64 *val) argument
953 pv_prod_head_set(void *data, u64 val) argument
960 pv_prod_head_get(void *data, u64 *val) argument
[all...]
/linux-master/drivers/accel/ivpu/
H A Divpu_hw_37xx.c111 u32 val; local
119 val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0);
120 val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, MIN_RATIO, min_ratio, val);
121 val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, MAX_RATIO, max_ratio, val);
122 REGB_WR32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD0, val);
124 val = REGB_RD32(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1);
125 val = REG_SET_FLD_NUM(VPU_37XX_BUTTRESS_WP_REQ_PAYLOAD1, TARGET_RATIO, target_ratio, val);
249 u32 val = 0; local
260 u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_RST_SET); local
277 u32 val = REGV_RD32(VPU_37XX_HOST_SS_CPR_CLK_SET); local
294 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN); local
304 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QACCEPTN); local
314 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QDENY); local
324 u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN); local
335 u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QACCEPTN); local
346 u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QDENY); local
370 u32 val; local
400 u32 val; local
432 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_TRICKLE_EN0); local
444 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISLAND_EN0); local
462 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_PWR_ISO_EN0); local
474 u32 val = REGV_RD32(VPU_37XX_HOST_SS_AON_DPU_ACTIVE); local
513 u32 val = REGV_RD32(VPU_37XX_HOST_IF_TCU_PTW_OVERRIDES); local
524 u32 val = REGV_RD32(VPU_37XX_HOST_IF_TBU_MMUSSIDV); local
536 u32 val; local
563 u32 val; local
610 u32 val; local
735 u32 val; local
780 u32 val; local
851 u32 val = REG_FLD(VPU_37XX_CPU_SS_DOORBELL_0, SET); local
[all...]
H A Divpu_hw_reg_io.h21 #define REGB_WR32(reg, val) ivpu_hw_reg_wr32(vdev, vdev->regb, (reg), (val), #reg, __func__)
22 #define REGB_WR64(reg, val) ivpu_hw_reg_wr64(vdev, vdev->regb, (reg), (val), #reg, __func__)
27 #define REGV_WR32(reg, val) ivpu_hw_reg_wr32(vdev, vdev->regv, (reg), (val), #reg, __func__)
28 #define REGV_WR64(reg, val) ivpu_hw_reg_wr64(vdev, vdev->regv, (reg), (val), #reg, __func__)
30 #define REGV_WR32I(reg, stride, index, val) \
31 ivpu_hw_reg_wr32_index(vdev, vdev->regv, (reg), (stride), (index), (val), #re
80 u32 val = readl(base + reg); local
90 u64 val = readq(base + reg); local
97 ivpu_hw_reg_wr32(struct ivpu_device *vdev, void __iomem *base, u32 reg, u32 val, const char *name, const char *func) argument
105 ivpu_hw_reg_wr64(struct ivpu_device *vdev, void __iomem *base, u32 reg, u64 val, const char *name, const char *func) argument
113 ivpu_hw_reg_wr32_index(struct ivpu_device *vdev, void __iomem *base, u32 reg, u32 stride, u32 index, u32 val, const char *name, const char *func) argument
[all...]
/linux-master/arch/mips/include/asm/
H A Dmipsregs.h1540 #define write_r10k_perf_cntr(counter,val) \
1545 : "r" (val), "i" (counter)); \
1559 #define write_r10k_perf_cntl(counter,val) \
1564 : "r" (val), "i" (counter)); \
1666 #define __write_ulong_c0_register(reg, sel, val) \
1669 __write_32bit_c0_register(reg, sel, val); \
1671 __write_64bit_c0_register(reg, sel, val); \
1725 #define __write_64bit_c0_split(source, sel, val) \
1727 unsigned long long __tmp = (val); \
1812 #define write_c0_index(val) __write_32bit_c0_registe
[all...]
/linux-master/drivers/misc/lkdtm/
H A Dheap.c94 int *base, *val, saw; local
110 val = kmalloc(len, GFP_KERNEL);
111 if (!val) {
112 pr_info("Unable to allocate val memory.\n");
117 *val = 0x12345678;
118 base[offset] = *val;
125 if (saw != *val) {
133 kfree(val);
138 int *base, val, saw; local
168 val
217 int saw, *val; local
254 u8 *val; local
286 u8 *val; local
318 int *val; local
335 int *val; local
[all...]
/linux-master/drivers/mfd/
H A Dpcf50633-gpio.c33 int pcf50633_gpio_set(struct pcf50633 *pcf, int gpio, u8 val) argument
39 return pcf50633_reg_set_bit_mask(pcf, reg, 0x07, val);
45 u8 reg, val; local
48 val = pcf50633_reg_read(pcf, reg) & 0x07;
50 return val;
56 u8 val, reg; local
59 val = !!invert << 3;
61 return pcf50633_reg_set_bit_mask(pcf, reg, 1 << 3, val);
67 u8 reg, val; local
70 val
79 u8 reg, val, mask; local
[all...]
/linux-master/arch/arm64/include/asm/
H A Dpercpu.h61 static inline void __percpu_write_##sz(void *ptr, unsigned long val) \
63 WRITE_ONCE(*(u##sz *)ptr, (u##sz)val); \
68 __percpu_##name##_case_##sz(void *ptr, unsigned long val) \
76 #op_llsc "\t%" #w "[tmp], %" #w "[tmp], %" #w "[val]\n" \
80 #op_lse "\t%" #w "[val], %[ptr]\n" \
84 : [val] "r" ((u##sz)(val))); \
89 __percpu_##name##_return_case_##sz(void *ptr, unsigned long val) \
97 #op_llsc "\t%" #w "[ret], %" #w "[ret], %" #w "[val]\n" \
101 #op_lse "\t%" #w "[val],
[all...]
/linux-master/arch/powerpc/include/asm/
H A Dkvm_booke.h26 static inline void kvmppc_set_gpr(struct kvm_vcpu *vcpu, int num, ulong val) argument
28 vcpu->arch.regs.gpr[num] = val;
36 static inline void kvmppc_set_cr(struct kvm_vcpu *vcpu, u32 val) argument
38 vcpu->arch.regs.ccr = val;
46 static inline void kvmppc_set_xer(struct kvm_vcpu *vcpu, ulong val) argument
48 vcpu->arch.regs.xer = val;
62 static inline void kvmppc_set_ctr(struct kvm_vcpu *vcpu, ulong val) argument
64 vcpu->arch.regs.ctr = val;
72 static inline void kvmppc_set_lr(struct kvm_vcpu *vcpu, ulong val) argument
74 vcpu->arch.regs.link = val;
82 kvmppc_set_pc(struct kvm_vcpu *vcpu, ulong val) argument
92 kvmppc_set_fpr(struct kvm_vcpu *vcpu, int i, u64 val) argument
[all...]
/linux-master/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_model.h12 int (*val)(struct ixgbe_fdir_filter *input, member in struct:ixgbe_mat_field
14 u32 val, u32 m);
30 u32 val, u32 m)
32 input->filter.formatted.src_ip[0] = (__force __be32)val;
39 u32 val, u32 m)
41 input->filter.formatted.dst_ip[0] = (__force __be32)val;
47 { .off = 12, .val = ixgbe_mat_prgm_sip,
49 { .off = 16, .val = ixgbe_mat_prgm_dip,
51 { .val = NULL } /* terminal node */
56 u32 val, u3
28 ixgbe_mat_prgm_sip(struct ixgbe_fdir_filter *input, union ixgbe_atr_input *mask, u32 val, u32 m) argument
37 ixgbe_mat_prgm_dip(struct ixgbe_fdir_filter *input, union ixgbe_atr_input *mask, u32 val, u32 m) argument
54 ixgbe_mat_prgm_ports(struct ixgbe_fdir_filter *input, union ixgbe_atr_input *mask, u32 val, u32 m) argument
85 u32 val; member in struct:ixgbe_nexthdr
[all...]
/linux-master/drivers/gpu/drm/sprd/
H A Dmegacores_pll.c127 static void dphy_set_timing_reg(struct regmap *regmap, int type, u8 val[]) argument
131 regmap_write(regmap, 0x31, val[CLK]);
132 regmap_write(regmap, 0x41, val[DATA]);
133 regmap_write(regmap, 0x51, val[DATA]);
134 regmap_write(regmap, 0x61, val[DATA]);
135 regmap_write(regmap, 0x71, val[DATA]);
137 regmap_write(regmap, 0x90, val[CLK]);
138 regmap_write(regmap, 0xa0, val[DATA]);
139 regmap_write(regmap, 0xb0, val[DATA]);
140 regmap_write(regmap, 0xc0, val[DAT
222 u8 val[2]; local
[all...]
/linux-master/tools/testing/selftests/bpf/prog_tests/
H A Dbtf_map_in_map.c28 int err, key = 0, val, i; local
53 bpf_map_lookup_elem(map1_fd, &key, &val);
54 CHECK(val != 1, "inner1", "got %d != exp %d\n", val, 1);
55 bpf_map_lookup_elem(map2_fd, &key, &val);
56 CHECK(val != 2, "inner2", "got %d != exp %d\n", val, 2);
57 bpf_map_lookup_elem(map3_fd, &key, &val);
58 CHECK(val != 3, "inner3", "got %d != exp %d\n", val,
[all...]
/linux-master/drivers/net/wireless/intel/iwlwifi/
H A Diwl-devtrace-io.h18 TP_PROTO(const struct device *dev, u32 offs, u32 val),
19 TP_ARGS(dev, offs, val),
23 __field(u32, val)
28 __entry->val = val;
31 __get_str(dev), __entry->offs, __entry->val)
35 TP_PROTO(const struct device *dev, u32 offs, u8 val),
36 TP_ARGS(dev, offs, val),
40 __field(u8, val)
45 __entry->val
[all...]
/linux-master/include/linux/
H A Diopoll.h20 * @val: Variable to read the value into
21 * @cond: Break condition (usually involving @val)
30 * case, the last read value at @args is stored in @val. Must not
36 #define read_poll_timeout(op, val, cond, sleep_us, timeout_us, \
46 (val) = op(args); \
51 (val) = op(args); \
65 * @val: Variable to read the value into
66 * @cond: Break condition (usually involving @val)
75 * case, the last read value at @args is stored in @val.
84 #define read_poll_timeout_atomic(op, val, con
[all...]
/linux-master/arch/x86/kernel/cpu/mce/
H A Dintel.c140 u64 val; local
143 rdmsrl(MSR_IA32_MCx_CTL2(bank), val); local
144 val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK;
145 wrmsrl(MSR_IA32_MCx_CTL2(bank), val | thresh);
175 static bool cmci_skip_bank(int bank, u64 *val) argument
186 rdmsrl(MSR_IA32_MCx_CTL2(bank), *val);
189 if (*val & MCI_CTL2_CMCI_EN) {
205 static u64 cmci_pick_threshold(u64 val, int *bios_zero_thresh) argument
207 if ((val & MCI_CTL2_CMCI_THRESHOLD_MASK) == CMCI_STORM_THRESHOLD)
208 return val;
229 cmci_claim_bank(int bank, u64 val, int bios_zero_thresh, int *bios_wrong_thresh) argument
234 wrmsrl(MSR_IA32_MCx_CTL2(bank), val); local
235 rdmsrl(MSR_IA32_MCx_CTL2(bank), val); local
284 u64 val; local
322 u64 val; local
328 wrmsrl(MSR_IA32_MCx_CTL2(bank), val); local
427 u64 val; local
440 u64 val; local
[all...]
/linux-master/drivers/net/ethernet/chelsio/cxgb/
H A Dmv88x201x.c112 u32 val; local
116 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_RXSTAT, &val);
117 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_TXSTAT, &val);
118 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT, &val);
123 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);
127 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_STAT1, &val);
129 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT, &val);
133 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_RXSTAT, &val);
134 cphy_mdio_read(cphy, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_TXSTAT, &val);
165 u32 val local
205 u32 val; local
229 u32 val; local
[all...]
/linux-master/drivers/phy/qualcomm/
H A Dphy-qcom-pcie2.c72 u32 val; local
75 val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
76 val &= ~BIT(1);
77 writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
82 val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
83 val &= ~BIT(0);
84 writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
87 val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3);
88 val |= BIT(0);
89 writel(val, qph
175 u32 val; local
[all...]
/linux-master/drivers/clk/mmp/
H A Dpwr-island.c30 u32 val; local
35 val = readl(pm_domain->reg);
38 val |= pm_domain->power_on;
39 writel(val, pm_domain->reg);
42 val |= 0x100;
43 writel(val, pm_domain->reg);
47 u32 after_power_on = val;
49 val &= ~pm_domain->reset;
50 writel(val, pm_domain->reg);
52 val |
71 u32 val; local
[all...]
/linux-master/samples/bpf/
H A Dibumad_kern.c80 u64 zero = 0, *val; local
85 val = bpf_map_lookup_elem(&read_count, &class);
86 if (!val) {
88 val = bpf_map_lookup_elem(&read_count, &class);
89 if (!val)
93 (*val) += 1;
100 u64 zero = 0, *val; local
105 val = bpf_map_lookup_elem(&read_count, &class);
106 if (!val) {
108 val
120 u64 zero = 0, *val; local
[all...]
/linux-master/drivers/misc/mei/
H A Dmei-trace.h20 TP_PROTO(const struct device *dev, const char *reg, u32 offs, u32 val),
21 TP_ARGS(dev, reg, offs, val),
26 __field(u32, val)
32 __entry->val = val;
35 __get_str(dev), __entry->reg, __entry->offs, __entry->val)
39 TP_PROTO(const struct device *dev, const char *reg, u32 offs, u32 val),
40 TP_ARGS(dev, reg, offs, val),
45 __field(u32, val)
51 __entry->val
[all...]
/linux-master/arch/powerpc/boot/
H A Dio.h21 static inline void out_8(volatile unsigned char *addr, int val) argument
24 : "=m" (*addr) : "r" (val));
46 static inline void out_le16(volatile u16 *addr, int val) argument
49 : "r" (val), "r" (addr));
52 static inline void out_be16(volatile u16 *addr, int val) argument
55 : "=m" (*addr) : "r" (val));
76 static inline void out_le32(volatile unsigned *addr, int val) argument
79 : "r" (val), "r" (addr));
82 static inline void out_be32(volatile unsigned *addr, int val) argument
85 : "=m" (*addr) : "r" (val));
[all...]
/linux-master/drivers/infiniband/hw/mthca/
H A Dmthca_doorbell.h54 static inline void mthca_write64_raw(__be64 val, void __iomem *dest) argument
56 __raw_writeq((__force u64) val, dest);
65 static inline void mthca_write_db_rec(__be32 val[2], __be32 *db) argument
67 *(u64 *) db = *(u64 *) val;
82 static inline void mthca_write64_raw(__be64 val, void __iomem *dest) argument
84 __raw_writel(((__force u32 *) &val)[0], dest);
85 __raw_writel(((__force u32 *) &val)[1], dest + 4);
102 static inline void mthca_write_db_rec(__be32 val[2], __be32 *db) argument
104 db[0] = val[0];
106 db[1] = val[
[all...]
/linux-master/arch/sh/include/asm/
H A Dwatchdog.h73 * @val: Value to write
75 * Writes the given value @val to the lower byte of the timer counter.
78 static inline void sh_wdt_write_cnt(__u32 val) argument
80 __raw_writel((WTCNT_HIGH << 24) | (__u32)val, WTCNT);
85 * @val: Value to write
87 * Writes the given value @val to the lower byte of the timer counter.
90 static inline void sh_wdt_write_bst(__u32 val) argument
92 __raw_writel((WTBST_HIGH << 24) | (__u32)val, WTBST);
106 * @val: Value to write
108 * Writes the given value @val t
111 sh_wdt_write_csr(__u32 val) argument
132 sh_wdt_write_cnt(__u8 val) argument
154 sh_wdt_write_csr(__u8 val) argument
[all...]

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