cpu/mce/intel.c

140 	u64 val;
143 	rdmsrl(MSR_IA32_MCx_CTL2(bank), val);
144 	val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK;
145 	wrmsrl(MSR_IA32_MCx_CTL2(bank), val | thresh);
175 static bool cmci_skip_bank(int bank, u64 *val)
186 	rdmsrl(MSR_IA32_MCx_CTL2(bank), *val);
189 	if (*val & MCI_CTL2_CMCI_EN) {
205 static u64 cmci_pick_threshold(u64 val, int *bios_zero_thresh)
207 	if ((val & MCI_CTL2_CMCI_THRESHOLD_MASK) == CMCI_STORM_THRESHOLD)
208 		return val;
211 		val &= ~MCI_CTL2_CMCI_THRESHOLD_MASK;
212 		val |= CMCI_THRESHOLD;
213 	} else if (!(val & MCI_CTL2_CMCI_THRESHOLD_MASK)) {
220 		val |= CMCI_THRESHOLD;
223 	return val;
229 static void cmci_claim_bank(int bank, u64 val, int bios_zero_thresh, int *bios_wrong_thresh)
233 	val |= MCI_CTL2_CMCI_EN;
234 	wrmsrl(MSR_IA32_MCx_CTL2(bank), val);
235 	rdmsrl(MSR_IA32_MCx_CTL2(bank), val);
238 	if (!(val & MCI_CTL2_CMCI_EN)) {
247 	if ((val & MCI_CTL2_CMCI_THRESHOLD_MASK) == CMCI_STORM_THRESHOLD) {
262 	    (val & MCI_CTL2_CMCI_THRESHOLD_MASK))
267 		cmci_threshold[bank] = val & MCI_CTL2_CMCI_THRESHOLD_MASK;
284 		u64 val;
287 		if (cmci_skip_bank(i, &val))
290 		val = cmci_pick_threshold(val, &bios_zero_thresh);
291 		cmci_claim_bank(i, val, bios_zero_thresh, &bios_wrong_thresh);
322 	u64 val;
326 	rdmsrl(MSR_IA32_MCx_CTL2(bank), val);
327 	val &= ~MCI_CTL2_CMCI_EN;
328 	wrmsrl(MSR_IA32_MCx_CTL2(bank), val);
331 	if ((val & MCI_CTL2_CMCI_THRESHOLD_MASK) == CMCI_STORM_THRESHOLD)
427 	u64 val;
432 	rdmsrl(MSR_IA32_MCG_EXT_CTL, val);
434 	if (!(val & MCG_EXT_CTL_LMCE_EN))
435 		wrmsrl(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN);
440 	u64 val;
445 	rdmsrl(MSR_IA32_MCG_EXT_CTL, val);
446 	val &= ~MCG_EXT_CTL_LMCE_EN;
447 	wrmsrl(MSR_IA32_MCG_EXT_CTL, val);