/linux-master/drivers/gpu/drm/amd/display/dc/inc/ |
H A D | core_types.h | 48 uint32_t controller_id); 368 uint32_t enable : 1; 369 uint32_t disable : 1; 370 uint32_t odm : 1; 371 uint32_t global_sync : 1; 372 uint32_t opp_changed : 1; 373 uint32_t tg_changed : 1; 374 uint32_t mpcc : 1; 375 uint32_t dppclk : 1; 376 uint32_t hubp_interdependen [all...] |
/linux-master/arch/x86/pci/ |
H A D | olpc.c | 41 static const uint32_t lxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */ 54 static const uint32_t gxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */ 67 static const uint32_t lxfb_hdr[] = { /* dev 1 function 1 - devfn = 9 */ 80 static const uint32_t gxfb_hdr[] = { /* dev 1 function 1 - devfn = 9 */ 93 static const uint32_t aes_hdr[] = { /* dev 1 function 2 - devfn = 0xa */ 107 static const uint32_t isa_hdr[] = { /* dev f function 0 - devfn = 78 */ 120 static const uint32_t ac97_hdr[] = { /* dev f function 3 - devfn = 7b */ 133 static const uint32_t ohci_hdr[] = { /* dev f function 4 - devfn = 7c */ 147 static const uint32_t ehci_hdr[] = { /* dev f function 4 - devfn = 7d */ 162 static uint32_t ff_lo [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dce/ |
H A D | dce_mem_input.c | 165 uint32_t wm_select, 166 uint32_t urgency_low_wm, 167 uint32_t urgency_high_wm) 180 uint32_t wm_select, 181 uint32_t urgency_low_wm, 182 uint32_t urgency_high_wm) 195 uint32_t wm_select, 196 uint32_t urgency_low_wm, 197 uint32_t urgency_high_wm) 215 uint32_t wm_selec [all...] |
H A D | dce_panel_cntl.c | 52 uint32_t bl_period, bl_int_count; 53 uint32_t bl_pwm, fractional_duty_cycle_en; 54 uint32_t bl_period_mask, bl_pwm_mask; 62 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm)); 86 return (uint32_t)(current_backlight); 89 static uint32_t dce_panel_cntl_hw_init(struct panel_cntl *panel_cntl) 92 uint32_t value; 93 uint32_t current_backlight; 150 uint32_t blon, blon_ovrd, pwrseq_target_state; 164 uint32_t pwr_seq_stat [all...] |
H A D | dce_mem_input.h | 111 uint32_t GRPH_ENABLE; 112 uint32_t GRPH_CONTROL; 113 uint32_t GRPH_X_START; 114 uint32_t GRPH_Y_START; 115 uint32_t GRPH_X_END; 116 uint32_t GRPH_Y_END; 117 uint32_t GRPH_PITCH; 118 uint32_t HW_ROTATION; 119 uint32_t GRPH_SWAP_CNTL; 120 uint32_t PRESCALE_GRPH_CONTRO [all...] |
/linux-master/drivers/gpu/drm/vmwgfx/ |
H A D | vmwgfx_drv.h | 205 uint32_t *image; 271 uint32_t capabilities; 289 uint32_t handle; 408 uint32_t *cmd_bounce; 409 uint32_t cmd_bounce_size; 413 uint32_t *buf_start; 486 uint32_t fb_max_width; 487 uint32_t fb_max_height; 488 uint32_t texture_max_width; 489 uint32_t texture_max_heigh [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dcn20/ |
H A D | dcn20_mmhubbub.h | 415 uint32_t MCIF_WB_BUFMGR_SW_CONTROL;\ 416 uint32_t MCIF_WB_BUFMGR_CUR_LINE_R;\ 417 uint32_t MCIF_WB_BUFMGR_STATUS;\ 418 uint32_t MCIF_WB_BUF_PITCH;\ 419 uint32_t MCIF_WB_BUF_1_STATUS;\ 420 uint32_t MCIF_WB_BUF_1_STATUS2;\ 421 uint32_t MCIF_WB_BUF_2_STATUS;\ 422 uint32_t MCIF_WB_BUF_2_STATUS2;\ 423 uint32_t MCIF_WB_BUF_3_STATUS;\ 424 uint32_t MCIF_WB_BUF_3_STATUS [all...] |
/linux-master/drivers/scsi/megaraid/ |
H A D | mbox_defs.h | 161 uint32_t lba; 162 uint32_t xferaddr; 186 uint32_t xferaddr_lo; 187 uint32_t xferaddr_hi; 242 uint32_t dataxferaddr; 243 uint32_t dataxferlen; 248 uint32_t dataxferaddr_lo; 249 uint32_t dataxferaddr_hi; 298 uint32_t dataxferaddr; 299 uint32_t dataxferle [all...] |
/linux-master/scripts/dtc/libfdt/ |
H A D | libfdt.h | 127 uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset); 141 static inline uint32_t fdt32_ld(const fdt32_t *p) 145 return ((uint32_t)bp[0] << 24) 146 | ((uint32_t)bp[1] << 16) 147 | ((uint32_t)bp[2] << 8) 151 static inline void fdt32_st(void *property, uint32_t value) 261 static inline void fdt_set_##name(void *fdt, uint32_t val) \ 292 size_t fdt_header_size_(uint32_t version); 381 int fdt_find_max_phandle(const void *fdt, uint32_t *phandle); 398 static inline uint32_t fdt_get_max_phandl [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/dce110/ |
H A D | dce110_timing_generator.c | 94 uint32_t addr = 0; 95 uint32_t value = 0; 96 uint32_t field = 0; 107 uint32_t early_cntl) 109 uint32_t regval; 111 uint32_t address = CRTC_REG(mmCRTC_CONTROL); 128 uint32_t value = 0; 156 uint32_t addr = CRTC_REG(mmCRTC_BLACK_COLOR); 157 uint32_t value = dm_read_reg(tg->ctx, addr); 192 uint32_t add [all...] |
H A D | dce110_compressor.c | 65 static uint32_t align_to_chunks_number_per_line(uint32_t pixels) 70 static void reset_lb_on_vblank(struct compressor *compressor, uint32_t crtc_inst) 72 uint32_t value; 73 uint32_t frame_count; 74 uint32_t status_pos; 75 uint32_t retry = 0; 114 uint32_t counter = 0; 115 uint32_t addr = mmFBC_STATUS; 116 uint32_t valu [all...] |
/linux-master/scripts/mod/ |
H A D | sumversion.c | 41 uint32_t hash[MD4_HASH_WORDS]; 42 uint32_t block[MD4_BLOCK_WORDS]; 46 static inline uint32_t lshift(uint32_t x, unsigned int s) 52 static inline uint32_t F(uint32_t x, uint32_t y, uint32_t z) 57 static inline uint32_t G(uint32_t [all...] |
/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
H A D | smu7_smumgr.c | 38 static int smu7_set_smc_sram_address(struct pp_hwmgr *hwmgr, uint32_t smc_addr, uint32_t limit) 49 int smu7_copy_bytes_from_smc(struct pp_hwmgr *hwmgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit) 51 uint32_t data; 52 uint32_t addr; 55 uint32_t *pdata = (uint32_t *) [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dce/ |
H A D | dce_hwseq.c | 51 uint32_t lock_val = lock ? 1 : 0; 52 uint32_t dcp_grph, scl, blnd, update_lock_mode, val; 82 uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]); 101 uint32_t feedthrough = 1; 102 uint32_t blnd_mode = 0; 103 uint32_t multiplied_mode = 0; 104 uint32_t alpha_mode = 2; 184 uint32_t rate_source = clk_src->id - CLOCK_SOURCE_COMBO_PHY_PLL0; 194 uint32_t rate_source = clk_src->id - CLOCK_SOURCE_ID_PLL0;
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/linux-master/drivers/gpu/drm/radeon/ |
H A D | radeon_bios.c | 295 uint32_t viph_control; 296 uint32_t bus_cntl; 297 uint32_t d1vga_control; 298 uint32_t d2vga_control; 299 uint32_t vga_render_control; 300 uint32_t rom_cntl; 301 uint32_t cg_spll_func_cntl = 0; 302 uint32_t cg_spll_status; 364 uint32_t viph_control; 365 uint32_t bus_cnt [all...] |
/linux-master/drivers/scsi/qla2xxx/ |
H A D | qla_edif_bsg.h | 27 uint32_t extra_rx_xchg_address; 45 uint32_t rx_xchg_address; 59 uint32_t host_support_edif; 60 uint32_t edif_enode_active; 61 uint32_t edif_edb_active; 83 uint32_t prli_status; 178 uint32_t salt; 179 uint32_t spi; 218 uint32_t event_code; 219 uint32_t event_data_siz [all...] |
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn10/ |
H A D | dcn10_optc.c | 107 uint32_t start_line, 108 uint32_t end_line) 119 uint32_t start_line) 129 uint32_t start_line) 164 uint32_t asic_blank_end; 165 uint32_t asic_blank_start; 166 uint32_t v_total; 167 uint32_t v_sync_end; 168 uint32_t h_sync_polarity, v_sync_polarity; 169 uint32_t start_poin [all...] |
/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
H A D | smu7_thermal.c | 55 uint32_t *speed) 57 uint32_t duty100; 58 uint32_t duty; 75 *speed = min_t(uint32_t, tmp64, 255); 80 int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) 82 uint32_t tach_period; 83 uint32_t crystal_clock_freq; 108 int smu7_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode) 204 uint32_t speed) 206 uint32_t duty10 [all...] |
H A D | smu_helper.c | 48 uint32_t **pptable_info_array, 49 const uint32_t *pptable_array, 50 uint32_t power_saving_clock_count) 52 uint32_t array_size, i; 53 uint32_t *table; 55 array_size = sizeof(uint32_t) * power_saving_clock_count; 70 uint32_t **pptable_info_array, 71 const uint32_t *pptable_array, 72 uint32_t od_setting_count) 74 uint32_t array_siz [all...] |
/linux-master/drivers/scsi/isci/ |
H A D | probe_roms.h | 314 uint32_t high; 315 uint32_t low; 318 uint32_t afe_tx_amp_control0; 319 uint32_t afe_tx_amp_control1; 320 uint32_t afe_tx_amp_control2; 321 uint32_t afe_tx_amp_control3;
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/linux-master/drivers/mtd/parsers/ |
H A D | parser_trx.c | 20 uint32_t magic; 21 uint32_t length; 22 uint32_t crc32; 25 uint32_t offset[3]; 31 uint32_t buf; 60 uint32_t trx_magic = TRX_MAGIC;
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/ |
H A D | dcn30_vpg.c | 48 uint32_t packet_index, 53 uint32_t i; 58 uint32_t max_retries = 50; 99 const uint32_t *content = 100 (const uint32_t *) &info_packet->sb[0]; 251 uint32_t inst,
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/linux-master/arch/powerpc/platforms/pseries/ |
H A D | hvcserver.c | 82 static int hvcs_next_partner(uint32_t unit_address, 119 int hvcs_get_partner_info(uint32_t unit_address, struct list_head *head, 124 * values are uint32_t. 213 int hvcs_register_connection( uint32_t unit_address, 214 uint32_t p_partition_ID, uint32_t p_unit_address) 233 int hvcs_free_connection(uint32_t unit_address)
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/linux-master/drivers/gpu/drm/amd/display/dc/irq/ |
H A D | irq_service.c | 90 uint32_t addr = info->enable_reg; 91 uint32_t value = dm_read_reg(irq_service->ctx, addr); 134 uint32_t addr = info->ack_reg; 135 uint32_t value = dm_read_reg(irq_service->ctx, addr); 172 uint32_t src_id, 173 uint32_t ext_id)
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/linux-master/arch/arm/boot/compressed/ |
H A D | fdt_check_mem_start.c | 25 static uint32_t get_cells(const void *fdt, const char *name) 37 static uint64_t get_val(const fdt32_t *cells, uint32_t ncells) 64 uint32_t fdt_check_mem_start(uint32_t mem_start, const void *fdt) 66 uint32_t addr_cells, size_cells, usable_base, base; 67 uint32_t fdt_mem_start = 0xffffffff;
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