Searched refs:sclk (Results 101 - 125 of 157) sorted by last modified time

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/linux-master/drivers/i2c/busses/
H A Di2c-emev2.c70 struct clk *sclk; member in struct:em_i2c_device
376 priv->sclk = devm_clk_get(&pdev->dev, "sclk");
377 if (IS_ERR(priv->sclk))
378 return PTR_ERR(priv->sclk);
380 ret = clk_prepare_enable(priv->sclk);
418 clk_disable_unprepare(priv->sclk);
427 clk_disable_unprepare(priv->sclk);
/linux-master/sound/soc/cirrus/
H A Dep93xx-i2s.c76 struct clk *sclk; member in struct:ep93xx_i2s_info
116 clk_prepare_enable(info->sclk);
161 clk_disable_unprepare(info->sclk);
354 err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv);
358 err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv);
474 info->sclk = clk_get(&pdev->dev, "sclk");
475 if (IS_ERR(info->sclk)) {
476 err = PTR_ERR(info->sclk);
502 clk_put(info->sclk);
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/linux-master/drivers/net/ethernet/marvell/octeontx2/af/
H A Dptp.h29 void ptp_start(struct rvu *rvu, u64 sclk, u32 ext_clk_freq, u32 extts);
/linux-master/drivers/gpu/drm/radeon/
H A Dsislands_smc.h148 SISLANDS_SMC_SCLK_VALUE sclk; member in struct:SISLANDS_SMC_HW_PERFORMANCE_LEVEL
H A Dradeon_kms.c535 *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
586 /* get sclk in Mhz */
H A Drv740_dpm.c120 RV770_SMC_SCLK_VALUE *sclk)
175 sclk->sclk_value = cpu_to_be32(engine_clock);
176 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
177 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
178 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
179 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum);
180 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2);
385 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
386 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
387 table->ACPIState.levels[0].sclk
119 rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, RV770_SMC_SCLK_VALUE *sclk) argument
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H A Dcypress_dpm.c694 ret = rv740_populate_sclk_value(rdev, pl->sclk, &level->sclk);
728 pl->sclk,
735 pl->sclk,
936 new_state->low.sclk,
939 new_state->medium.sclk,
942 new_state->high.sclk,
1267 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
1269 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
1271 table->initialState.levels[0].sclk
[all...]
/linux-master/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dcyan_skillfish_ppt.c57 uint32_t sclk; member in struct:gfx_user_settings
374 * cyan_skillfish specific, query default sclk inseted of hard code.
454 dev_err(smu->adev->dev, "Invalid sclk! Valid sclk range: %uMHz - %uMhz\n",
466 cyan_skillfish_user_settings.sclk = input[1];
476 cyan_skillfish_user_settings.sclk = cyan_skillfish_sclk_default;
486 if (cyan_skillfish_user_settings.sclk < CYAN_SKILLFISH_SCLK_MIN ||
487 cyan_skillfish_user_settings.sclk > CYAN_SKILLFISH_SCLK_MAX) {
488 dev_err(smu->adev->dev, "Invalid sclk! Valid sclk rang
[all...]
/linux-master/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dtonga_smumgr.c260 /* find first sclk bigger than request */
286 /* sclk is bigger than max sclk in the dependence table */
539 uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk)
606 sclk->SclkFrequency = engine_clock;
607 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
608 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
609 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
610 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
611 sclk
538 tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr, uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk) argument
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H A Dfiji_smumgr.c367 /* find first sclk bigger than request */
396 /* sclk is bigger than max sclk in the dependence table */
856 uint32_t clock, struct SMU73_Discrete_GraphicsLevel *sclk)
926 sclk->SclkFrequency = clock;
927 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
928 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
929 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
930 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
931 sclk
855 fiji_calculate_sclk_params(struct pp_hwmgr *hwmgr, uint32_t clock, struct SMU73_Discrete_GraphicsLevel *sclk) argument
[all...]
/linux-master/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega10_processpptables.c835 limits->sclk = le32_to_cpu(limit_table->entries[0].ulSOCCLKLimit);
992 hwmgr->dyn_state.max_clock_voltage_on_dc.sclk =
993 pp_table_info->max_clock_voltage_on_dc.sclk;
H A Dsmu_helper.h89 uint16_t virtual_voltage_id, int32_t *sclk);
95 uint32_t sclk, uint16_t id, uint16_t *voltage);
H A Dsmu_helper.c462 uint16_t virtual_voltage_id, int32_t *sclk)
483 *sclk = table_info->vdd_dep_on_sclk->entries[entry_id].clk;
583 uint32_t sclk, uint16_t id, uint16_t *voltage)
591 ret = atomctrl_get_voltage_evv_on_sclk(hwmgr, voltage_type, sclk, id, voltage);
595 ret = atomctrl_get_voltage_evv_on_sclk_ai(hwmgr, voltage_type, sclk, id, &vol);
460 phm_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table, uint16_t virtual_voltage_id, int32_t *sclk) argument
582 phm_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t id, uint16_t *voltage) argument
H A Dsmu10_hwmgr.c986 pr_info("Currently sclk only support 3 levels on RV\n");
1297 uint32_t sclk, mclk, activity_percent; local
1313 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &sclk);
1315 *((uint32_t *)value) = sclk * 100;
1555 pr_err("Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
1563 pr_err("Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
1588 pr_err("The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
H A Dprocesspptables.c430 limits->sclk = ((unsigned long)table->entries[0].ucSclkHigh << 16) |
H A Dppatomctrl.h294 extern int atomctrl_get_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage);
320 uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug);
325 uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage);
H A Dhwmgr.c245 if ((hwmgr->dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
/linux-master/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsislands_smc.h144 SISLANDS_SMC_SCLK_VALUE sclk; member in struct:SISLANDS_SMC_HW_PERFORMANCE_LEVEL
/linux-master/drivers/clk/ralink/
H A Dclk-mt7621.c134 struct mt7621_gate *sclk)
145 .parent_names = &sclk->parent_name,
147 .name = sclk->name,
150 sclk->hw.init = &init;
151 return devm_clk_hw_register(dev, &sclk->hw);
159 struct mt7621_gate *sclk; local
163 sclk = &mt7621_gates[i];
164 sclk->priv = priv;
165 ret = mt7621_gate_ops_init(dev, sclk);
167 dev_err(dev, "Couldn't register clock %s\n", sclk
133 mt7621_gate_ops_init(struct device *dev, struct mt7621_gate *sclk) argument
204 struct mt7621_fixed_clk *sclk; local
322 struct mt7621_clk *sclk; local
397 struct mt7621_clk *sclk = &mt7621_clks_base[i]; local
551 struct mt7621_gate *sclk = &mt7621_gates[i]; local
558 struct mt7621_fixed_clk *sclk = &mt7621_fixed_clks[i]; local
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/linux-master/drivers/clk/
H A Dclk-scpi.c139 struct scpi_clk *sclk, const char *name)
149 sclk->hw.init = &init;
150 sclk->scpi_ops = get_scpi_ops();
153 sclk->info = sclk->scpi_ops->dvfs_get_info(sclk->id);
154 if (IS_ERR(sclk->info))
155 return PTR_ERR(sclk->info);
157 if (sclk->scpi_ops->clk_get_range(sclk
138 scpi_clk_ops_init(struct device *dev, const struct of_device_id *match, struct scpi_clk *sclk, const char *name) argument
177 struct scpi_clk *sclk; local
213 struct scpi_clk *sclk; local
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H A Dclk-lmk04832.c243 * @sclk: reference to the internal sysref clock (SCLK)
262 struct clk_hw sclk; member in struct:lmk04832
714 /** lmk04832_sclk_sync - Establish deterministic phase relationship between sclk
846 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
859 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
867 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
876 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
894 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
915 struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
958 init.name = "lmk-sclk";
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dpower_state.h177 unsigned long sclk; member in struct:pp_clock_engine_request
/linux-master/sound/soc/codecs/
H A Drk3328_codec.c37 unsigned int sclk; member in struct:rk3328_codec_priv
/linux-master/drivers/video/fbdev/aty/
H A Datyfb.h52 int sclk, mclk, mclk_pm, xclk; member in struct:pll_info
/linux-master/drivers/gpu/drm/amd/display/dc/
H A Ddm_services_types.h63 struct dm_pp_clock_range sclk; member in struct:dm_pp_gpu_clock_range

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