1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * linux/sound/soc/ep93xx-i2s.c 4 * EP93xx I2S driver 5 * 6 * Copyright (C) 2010 Ryan Mallon 7 * 8 * Based on the original driver by: 9 * Copyright (C) 2007 Chase Douglas <chasedouglas@gmail> 10 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> 11 */ 12 13#include <linux/module.h> 14#include <linux/init.h> 15#include <linux/slab.h> 16#include <linux/clk.h> 17#include <linux/io.h> 18#include <linux/of.h> 19 20#include <sound/core.h> 21#include <sound/dmaengine_pcm.h> 22#include <sound/pcm.h> 23#include <sound/pcm_params.h> 24#include <sound/initval.h> 25#include <sound/soc.h> 26 27#include <linux/platform_data/dma-ep93xx.h> 28#include <linux/soc/cirrus/ep93xx.h> 29 30#include "ep93xx-pcm.h" 31 32#define EP93XX_I2S_TXCLKCFG 0x00 33#define EP93XX_I2S_RXCLKCFG 0x04 34#define EP93XX_I2S_GLSTS 0x08 35#define EP93XX_I2S_GLCTRL 0x0C 36 37#define EP93XX_I2S_I2STX0LFT 0x10 38#define EP93XX_I2S_I2STX0RT 0x14 39 40#define EP93XX_I2S_TXLINCTRLDATA 0x28 41#define EP93XX_I2S_TXCTRL 0x2C 42#define EP93XX_I2S_TXWRDLEN 0x30 43#define EP93XX_I2S_TX0EN 0x34 44 45#define EP93XX_I2S_RXLINCTRLDATA 0x58 46#define EP93XX_I2S_RXCTRL 0x5C 47#define EP93XX_I2S_RXWRDLEN 0x60 48#define EP93XX_I2S_RX0EN 0x64 49 50#define EP93XX_I2S_WRDLEN_16 (0 << 0) 51#define EP93XX_I2S_WRDLEN_24 (1 << 0) 52#define EP93XX_I2S_WRDLEN_32 (2 << 0) 53 54#define EP93XX_I2S_RXLINCTRLDATA_R_JUST BIT(1) /* Right justify */ 55 56#define EP93XX_I2S_TXLINCTRLDATA_R_JUST BIT(2) /* Right justify */ 57 58/* 59 * Transmit empty interrupt level select: 60 * 0 - Generate interrupt when FIFO is half empty 61 * 1 - Generate interrupt when FIFO is empty 62 */ 63#define EP93XX_I2S_TXCTRL_TXEMPTY_LVL BIT(0) 64#define EP93XX_I2S_TXCTRL_TXUFIE BIT(1) /* Transmit interrupt enable */ 65 66#define EP93XX_I2S_CLKCFG_LRS (1 << 0) /* lrclk polarity */ 67#define EP93XX_I2S_CLKCFG_CKP (1 << 1) /* Bit clock polarity */ 68#define EP93XX_I2S_CLKCFG_REL (1 << 2) /* First bit transition */ 69#define EP93XX_I2S_CLKCFG_MASTER (1 << 3) /* Master mode */ 70#define EP93XX_I2S_CLKCFG_NBCG (1 << 4) /* Not bit clock gating */ 71 72#define EP93XX_I2S_GLSTS_TX0_FIFO_FULL BIT(12) 73 74struct ep93xx_i2s_info { 75 struct clk *mclk; 76 struct clk *sclk; 77 struct clk *lrclk; 78 void __iomem *regs; 79 struct snd_dmaengine_dai_dma_data dma_params_rx; 80 struct snd_dmaengine_dai_dma_data dma_params_tx; 81}; 82 83static struct ep93xx_dma_data ep93xx_i2s_dma_data[] = { 84 [SNDRV_PCM_STREAM_PLAYBACK] = { 85 .name = "i2s-pcm-out", 86 .port = EP93XX_DMA_I2S1, 87 .direction = DMA_MEM_TO_DEV, 88 }, 89 [SNDRV_PCM_STREAM_CAPTURE] = { 90 .name = "i2s-pcm-in", 91 .port = EP93XX_DMA_I2S1, 92 .direction = DMA_DEV_TO_MEM, 93 }, 94}; 95 96static inline void ep93xx_i2s_write_reg(struct ep93xx_i2s_info *info, 97 unsigned reg, unsigned val) 98{ 99 __raw_writel(val, info->regs + reg); 100} 101 102static inline unsigned ep93xx_i2s_read_reg(struct ep93xx_i2s_info *info, 103 unsigned reg) 104{ 105 return __raw_readl(info->regs + reg); 106} 107 108static void ep93xx_i2s_enable(struct ep93xx_i2s_info *info, int stream) 109{ 110 unsigned base_reg; 111 112 if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 && 113 (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) { 114 /* Enable clocks */ 115 clk_prepare_enable(info->mclk); 116 clk_prepare_enable(info->sclk); 117 clk_prepare_enable(info->lrclk); 118 119 /* Enable i2s */ 120 ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 1); 121 } 122 123 /* Enable fifo */ 124 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 125 base_reg = EP93XX_I2S_TX0EN; 126 else 127 base_reg = EP93XX_I2S_RX0EN; 128 ep93xx_i2s_write_reg(info, base_reg, 1); 129 130 /* Enable TX IRQs (FIFO empty or underflow) */ 131 if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG) && 132 stream == SNDRV_PCM_STREAM_PLAYBACK) 133 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCTRL, 134 EP93XX_I2S_TXCTRL_TXEMPTY_LVL | 135 EP93XX_I2S_TXCTRL_TXUFIE); 136} 137 138static void ep93xx_i2s_disable(struct ep93xx_i2s_info *info, int stream) 139{ 140 unsigned base_reg; 141 142 /* Disable IRQs */ 143 if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG) && 144 stream == SNDRV_PCM_STREAM_PLAYBACK) 145 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCTRL, 0); 146 147 /* Disable fifo */ 148 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 149 base_reg = EP93XX_I2S_TX0EN; 150 else 151 base_reg = EP93XX_I2S_RX0EN; 152 ep93xx_i2s_write_reg(info, base_reg, 0); 153 154 if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 && 155 (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) { 156 /* Disable i2s */ 157 ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 0); 158 159 /* Disable clocks */ 160 clk_disable_unprepare(info->lrclk); 161 clk_disable_unprepare(info->sclk); 162 clk_disable_unprepare(info->mclk); 163 } 164} 165 166/* 167 * According to documentation I2S controller can handle underflow conditions 168 * just fine, but in reality the state machine is sometimes confused so that 169 * the whole stream is shifted by one byte. The watchdog below disables the TX 170 * FIFO, fills the buffer with zeroes and re-enables the FIFO. State machine 171 * is being reset and by filling the buffer we get some time before next 172 * underflow happens. 173 */ 174static irqreturn_t ep93xx_i2s_interrupt(int irq, void *dev_id) 175{ 176 struct ep93xx_i2s_info *info = dev_id; 177 178 /* Disable FIFO */ 179 ep93xx_i2s_write_reg(info, EP93XX_I2S_TX0EN, 0); 180 /* 181 * Fill TX FIFO with zeroes, this way we can defer next IRQs as much as 182 * possible and get more time for DMA to catch up. Actually there are 183 * only 8 samples in this FIFO, so even on 8kHz maximum deferral here is 184 * 1ms. 185 */ 186 while (!(ep93xx_i2s_read_reg(info, EP93XX_I2S_GLSTS) & 187 EP93XX_I2S_GLSTS_TX0_FIFO_FULL)) { 188 ep93xx_i2s_write_reg(info, EP93XX_I2S_I2STX0LFT, 0); 189 ep93xx_i2s_write_reg(info, EP93XX_I2S_I2STX0RT, 0); 190 } 191 /* Re-enable FIFO */ 192 ep93xx_i2s_write_reg(info, EP93XX_I2S_TX0EN, 1); 193 194 return IRQ_HANDLED; 195} 196 197static int ep93xx_i2s_dai_probe(struct snd_soc_dai *dai) 198{ 199 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai); 200 201 info->dma_params_tx.filter_data = 202 &ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_PLAYBACK]; 203 info->dma_params_rx.filter_data = 204 &ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_CAPTURE]; 205 206 snd_soc_dai_init_dma_data(dai, &info->dma_params_tx, 207 &info->dma_params_rx); 208 209 return 0; 210} 211 212static int ep93xx_i2s_startup(struct snd_pcm_substream *substream, 213 struct snd_soc_dai *dai) 214{ 215 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai); 216 217 ep93xx_i2s_enable(info, substream->stream); 218 219 return 0; 220} 221 222static void ep93xx_i2s_shutdown(struct snd_pcm_substream *substream, 223 struct snd_soc_dai *dai) 224{ 225 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai); 226 227 ep93xx_i2s_disable(info, substream->stream); 228} 229 230static int ep93xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, 231 unsigned int fmt) 232{ 233 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai); 234 unsigned int clk_cfg; 235 unsigned int txlin_ctrl = 0; 236 unsigned int rxlin_ctrl = 0; 237 238 clk_cfg = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXCLKCFG); 239 240 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 241 case SND_SOC_DAIFMT_I2S: 242 clk_cfg |= EP93XX_I2S_CLKCFG_REL; 243 break; 244 245 case SND_SOC_DAIFMT_LEFT_J: 246 clk_cfg &= ~EP93XX_I2S_CLKCFG_REL; 247 break; 248 249 case SND_SOC_DAIFMT_RIGHT_J: 250 clk_cfg &= ~EP93XX_I2S_CLKCFG_REL; 251 rxlin_ctrl |= EP93XX_I2S_RXLINCTRLDATA_R_JUST; 252 txlin_ctrl |= EP93XX_I2S_TXLINCTRLDATA_R_JUST; 253 break; 254 255 default: 256 return -EINVAL; 257 } 258 259 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 260 case SND_SOC_DAIFMT_BP_FP: 261 /* CPU is provider */ 262 clk_cfg |= EP93XX_I2S_CLKCFG_MASTER; 263 break; 264 265 case SND_SOC_DAIFMT_BC_FC: 266 /* Codec is provider */ 267 clk_cfg &= ~EP93XX_I2S_CLKCFG_MASTER; 268 break; 269 270 default: 271 return -EINVAL; 272 } 273 274 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 275 case SND_SOC_DAIFMT_NB_NF: 276 /* Negative bit clock, lrclk low on left word */ 277 clk_cfg &= ~(EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_LRS); 278 break; 279 280 case SND_SOC_DAIFMT_NB_IF: 281 /* Negative bit clock, lrclk low on right word */ 282 clk_cfg &= ~EP93XX_I2S_CLKCFG_CKP; 283 clk_cfg |= EP93XX_I2S_CLKCFG_LRS; 284 break; 285 286 case SND_SOC_DAIFMT_IB_NF: 287 /* Positive bit clock, lrclk low on left word */ 288 clk_cfg |= EP93XX_I2S_CLKCFG_CKP; 289 clk_cfg &= ~EP93XX_I2S_CLKCFG_LRS; 290 break; 291 292 case SND_SOC_DAIFMT_IB_IF: 293 /* Positive bit clock, lrclk low on right word */ 294 clk_cfg |= EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_LRS; 295 break; 296 } 297 298 /* Write new register values */ 299 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXCLKCFG, clk_cfg); 300 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCLKCFG, clk_cfg); 301 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXLINCTRLDATA, rxlin_ctrl); 302 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXLINCTRLDATA, txlin_ctrl); 303 return 0; 304} 305 306static int ep93xx_i2s_hw_params(struct snd_pcm_substream *substream, 307 struct snd_pcm_hw_params *params, 308 struct snd_soc_dai *dai) 309{ 310 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai); 311 unsigned word_len, div, sdiv, lrdiv; 312 int err; 313 314 switch (params_format(params)) { 315 case SNDRV_PCM_FORMAT_S16_LE: 316 word_len = EP93XX_I2S_WRDLEN_16; 317 break; 318 319 case SNDRV_PCM_FORMAT_S24_LE: 320 word_len = EP93XX_I2S_WRDLEN_24; 321 break; 322 323 case SNDRV_PCM_FORMAT_S32_LE: 324 word_len = EP93XX_I2S_WRDLEN_32; 325 break; 326 327 default: 328 return -EINVAL; 329 } 330 331 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 332 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXWRDLEN, word_len); 333 else 334 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXWRDLEN, word_len); 335 336 /* 337 * EP93xx I2S module can be setup so SCLK / LRCLK value can be 338 * 32, 64, 128. MCLK / SCLK value can be 2 and 4. 339 * We set LRCLK equal to `rate' and minimum SCLK / LRCLK 340 * value is 64, because our sample size is 32 bit * 2 channels. 341 * I2S standard permits us to transmit more bits than 342 * the codec uses. 343 */ 344 div = clk_get_rate(info->mclk) / params_rate(params); 345 sdiv = 4; 346 if (div > (256 + 512) / 2) { 347 lrdiv = 128; 348 } else { 349 lrdiv = 64; 350 if (div < (128 + 256) / 2) 351 sdiv = 2; 352 } 353 354 err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv); 355 if (err) 356 return err; 357 358 err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv); 359 if (err) 360 return err; 361 362 return 0; 363} 364 365static int ep93xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id, 366 unsigned int freq, int dir) 367{ 368 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai); 369 370 if (dir == SND_SOC_CLOCK_IN || clk_id != 0) 371 return -EINVAL; 372 if (!freq) 373 return 0; 374 375 return clk_set_rate(info->mclk, freq); 376} 377 378#ifdef CONFIG_PM 379static int ep93xx_i2s_suspend(struct snd_soc_component *component) 380{ 381 struct ep93xx_i2s_info *info = snd_soc_component_get_drvdata(component); 382 383 if (!snd_soc_component_active(component)) 384 return 0; 385 386 ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_PLAYBACK); 387 ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_CAPTURE); 388 389 return 0; 390} 391 392static int ep93xx_i2s_resume(struct snd_soc_component *component) 393{ 394 struct ep93xx_i2s_info *info = snd_soc_component_get_drvdata(component); 395 396 if (!snd_soc_component_active(component)) 397 return 0; 398 399 ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_PLAYBACK); 400 ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_CAPTURE); 401 402 return 0; 403} 404#else 405#define ep93xx_i2s_suspend NULL 406#define ep93xx_i2s_resume NULL 407#endif 408 409static const struct snd_soc_dai_ops ep93xx_i2s_dai_ops = { 410 .probe = ep93xx_i2s_dai_probe, 411 .startup = ep93xx_i2s_startup, 412 .shutdown = ep93xx_i2s_shutdown, 413 .hw_params = ep93xx_i2s_hw_params, 414 .set_sysclk = ep93xx_i2s_set_sysclk, 415 .set_fmt = ep93xx_i2s_set_dai_fmt, 416}; 417 418#define EP93XX_I2S_FORMATS (SNDRV_PCM_FMTBIT_S32_LE) 419 420static struct snd_soc_dai_driver ep93xx_i2s_dai = { 421 .symmetric_rate = 1, 422 .playback = { 423 .channels_min = 2, 424 .channels_max = 2, 425 .rates = SNDRV_PCM_RATE_8000_192000, 426 .formats = EP93XX_I2S_FORMATS, 427 }, 428 .capture = { 429 .channels_min = 2, 430 .channels_max = 2, 431 .rates = SNDRV_PCM_RATE_8000_192000, 432 .formats = EP93XX_I2S_FORMATS, 433 }, 434 .ops = &ep93xx_i2s_dai_ops, 435}; 436 437static const struct snd_soc_component_driver ep93xx_i2s_component = { 438 .name = "ep93xx-i2s", 439 .suspend = ep93xx_i2s_suspend, 440 .resume = ep93xx_i2s_resume, 441 .legacy_dai_naming = 1, 442}; 443 444static int ep93xx_i2s_probe(struct platform_device *pdev) 445{ 446 struct ep93xx_i2s_info *info; 447 int err; 448 449 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); 450 if (!info) 451 return -ENOMEM; 452 453 info->regs = devm_platform_ioremap_resource(pdev, 0); 454 if (IS_ERR(info->regs)) 455 return PTR_ERR(info->regs); 456 457 if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG)) { 458 int irq = platform_get_irq(pdev, 0); 459 if (irq <= 0) 460 return irq < 0 ? irq : -ENODEV; 461 462 err = devm_request_irq(&pdev->dev, irq, ep93xx_i2s_interrupt, 0, 463 pdev->name, info); 464 if (err) 465 return err; 466 } 467 468 info->mclk = clk_get(&pdev->dev, "mclk"); 469 if (IS_ERR(info->mclk)) { 470 err = PTR_ERR(info->mclk); 471 goto fail; 472 } 473 474 info->sclk = clk_get(&pdev->dev, "sclk"); 475 if (IS_ERR(info->sclk)) { 476 err = PTR_ERR(info->sclk); 477 goto fail_put_mclk; 478 } 479 480 info->lrclk = clk_get(&pdev->dev, "lrclk"); 481 if (IS_ERR(info->lrclk)) { 482 err = PTR_ERR(info->lrclk); 483 goto fail_put_sclk; 484 } 485 486 dev_set_drvdata(&pdev->dev, info); 487 488 err = devm_snd_soc_register_component(&pdev->dev, &ep93xx_i2s_component, 489 &ep93xx_i2s_dai, 1); 490 if (err) 491 goto fail_put_lrclk; 492 493 err = devm_ep93xx_pcm_platform_register(&pdev->dev); 494 if (err) 495 goto fail_put_lrclk; 496 497 return 0; 498 499fail_put_lrclk: 500 clk_put(info->lrclk); 501fail_put_sclk: 502 clk_put(info->sclk); 503fail_put_mclk: 504 clk_put(info->mclk); 505fail: 506 return err; 507} 508 509static void ep93xx_i2s_remove(struct platform_device *pdev) 510{ 511 struct ep93xx_i2s_info *info = dev_get_drvdata(&pdev->dev); 512 513 clk_put(info->lrclk); 514 clk_put(info->sclk); 515 clk_put(info->mclk); 516} 517 518static const struct of_device_id ep93xx_i2s_of_ids[] = { 519 { .compatible = "cirrus,ep9301-i2s" }, 520 {} 521}; 522MODULE_DEVICE_TABLE(of, ep93xx_i2s_of_ids); 523 524static struct platform_driver ep93xx_i2s_driver = { 525 .probe = ep93xx_i2s_probe, 526 .remove_new = ep93xx_i2s_remove, 527 .driver = { 528 .name = "ep93xx-i2s", 529 .of_match_table = ep93xx_i2s_of_ids, 530 }, 531}; 532 533module_platform_driver(ep93xx_i2s_driver); 534 535MODULE_ALIAS("platform:ep93xx-i2s"); 536MODULE_AUTHOR("Ryan Mallon"); 537MODULE_DESCRIPTION("EP93XX I2S driver"); 538MODULE_LICENSE("GPL"); 539