Searched refs:reg_val (Results 76 - 100 of 394) sorted by relevance

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/linux-master/drivers/infiniband/hw/irdma/
H A Di40iw_hw.c109 u32 reg_val; local
111 reg_val = FIELD_PREP(I40E_PFINT_LNKLSTN_FIRSTQ_INDX, ceq_id) |
113 wr32(dev->hw, I40E_PFINT_LNKLSTN(idx - 1), reg_val);
115 reg_val = FIELD_PREP(I40E_PFINT_DYN_CTLN_ITR_INDX, 0x3) |
117 wr32(dev->hw, I40E_PFINT_DYN_CTLN(idx - 1), reg_val);
119 reg_val = FIELD_PREP(IRDMA_GLINT_CEQCTL_CAUSE_ENA, enable) |
124 wr32(dev->hw, i40iw_regs[IRDMA_GLINT_CEQCTL] + 4 * ceq_id, reg_val);
/linux-master/drivers/gpu/drm/imagination/
H A Dpvr_fw_startstop.c23 u64 reg_val = local
33 pvr_cr_write64(pvr_dev, ROGUE_CR_AXI_ACE_LITE_CONFIGURATION, reg_val);
58 u32 reg_val; local
68 reg_val = (pvr_cr_read32(pvr_dev, ROGUE_CR_SLC_CTRL_MISC) &
78 reg_val |= ROGUE_CR_SLC_CTRL_MISC_BYPASS_BURST_COMBINER_EN;
81 reg_val |= ROGUE_CR_SLC_CTRL_MISC_LAZYWB_OVERRIDE_EN;
83 pvr_cr_write32(pvr_dev, ROGUE_CR_SLC_CTRL_MISC, reg_val);
/linux-master/drivers/hwmon/
H A Dltc2991.c82 int reg_val, ret, offset = 0; local
84 ret = ltc2991_read_reg(st, reg, 2, &reg_val);
93 *val = DIV_ROUND_CLOSEST(sign_extend32(reg_val, 14) * 30518,
120 int reg_val, ret; local
122 ret = ltc2991_read_reg(st, reg, 2, &reg_val);
127 *val = DIV_ROUND_CLOSEST(sign_extend32(reg_val, 14) * 19075,
151 int reg_val, ret; local
153 ret = ltc2991_read_reg(st, reg, 2, &reg_val);
158 *val = DIV_ROUND_CLOSEST(sign_extend32(reg_val, 12) * 1000, 16);
/linux-master/drivers/input/mouse/
H A Dsentelic.c37 static unsigned char fsp_test_swap_cmd(unsigned char reg_val) argument
39 switch (reg_val) {
46 return (reg_val >> 4) | (reg_val << 4);
48 return reg_val; /* swap isn't necessary */
56 static unsigned char fsp_test_invert_cmd(unsigned char reg_val) argument
58 switch (reg_val) {
65 return ~reg_val;
67 return reg_val; /* inversion isn't necessary */
71 static int fsp_reg_read(struct psmouse *psmouse, int reg_addr, int *reg_val) argument
128 fsp_reg_write(struct psmouse *psmouse, int reg_addr, int reg_val) argument
201 fsp_page_reg_read(struct psmouse *psmouse, int *reg_val) argument
239 fsp_page_reg_write(struct psmouse *psmouse, int reg_val) argument
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/linux-master/drivers/gpu/drm/sprd/
H A Dmegacores_pll.c83 u8 reg_val[9] = {0}; local
91 reg_val[0] = 1 | (1 << 1) | (pll->lpf_sel << 2);
92 reg_val[1] = pll->div | (1 << 3) | (pll->cp_s << 5) | (pll->fdk_s << 7);
93 reg_val[2] = pll->nint;
94 reg_val[3] = pll->vco_band | (pll->sdm_en << 1) | (pll->refin << 2);
95 reg_val[4] = pll->kint >> 12;
96 reg_val[5] = pll->kint >> 4;
97 reg_val[6] = pll->out_sel | ((pll->kint << 4) & 0xf);
98 reg_val[7] = 1 << 4;
99 reg_val[
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/linux-master/drivers/net/ethernet/intel/i40e/
H A Di40e_diag.c121 u16 reg_val; local
124 ret_code = i40e_read_nvm_word(hw, I40E_SR_NVM_CONTROL_WORD, &reg_val);
126 ((reg_val & I40E_SR_CONTROL_WORD_1_MASK) ==
/linux-master/drivers/gpio/
H A Dgpio-madera.c76 unsigned int reg_val = value ? MADERA_GP1_LVL : 0; local
87 MADERA_GP1_LVL_MASK, reg_val);
96 unsigned int reg_val = value ? MADERA_GP1_LVL : 0; local
101 MADERA_GP1_LVL_MASK, reg_val);
H A Dgpio-adp5520.c26 uint8_t reg_val; local
36 adp5520_read(dev->master, ADP5520_GPIO_OUT, &reg_val);
38 adp5520_read(dev->master, ADP5520_GPIO_IN, &reg_val);
40 return !!(reg_val & dev->lut[off]);
/linux-master/arch/mips/include/asm/
H A Dmips-cps.h75 uint##sz##_t reg_val = read_##unit##_##name(); \
76 reg_val &= ~mask; \
77 reg_val |= val; \
78 write_##unit##_##name(reg_val); \
/linux-master/drivers/media/platform/rockchip/rkisp1/
H A Drkisp1-stats.c182 u32 reg_val; local
185 reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_WHITE_CNT_V10);
187 RKISP1_CIF_ISP_AWB_GET_PIXEL_CNT(reg_val);
188 reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_MEAN_V10);
191 RKISP1_CIF_ISP_AWB_GET_MEAN_CR_R(reg_val);
193 RKISP1_CIF_ISP_AWB_GET_MEAN_CB_B(reg_val);
195 RKISP1_CIF_ISP_AWB_GET_MEAN_Y_G(reg_val);
203 u32 reg_val; local
206 reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_AWB_WHITE_CNT_V12);
208 RKISP1_CIF_ISP_AWB_GET_PIXEL_CNT(reg_val);
281 u32 reg_val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_HIST_BIN_0_V10 + i * 4); local
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/linux-master/drivers/power/supply/
H A Daxp288_charger.c155 u8 reg_val; local
163 reg_val = (cc - CHRG_CCCV_CC_OFFSET) / CHRG_CCCV_CC_LSB_RES;
164 cc = (reg_val * CHRG_CCCV_CC_LSB_RES) + CHRG_CCCV_CC_OFFSET;
165 reg_val = reg_val << CHRG_CCCV_CC_BIT_POS;
169 CHRG_CCCV_CC_MASK, reg_val);
178 u8 reg_val; local
182 reg_val = CHRG_CCCV_CV_4100MV;
185 reg_val = CHRG_CCCV_CV_4150MV;
188 reg_val
241 u8 reg_val; local
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/linux-master/drivers/mfd/
H A Dda903x.c173 uint8_t reg_val; local
178 ret = __da903x_read(chip->client, reg, &reg_val);
182 if ((reg_val & bit_mask) != bit_mask) {
183 reg_val |= bit_mask;
184 ret = __da903x_write(chip->client, reg, reg_val);
195 uint8_t reg_val; local
200 ret = __da903x_read(chip->client, reg, &reg_val);
204 if (reg_val & bit_mask) {
205 reg_val &= ~bit_mask;
206 ret = __da903x_write(chip->client, reg, reg_val);
217 uint8_t reg_val; local
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H A Dtwl6030-irq.c262 u8 reg_val = 0; local
273 ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &reg_val, TWL6030_MMCCTRL);
278 reg_val &= ~VMMC_AUTO_OFF;
279 reg_val |= SW_FC;
280 ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, TWL6030_MMCCTRL);
287 ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &reg_val,
294 reg_val &= ~(MMC_PU | MMC_PD);
295 ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val,
/linux-master/drivers/leds/
H A Dleds-lm355x.c161 unsigned int reg_val; local
167 reg_val = (u32)pdata->pin_tx2 | (u32)pdata->ntc_pin;
168 ret = regmap_update_bits(chip->regmap, 0xE0, 0x28, reg_val);
171 reg_val = (u32)pdata->pass_mode;
172 ret = regmap_update_bits(chip->regmap, 0xA0, 0x04, reg_val);
178 reg_val = (u32)pdata->pin_tx2 | (u32)pdata->ntc_pin |
180 ret = regmap_update_bits(chip->regmap, 0x0A, 0xC4, reg_val);
199 unsigned int reg_val; local
251 reg_val = 0x00;
253 reg_val
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/linux-master/drivers/net/phy/mscc/
H A Dmscc_main.c180 u16 reg_val; local
183 reg_val = phy_read(phydev, MSCC_PHY_LED_MODE_SEL);
184 reg_val &= ~LED_MODE_SEL_MASK(led_num);
185 reg_val |= LED_MODE_SEL(led_num, (u16)mode);
186 rc = phy_write(phydev, MSCC_PHY_LED_MODE_SEL, reg_val);
194 u16 reg_val; local
196 reg_val = phy_read(phydev, MSCC_PHY_DEV_AUX_CNTL);
197 if (reg_val & HP_AUTO_MDIX_X_OVER_IND_MASK)
208 u16 reg_val; local
210 reg_val
242 int reg_val; local
281 u16 reg_val; local
353 u16 reg_val; local
483 u16 reg_val; local
533 u16 reg_val = 0; local
847 u16 reg_val; local
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/linux-master/drivers/gpu/drm/kmb/
H A Dkmb_dsi.h353 u32 reg_val = kmb_read_mipi(kmb_dsi, reg); local
358 reg_val &= (~mask);
359 reg_val |= (value << offset);
360 kmb_write_mipi(kmb_dsi, reg, reg_val);
366 u32 reg_val = kmb_read_mipi(kmb_dsi, reg); local
368 kmb_write_mipi(kmb_dsi, reg, reg_val | (1 << offset));
374 u32 reg_val = kmb_read_mipi(kmb_dsi, reg); local
376 kmb_write_mipi(kmb_dsi, reg, reg_val & (~(1 << offset)));
/linux-master/drivers/input/touchscreen/
H A Dsun4i-ts.c117 static void sun4i_ts_irq_handle_input(struct sun4i_ts_data *ts, u32 reg_val) argument
121 if (reg_val & FIFO_DATA_PENDING) {
140 if (reg_val & TP_UP_PENDING) {
150 u32 reg_val; local
152 reg_val = readl(ts->base + TP_INT_FIFOS);
154 if (reg_val & TEMP_DATA_PENDING)
158 sun4i_ts_irq_handle_input(ts, reg_val);
160 writel(reg_val, ts->base + TP_INT_FIFOS);
/linux-master/drivers/thermal/intel/int340x_thermal/
H A Dprocessor_thermal_rfim.c100 u32 reg_val;\
117 reg_val = readl((void __iomem *) (proc_priv->mmio_base + mmio_regs[ret].offset));\
118 ret = (reg_val >> mmio_regs[ret].shift) & mmio_regs[ret].mask;\
133 u32 reg_val;\
157 reg_val = readl((void __iomem *) (proc_priv->mmio_base + mmio_regs[ret].offset));\
158 reg_val &= ~mask;\
159 reg_val |= (input << mmio_regs[ret].shift);\
160 writel(reg_val, (void __iomem *) (proc_priv->mmio_base + mmio_regs[ret].offset));\
/linux-master/drivers/net/ethernet/qlogic/qed/
H A Dqed_init_fw_funcs.c894 u32 reg_val, i; local
896 for (i = 0, reg_val = 0; i < QM_STOP_CMD_MAX_POLL_COUNT && !reg_val;
899 reg_val = qed_rd(p_hwfn, p_ptt, QM_REG_SDMCMDREADY);
1263 u32 reg_val; local
1267 reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
1268 SET_FIELD(reg_val,
1270 qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
1271 if (reg_val) {
1272 reg_val
1296 u32 reg_val; local
1351 u32 reg_val; local
1398 u32 reg_val, cfg_mask; local
1459 u32 reg_val, cam_line; local
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/linux-master/drivers/thermal/
H A Drzg2l_thermal.c123 u32 reg_val; local
135 reg_val = rzg2l_thermal_read(priv, TSU_ST);
136 reg_val |= TSU_ST_START;
137 rzg2l_thermal_write(priv, TSU_ST, reg_val);
139 return readl_poll_timeout(priv->base + TSU_SS, reg_val,
140 reg_val == TSU_SS_CONV_RUNNING, 50,
/linux-master/drivers/nvmem/
H A Dsunxi_sid.c66 u32 reg_val; local
70 reg_val = (offset & SUN8I_SID_OFFSET_MASK)
72 reg_val |= SUN8I_SID_OP_LOCK | SUN8I_SID_READ;
73 writel(reg_val, sid->base + SUN8I_SID_PRCTL);
75 ret = readl_poll_timeout(sid->base + SUN8I_SID_PRCTL, reg_val,
76 !(reg_val & SUN8I_SID_READ), 100, 250000);
/linux-master/drivers/input/keyboard/
H A Dtca6416-keypad.c91 u16 reg_val, val; local
94 error = tca6416_read_reg(chip, TCA6416_INPUT, &reg_val);
98 reg_val &= chip->pinmask;
101 val = reg_val ^ chip->reg_input;
102 chip->reg_input = reg_val;
108 int state = ((reg_val & (1 << i)) ? 1 : 0)
/linux-master/drivers/gpu/drm/xe/
H A Dxe_gt_topology.c37 u32 reg_val = xe_mmio_read32(gt, XELP_EU_ENABLE); local
48 reg_val = ~reg_val & XELP_EU_MASK;
52 val = reg_val;
55 for (i = 0; i < fls(reg_val); i++)
56 if (reg_val & BIT(i))
/linux-master/sound/soc/amd/raven/
H A Dacp3x-pcm-dma.c433 u32 val, reg_val, frmt_val; local
435 reg_val = 0;
445 reg_val = mmACP_BTTDM_ITER;
450 reg_val = mmACP_I2STDM_ITER;
454 rtd->acp3x_base + reg_val);
462 reg_val = mmACP_BTTDM_IRER;
467 reg_val = mmACP_I2STDM_IRER;
471 rtd->acp3x_base + reg_val);
475 val = rv_readl(adata->acp3x_base + reg_val);
476 rv_writel(val | 0x2, adata->acp3x_base + reg_val);
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/linux-master/sound/soc/amd/acp/
H A Dacp-legacy-common.c198 u32 tdm_fmt, reg_val, fmt_reg, val; local
206 reg_val = ACP_BTTDM_ITER;
210 reg_val = ACP_I2STDM_ITER;
214 reg_val = ACP_HSTDM_ITER;
226 reg_val = ACP_BTTDM_IRER;
230 reg_val = ACP_I2STDM_IRER;
234 reg_val = ACP_HSTDM_IRER;
243 writel(val, adata->acp_base + reg_val);
246 val = readl(adata->acp_base + reg_val);
247 writel(val | 0x2, adata->acp_base + reg_val);
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Completed in 305 milliseconds

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