qlogic/qed/qed_init_fw_funcs.c

894 	u32 reg_val, i;
896 	for (i = 0, reg_val = 0; i < QM_STOP_CMD_MAX_POLL_COUNT && !reg_val;
899 		reg_val = qed_rd(p_hwfn, p_ptt, QM_REG_SDMCMDREADY);
1263 	u32 reg_val;
1267 	reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
1268 	SET_FIELD(reg_val,
1270 	qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
1271 	if (reg_val) {
1272 		reg_val =
1276 		if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT)
1282 	reg_val = qed_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);
1284 	SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, vxlan_enable);
1285 	qed_wr(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE, reg_val);
1296 	u32 reg_val;
1300 	reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
1301 	SET_FIELD(reg_val,
1304 	SET_FIELD(reg_val,
1307 	qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
1308 	if (reg_val) {
1309 		reg_val =
1313 		if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT)
1319 	reg_val = qed_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);
1321 	SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, eth_gre_enable);
1323 	SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, ip_gre_enable);
1324 	qed_wr(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE, reg_val);
1351 	u32 reg_val;
1354 	reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
1355 	SET_FIELD(reg_val,
1358 	SET_FIELD(reg_val,
1361 	qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
1362 	if (reg_val) {
1363 		reg_val =
1367 		if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT)
1398 	u32 reg_val, cfg_mask;
1401 	reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_MSG_INFO);
1408 		reg_val |= cfg_mask;
1417 		reg_val &= ~cfg_mask;
1421 	qed_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, reg_val);
1459 	u32 reg_val, cam_line;
1472 	reg_val = T_ETH_PACKET_MATCH_RFS_EVENTID <<
1474 	reg_val |= PARSER_ETH_CONN_CM_HDR << PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT;
1475 	qed_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, reg_val);