Searched refs:pll (Results 51 - 75 of 339) sorted by relevance

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/linux-master/drivers/clk/baikal-t1/
H A D	ccu-pll.h	63 static inline struct clk_hw *ccu_pll_get_clk_hw(struct ccu_pll *pll) argument 65 return pll ? &pll->hw : NULL; 70 void ccu_pll_hw_unregister(struct ccu_pll *pll);
/linux-master/drivers/video/fbdev/matrox/
H A D	matroxfb_misc.h	8 int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int fmax, 15 return matroxfb_PLL_calcclock(&minfo->features.pll, freq, fmax, in, feed, post);
H A D	g450_pll.c	35 return (minfo->features.pll.ref_freq * n + (m >> 1)) / m; 99 n = ((tvco * (m+1) + minfo->features.pll.ref_freq) / (minfo->features.pll.ref_freq * 2)) - 2; 137 unsigned int mnp, unsigned int pll) 139 switch (pll) { 174 unsigned int mnp, unsigned int pll) 180 switch (pll) { 230 unsigned int pll) 232 return g450_isplllocked(minfo, g450_setpll(minfo, mnp, pll)); 235 static void updatehwstate_clk(struct matrox_hw_state* hw, unsigned int mnp, unsigned int pll) { argument 136 g450_setpll(const struct matrox_fb_info *minfo, unsigned int mnp, unsigned int pll) argument 173 g450_cmppll(const struct matrox_fb_info *minfo, unsigned int mnp, unsigned int pll) argument 229 g450_testpll(const struct matrox_fb_info *minfo, unsigned int mnp, unsigned int pll) argument 245 matroxfb_g450_setpll_cond(struct matrox_fb_info *minfo, unsigned int mnp, unsigned int pll) argument 253 g450_findworkingpll(struct matrox_fb_info *minfo, unsigned int pll, unsigned int *mnparray, unsigned int mnpcount) argument 331 __g450_setclk(struct matrox_fb_info *minfo, unsigned int fout, unsigned int pll, unsigned int *mnparray, unsigned int *deltaarray) argument 494 matroxfb_g450_setclk(struct matrox_fb_info *minfo, unsigned int fout, unsigned int pll) argument [all...]
/linux-master/drivers/clk/nuvoton/
H A D	Makefile	4 obj-$(CONFIG_CLK_MA35D1) += clk-ma35d1-pll.o
/linux-master/drivers/clk/socfpga/
H A D	Makefile	2 obj-$(CONFIG_CLK_INTEL_SOCFPGA32) += clk.o clk-gate.o clk-pll.o clk-periph.o \ 3 clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o 5 clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o \
/linux-master/drivers/clk/zynq/
H A D	pll.c	15 * struct zynq_pll - pll clock 188 struct zynq_pll *pll; local 201 pll = kmalloc(sizeof(*pll), GFP_KERNEL); 202 if (!pll) 206 pll->hw.init = &initd; 207 pll->pll_ctrl = pll_ctrl; 208 pll->pll_status = pll_status; 209 pll->lockbit = lock_index; 210 pll [all...]
/linux-master/drivers/video/fbdev/omap2/omapfb/dss/
H A D	pll.c	30 int dss_pll_register(struct dss_pll *pll) argument 36 dss_plls[i] = pll; 44 void dss_pll_unregister(struct dss_pll *pll) argument 49 if (dss_plls[i] == pll) { 68 int dss_pll_enable(struct dss_pll *pll) argument 72 r = clk_prepare_enable(pll->clkin); 76 if (pll->regulator) { 77 r = regulator_enable(pll->regulator); 82 r = pll->ops->enable(pll); 96 dss_pll_disable(struct dss_pll *pll) argument 108 dss_pll_set_config(struct dss_pll *pll, const struct dss_pll_clock_info *cinfo) argument 121 dss_pll_hsdiv_calc(const struct dss_pll *pll, unsigned long clkdco, unsigned long out_min, unsigned long out_max, dss_hsdiv_calc_func func, void *data) argument 146 dss_pll_calc(const struct dss_pll *pll, unsigned long clkin, unsigned long pll_min, unsigned long pll_max, dss_pll_calc_func func, void *data) argument 214 dss_pll_wait_reset_done(struct dss_pll *pll) argument 224 dss_wait_hsdiv_ack(struct dss_pll *pll, u32 hsdiv_ack_mask) argument 238 dss_pll_write_config_type_a(struct dss_pll *pll, const struct dss_pll_clock_info *cinfo) argument 330 dss_pll_write_config_type_b(struct dss_pll *pll, const struct dss_pll_clock_info *cinfo) argument [all...]
/linux-master/drivers/gpu/drm/msm/hdmi/
H A D	hdmi_phy_8996.c	33 /* pll mmio base */ 81 static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8996 *pll) argument 83 return platform_get_drvdata(pll->pdev); 86 static inline void hdmi_pll_write(struct hdmi_pll_8996 *pll, int offset, argument 89 writel(data, pll->mmio_qserdes_com + offset); 92 static inline u32 hdmi_pll_read(struct hdmi_pll_8996 *pll, int offset) argument 94 return readl(pll->mmio_qserdes_com + offset); 97 static inline void hdmi_tx_chan_write(struct hdmi_pll_8996 *pll, int channel, argument 100 writel(data, pll->mmio_qserdes_tx[channel] + offset); 398 struct hdmi_pll_8996 *pll local 567 hdmi_8996_pll_lock_status(struct hdmi_pll_8996 *pll) argument 594 struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw); local 647 struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw); local 666 struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw); local 675 struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw); local 707 struct hdmi_pll_8996 *pll; local [all...]
H A D	hdmi_pll_8960.c	26 * To get the parent clock setup properly, we need to plug in hdmi pll 237 static inline void pll_write(struct hdmi_pll_8960 *pll, u32 reg, u32 data) argument 239 writel(data, pll->mmio + reg); 242 static inline u32 pll_read(struct hdmi_pll_8960 *pll, u32 reg) argument 244 return readl(pll->mmio + reg); 247 static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8960 *pll) argument 249 return platform_get_drvdata(pll->pdev); 254 struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw); local 255 struct hdmi_phy *phy = pll_get_phy(pll); 262 pll_write(pll, REG_HDMI_8960_PHY_PLL_LOCKDET_CFG 339 struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw); local 371 struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw); local 387 struct hdmi_pll_8960 *pll = hw_clk_to_pll(hw); local 424 struct hdmi_pll_8960 *pll; local [all...]
/linux-master/drivers/clk/st/
H A D	clkgen-pll.c	93 { .name = "clk-s-a0-pll-odf-0", }, 154 { .name = "clockgen-a9-pll-odf", }, 179 { .name = "clockgen-a9-pll-odf", }, 230 struct clkgen_pll *pll = to_clkgen_pll(hw); local 231 u32 locked = CLKGEN_READ(pll, locked_status); 238 struct clkgen_pll *pll = to_clkgen_pll(hw); local 239 u32 poweroff = CLKGEN_READ(pll, pdn_status); 245 struct clkgen_pll *pll = to_clkgen_pll(hw); local 246 void __iomem *base = pll->regs_base; 247 struct clkgen_field *field = &pll 271 struct clkgen_pll *pll = to_clkgen_pll(hw); local 288 struct clkgen_pll *pll = to_clkgen_pll(hw); local 303 struct clkgen_pll *pll = to_clkgen_pll(hw); local 315 clk_pll3200c32_get_params(unsigned long input, unsigned long output, struct stm_pll *pll) argument 365 clk_pll3200c32_get_rate(unsigned long input, struct stm_pll *pll, unsigned long *rate) argument 379 struct clkgen_pll *pll = to_clkgen_pll(hw); local 422 struct clkgen_pll *pll = to_clkgen_pll(hw); local 476 clk_pll4600c28_get_params(unsigned long input, unsigned long output, struct stm_pll *pll) argument 521 clk_pll4600c28_get_rate(unsigned long input, struct stm_pll *pll, unsigned long *rate) argument 535 struct clkgen_pll *pll = to_clkgen_pll(hw); local 576 struct clkgen_pll *pll = to_clkgen_pll(hw); local 649 struct clkgen_pll *pll; local [all...]
/linux-master/drivers/gpu/drm/omapdrm/dss/
H A D	pll.c	28 int dss_pll_register(struct dss_device *dss, struct dss_pll *pll) argument 34 dss->plls[i] = pll; 35 pll->dss = dss; 43 void dss_pll_unregister(struct dss_pll *pll) argument 45 struct dss_device *dss = pll->dss; 49 if (dss->plls[i] == pll) { 51 pll->dss = NULL; 72 struct dss_pll *pll; local 85 pll = dss_pll_find(dss, "dsi0"); 86 if (!pll) 123 dss_pll_enable(struct dss_pll *pll) argument 151 dss_pll_disable(struct dss_pll *pll) argument 163 dss_pll_set_config(struct dss_pll *pll, const struct dss_pll_clock_info *cinfo) argument 176 dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco, unsigned long out_min, unsigned long out_max, dss_hsdiv_calc_func func, void *data) argument 205 dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin, unsigned long pll_min, unsigned long pll_max, dss_pll_calc_func func, void *data) argument 272 dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin, unsigned long target_clkout, struct dss_pll_clock_info *cinfo) argument 356 dss_pll_wait_reset_done(struct dss_pll *pll) argument 366 dss_wait_hsdiv_ack(struct dss_pll *pll, u32 hsdiv_ack_mask) argument 396 dss_pll_write_config_type_a(struct dss_pll *pll, const struct dss_pll_clock_info *cinfo) argument 524 dss_pll_write_config_type_b(struct dss_pll *pll, const struct dss_pll_clock_info *cinfo) argument [all...]
/linux-master/drivers/clk/mediatek/
H A D	clk-fhctl.c	55 static void dump_hw(struct mtk_clk_pll *pll, struct fh_pll_regs *regs, argument 65 pr_info("pcw<%x>\n", readl(pll->pcw_addr)); 68 static int fhctl_set_ssc_regs(struct mtk_clk_pll *pll, struct fh_pll_regs *regs, argument 89 writel((readl(pll->pcw_addr) & data->dds_mask) | data->tgl_org, 116 static int hopping_hw_flow(struct mtk_clk_pll *pll, struct fh_pll_regs *regs, argument 126 fhctl_set_ssc_regs(pll, regs, data, 0); 128 writel((readl(pll->pcw_addr) & dds_mask) | data->tgl_org, 144 pr_warn("%s: FHCTL hopping timeout\n", pll->data->name); 145 dump_hw(pll, regs, data); 148 con_pcw_tmp = readl(pll 161 __get_postdiv(struct mtk_clk_pll *pll) argument 171 __set_postdiv(struct mtk_clk_pll *pll, unsigned int postdiv) argument 187 struct mtk_clk_pll *pll = &fh->clk_pll; local 217 struct mtk_clk_pll *pll = &fh->clk_pll; local [all...]
H A D	clk-pllfh.c	22 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); local 24 return container_of(pll, struct mtk_fh, clk_pll); 30 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); local 35 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); 213 const struct mtk_pll_data *pll = &plls[i]; local 217 pllfh = get_pllfh_by_id(pllfhs, num_fhs, pll->id); 221 hw = mtk_clk_register_pllfh(pll, pllfh, base); 223 hw = mtk_clk_register_pll(pll, base); 227 use_fhctl ? "fhpll" : "pll", pll 239 const struct mtk_pll_data *pll = &plls[i]; local 271 const struct mtk_pll_data *pll = &plls[i - 1]; local [all...]
/linux-master/drivers/gpu/drm/i915/display/
H A D	intel_dpll_mgr.c	64 * Hook for enabling the pll, called from intel_enable_shared_dpll() if 65 * the pll is not already enabled. 68 struct intel_shared_dpll *pll, 72 * Hook for disabling the pll, called from intel_disable_shared_dpll() 73 * only when it is safe to disable the pll, i.e., there are no more 77 struct intel_shared_dpll *pll); 85 struct intel_shared_dpll *pll, 89 * Hook for calculating the pll's output frequency based on its passed 93 const struct intel_shared_dpll *pll, 122 struct intel_shared_dpll *pll; local 159 struct intel_shared_dpll *pll; local 172 assert_shared_dpll(struct drm_i915_private *i915, struct intel_shared_dpll *pll, bool state) argument 201 intel_combo_pll_enable_reg(struct drm_i915_private *i915, struct intel_shared_dpll *pll) argument 214 intel_tc_pll_enable_reg(struct drm_i915_private *i915, struct intel_shared_dpll *pll) argument 226 _intel_enable_shared_dpll(struct drm_i915_private *i915, struct intel_shared_dpll *pll) argument 236 _intel_disable_shared_dpll(struct drm_i915_private *i915, struct intel_shared_dpll *pll) argument 256 struct intel_shared_dpll *pll = crtc_state->shared_dpll; local 302 struct intel_shared_dpll *pll = crtc_state->shared_dpll; local 341 struct intel_shared_dpll *pll; local 371 struct intel_shared_dpll *pll; local 417 intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc, const struct intel_shared_dpll *pll, struct intel_shared_dpll_state *shared_dpll_state) argument 432 intel_reference_shared_dpll(struct intel_atomic_state *state, const struct intel_crtc *crtc, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) argument 456 intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc, const struct intel_shared_dpll *pll, struct intel_shared_dpll_state *shared_dpll_state) argument 470 intel_unreference_shared_dpll(struct intel_atomic_state *state, const struct intel_crtc *crtc, const struct intel_shared_dpll *pll) argument 512 struct intel_shared_dpll *pll; local 522 ibx_pch_dpll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) argument 558 ibx_pch_dpll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) argument 587 ibx_pch_dpll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) argument 611 struct intel_shared_dpll *pll; local 688 hsw_ddi_wrpll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) argument 700 hsw_ddi_spll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) argument 711 hsw_ddi_wrpll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) argument 727 hsw_ddi_spll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) argument 743 hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) argument 765 hsw_ddi_spll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) argument 992 hsw_ddi_wrpll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) argument 1091 struct intel_shared_dpll *pll; local 1118 hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) argument 1170 hsw_ddi_spll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) argument 1218 struct intel_shared_dpll *pll = NULL; local 1281 hsw_ddi_lcpll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *hw_state) argument 1287 hsw_ddi_lcpll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) argument 1292 hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) argument 1360 skl_ddi_pll_write_ctrl1(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct skl_dpll_hw_state *hw_state) argument 1374 skl_ddi_pll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) argument 1396 skl_ddi_dpll0_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) argument 1405 skl_ddi_pll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) argument 1416 skl_ddi_dpll0_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) argument 1421 skl_ddi_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) argument 1459 skl_ddi_dpll0_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) argument 1732 skl_ddi_wrpll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) argument 1880 skl_ddi_lcpll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) argument 1936 struct intel_shared_dpll *pll; local 1959 skl_ddi_pll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) argument 2034 bxt_ddi_pll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) argument 2137 bxt_ddi_pll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) argument 2156 bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) argument 2356 bxt_ddi_pll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) argument 2426 struct intel_shared_dpll *pll; local 2751 icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) argument 2822 icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) argument 3195 icl_ddi_mg_pll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) argument 3534 mg_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) argument 3601 dkl_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) argument 3673 icl_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state, i915_reg_t enable_reg) argument 3734 combo_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) argument 3743 tbt_pll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) argument 3750 icl_dpll_write(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct icl_dpll_hw_state *hw_state) argument 3792 icl_mg_pll_write(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct icl_dpll_hw_state *hw_state) argument 3835 dkl_pll_write(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct icl_dpll_hw_state *hw_state) argument 3900 icl_pll_power_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, i915_reg_t enable_reg) argument 3915 icl_pll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, i915_reg_t enable_reg) argument 3926 adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct intel_shared_dpll *pll) argument 3950 combo_pll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) argument 3974 tbt_pll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) argument 3995 mg_pll_enable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) argument 4020 icl_pll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll, i915_reg_t enable_reg) argument 4051 combo_pll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) argument 4059 tbt_pll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) argument 4065 mg_pll_disable(struct drm_i915_private *i915, struct intel_shared_dpll *pll) argument 4477 intel_dpll_get_freq(struct drm_i915_private *i915, const struct intel_shared_dpll *pll, const struct intel_dpll_hw_state *dpll_hw_state) argument 4495 intel_dpll_get_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_dpll_hw_state *dpll_hw_state) argument 4502 readout_dpll_hw_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll) argument 4535 struct intel_shared_dpll *pll; local 4542 sanitize_dpll_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll) argument 4562 struct intel_shared_dpll *pll; local 4616 verify_single_dpll_state(struct drm_i915_private *i915, struct intel_shared_dpll *pll, struct intel_crtc *crtc, const struct intel_crtc_state *new_crtc_state) argument 4693 struct intel_shared_dpll *pll = old_crtc_state->shared_dpll; local 4711 struct intel_shared_dpll *pll; local [all...]
/linux-master/drivers/clk/imx/
H A D	clk-sscg-pll.c	7 * Documentation for this SCCG pll can be found at: 98 static int clk_sscg_pll_wait_lock(struct clk_sscg_pll *pll) argument 102 val = readl_relaxed(pll->base + PLL_CFG0); 106 return readl_poll_timeout(pll->base, val, val & PLL_LOCK_MASK, 298 struct clk_sscg_pll *pll = to_clk_sscg_pll(hw); local 300 u32 val = readl_relaxed(pll->base + PLL_CFG0); 307 struct clk_sscg_pll *pll = to_clk_sscg_pll(hw); local 310 val = readl_relaxed(pll->base + PLL_CFG0); 312 writel_relaxed(val, pll->base + PLL_CFG0); 314 return clk_sscg_pll_wait_lock(pll); 319 struct clk_sscg_pll *pll = to_clk_sscg_pll(hw); local 330 struct clk_sscg_pll *pll = to_clk_sscg_pll(hw); local 361 struct clk_sscg_pll *pll = to_clk_sscg_pll(hw); local 386 struct clk_sscg_pll *pll = to_clk_sscg_pll(hw); local 400 struct clk_sscg_pll *pll = to_clk_sscg_pll(hw); local 418 struct clk_sscg_pll *pll = to_clk_sscg_pll(hw); local 456 struct clk_sscg_pll *pll = to_clk_sscg_pll(hw); local 507 struct clk_sscg_pll *pll; local [all...]
H A D	clk-cpu.c	16 struct clk *pll; member in struct:clk_cpu 38 return clk_round_rate(cpu->pll, rate); 53 ret = clk_set_rate(cpu->pll, rate); 55 clk_set_parent(cpu->mux, cpu->pll); 59 clk_set_parent(cpu->mux, cpu->pll); 74 struct clk *div, struct clk *mux, struct clk *pll, 88 cpu->pll = pll; 73 imx_clk_hw_cpu(const char *name, const char *parent_name, struct clk *div, struct clk *mux, struct clk *pll, struct clk *step) argument
/linux-master/drivers/clk/spear/
H A D	clk-vco-pll.c	9 #define pr_fmt(fmt) "clk-vco-pll: " fmt 28 * pll_rate = pll/2^p 30 * vco and pll are very closely bound to each other, "vco needs to program: 31 * mode, m & n" and "pll needs to program p", both share common enable/disable 34 * clk_register_vco_pll() registers instances of both vco & pll. 35 * CLK_SET_RATE_PARENT flag is forced for pll, as it will always pass its 65 /* Calculates pll clk rate for specific value of mode, m, n and p */ 84 struct clk_pll *pll = to_clk_pll(hw); local 90 pr_err("%s: prate is must for pll clk\n", __func__); 94 for (*index = 0; *index < pll 124 struct clk_pll *pll = to_clk_pll(hw); local 144 struct clk_pll *pll = to_clk_pll(hw); local 280 struct clk_pll *pll; local [all...]
/linux-master/drivers/clk/berlin/
H A D	Makefile	2 obj-y += berlin2-avpll.o berlin2-pll.o berlin2-div.o
/linux-master/drivers/clk/x86/
H A D	Makefile	4 obj-$(CONFIG_CLK_LGM_CGU) += clk-cgu.o clk-cgu-pll.o clk-lgm.o
/linux-master/drivers/phy/freescale/
H A D	phy-fsl-lynx-28g.c	27 #define LYNX_28G_PLLnRSTCTL(pll) (0x400 + (pll) * 0x100 + 0x0) 31 #define LYNX_28G_PLLnCR0(pll) (0x400 + (pll) * 0x100 + 0x4) 39 #define LYNX_28G_PLLnCR1(pll) (0x400 + (pll) * 0x100 + 0x8) 134 struct lynx_28g_pll pll[LYNX_28G_NUM_PLL]; member in struct:lynx_28g_priv 157 #define lynx_28g_pll_read(pll, reg) \ 158 ioread32((pll)->priv->base + LYNX_28G_##reg((pll) 178 struct lynx_28g_pll *pll; local 194 lynx_28g_lane_set_nrate(struct lynx_28g_lane *lane, struct lynx_28g_pll *pll, phy_interface_t intf) argument 227 lynx_28g_lane_set_pll(struct lynx_28g_lane *lane, struct lynx_28g_pll *pll) argument 266 struct lynx_28g_pll *pll; local 302 struct lynx_28g_pll *pll; local 474 struct lynx_28g_pll *pll; local [all...]
/linux-master/drivers/clk/qcom/
H A D	clk-alpha-pll.h	77 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 101 * @regs: alpha pll register map (see @clk_alpha_pll_regs) 195 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 197 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 199 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 201 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 203 #define clk_lucid_pll_configure(pll, regmap, config) \ 204 clk_trion_pll_configure(pll, regmap, config) 206 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 208 void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struc [all...]
/linux-master/drivers/clk/actions/
H A D	owl-pll.c	3 // OWL pll clock driver 16 #include "owl-pll.h" 62 struct owl_pll *pll = hw_to_owl_pll(hw); local 63 struct owl_pll_hw *pll_hw = &pll->pll_hw; 84 struct owl_pll *pll = hw_to_owl_pll(hw); local 85 struct owl_pll_hw *pll_hw = &pll->pll_hw; 86 const struct owl_clk_common *common = &pll->common; 112 struct owl_pll *pll = hw_to_owl_pll(hw); local 113 struct owl_pll_hw *pll_hw = &pll->pll_hw; 114 const struct owl_clk_common *common = &pll 139 struct owl_pll *pll = hw_to_owl_pll(hw); local 149 struct owl_pll *pll = hw_to_owl_pll(hw); local 158 struct owl_pll *pll = hw_to_owl_pll(hw); local [all...]
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A D	gk20a.c	65 gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll) argument 71 pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); 72 pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); 73 pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); 77 gk20a_pllg_write_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll) argument 82 val = (pll->m & MASK(GPCPLL_COEFF_M_WIDTH)) << GPCPLL_COEFF_M_SHIFT; 83 val |= (pll->n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT; 84 val |= (pll->pl & MASK(GPCPLL_COEFF_P_WIDTH)) << GPCPLL_COEFF_P_SHIFT; 89 gk20a_pllg_calc_rate(struct gk20a_clk *clk, struct gk20a_pll *pll) argument 94 rate = clk->parent_rate * pll 101 gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate, struct gk20a_pll *pll) argument 215 struct gk20a_pll pll; local 296 gk20a_pllg_program_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll) argument 335 gk20a_pllg_program_mnp_slide(struct gk20a_clk *clk, const struct gk20a_pll *pll) argument 465 struct gk20a_pll pll; local 550 struct gk20a_pll pll; local [all...]
/linux-master/drivers/phy/qualcomm/
H A D	phy-qcom-edp.c	106 void __iomem *pll; member in struct:qcom_edp 371 return readl_poll_timeout(edp->pll + QSERDES_V4_COM_CMN_STATUS, 379 writel(0x20, edp->pll + QSERDES_V4_COM_RESETSM_CNTRL); 381 return readl_poll_timeout(edp->pll + QSERDES_V4_COM_C_READY_STATUS, 388 writel(0x17, edp->pll + QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN); 417 writel(0x01, edp->pll + QSERDES_V4_COM_SSC_EN_CENTER); 418 writel(0x00, edp->pll + QSERDES_V4_COM_SSC_ADJ_PER1); 419 writel(0x36, edp->pll + QSERDES_V4_COM_SSC_PER1); 420 writel(0x01, edp->pll + QSERDES_V4_COM_SSC_PER2); 421 writel(step1, edp->pll [all...]
/linux-master/drivers/media/i2c/
H A D	aptina-pll.h	41 struct aptina_pll *pll);

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Indexes created Sun Jun 23 19:15:37 MDT 2024