1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2015, 2018, 2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7
8#ifndef __QCOM_CLK_ALPHA_PLL_H__
9#define __QCOM_CLK_ALPHA_PLL_H__
10
11#include <linux/clk-provider.h>
12#include "clk-regmap.h"
13
14/* Alpha PLL types */
15enum {
16	CLK_ALPHA_PLL_TYPE_DEFAULT,
17	CLK_ALPHA_PLL_TYPE_HUAYRA,
18	CLK_ALPHA_PLL_TYPE_HUAYRA_APSS,
19	CLK_ALPHA_PLL_TYPE_BRAMMO,
20	CLK_ALPHA_PLL_TYPE_FABIA,
21	CLK_ALPHA_PLL_TYPE_TRION,
22	CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
23	CLK_ALPHA_PLL_TYPE_AGERA,
24	CLK_ALPHA_PLL_TYPE_ZONDA,
25	CLK_ALPHA_PLL_TYPE_ZONDA_OLE,
26	CLK_ALPHA_PLL_TYPE_LUCID_EVO,
27	CLK_ALPHA_PLL_TYPE_LUCID_OLE,
28	CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
29	CLK_ALPHA_PLL_TYPE_DEFAULT_EVO,
30	CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
31	CLK_ALPHA_PLL_TYPE_STROMER,
32	CLK_ALPHA_PLL_TYPE_STROMER_PLUS,
33	CLK_ALPHA_PLL_TYPE_MAX,
34};
35
36enum {
37	PLL_OFF_L_VAL,
38	PLL_OFF_CAL_L_VAL,
39	PLL_OFF_ALPHA_VAL,
40	PLL_OFF_ALPHA_VAL_U,
41	PLL_OFF_USER_CTL,
42	PLL_OFF_USER_CTL_U,
43	PLL_OFF_USER_CTL_U1,
44	PLL_OFF_CONFIG_CTL,
45	PLL_OFF_CONFIG_CTL_U,
46	PLL_OFF_CONFIG_CTL_U1,
47	PLL_OFF_CONFIG_CTL_U2,
48	PLL_OFF_TEST_CTL,
49	PLL_OFF_TEST_CTL_U,
50	PLL_OFF_TEST_CTL_U1,
51	PLL_OFF_TEST_CTL_U2,
52	PLL_OFF_STATE,
53	PLL_OFF_STATUS,
54	PLL_OFF_OPMODE,
55	PLL_OFF_FRAC,
56	PLL_OFF_CAL_VAL,
57	PLL_OFF_MAX_REGS
58};
59
60extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS];
61
62struct pll_vco {
63	unsigned long min_freq;
64	unsigned long max_freq;
65	u32 val;
66};
67
68#define VCO(a, b, c) { \
69	.val = a,\
70	.min_freq = b,\
71	.max_freq = c,\
72}
73
74/**
75 * struct clk_alpha_pll - phase locked loop (PLL)
76 * @offset: base address of registers
77 * @regs: alpha pll register map (see @clk_alpha_pll_regs)
78 * @vco_table: array of VCO settings
79 * @num_vco: number of VCO settings in @vco_table
80 * @flags: bitmask to indicate features supported by the hardware
81 * @clkr: regmap clock handle
82 */
83struct clk_alpha_pll {
84	u32 offset;
85	const u8 *regs;
86
87	const struct pll_vco *vco_table;
88	size_t num_vco;
89#define SUPPORTS_OFFLINE_REQ		BIT(0)
90#define SUPPORTS_FSM_MODE		BIT(2)
91#define SUPPORTS_DYNAMIC_UPDATE	BIT(3)
92#define SUPPORTS_FSM_LEGACY_MODE	BIT(4)
93	u8 flags;
94
95	struct clk_regmap clkr;
96};
97
98/**
99 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
100 * @offset: base address of registers
101 * @regs: alpha pll register map (see @clk_alpha_pll_regs)
102 * @width: width of post-divider
103 * @post_div_shift: shift to differentiate between odd & even post-divider
104 * @post_div_table: table with PLL odd and even post-divider settings
105 * @num_post_div: Number of PLL post-divider settings
106 *
107 * @clkr: regmap clock handle
108 */
109struct clk_alpha_pll_postdiv {
110	u32 offset;
111	u8 width;
112	const u8 *regs;
113
114	struct clk_regmap clkr;
115	int post_div_shift;
116	const struct clk_div_table *post_div_table;
117	size_t num_post_div;
118};
119
120struct alpha_pll_config {
121	u32 l;
122	u32 alpha;
123	u32 alpha_hi;
124	u32 config_ctl_val;
125	u32 config_ctl_hi_val;
126	u32 config_ctl_hi1_val;
127	u32 config_ctl_hi2_val;
128	u32 user_ctl_val;
129	u32 user_ctl_hi_val;
130	u32 user_ctl_hi1_val;
131	u32 test_ctl_val;
132	u32 test_ctl_mask;
133	u32 test_ctl_hi_val;
134	u32 test_ctl_hi_mask;
135	u32 test_ctl_hi1_val;
136	u32 test_ctl_hi2_val;
137	u32 main_output_mask;
138	u32 aux_output_mask;
139	u32 aux2_output_mask;
140	u32 early_output_mask;
141	u32 alpha_en_mask;
142	u32 alpha_mode_mask;
143	u32 pre_div_val;
144	u32 pre_div_mask;
145	u32 post_div_val;
146	u32 post_div_mask;
147	u32 vco_val;
148	u32 vco_mask;
149	u32 status_val;
150	u32 status_mask;
151	u32 lock_det;
152};
153
154extern const struct clk_ops clk_alpha_pll_ops;
155extern const struct clk_ops clk_alpha_pll_fixed_ops;
156extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
157extern const struct clk_ops clk_alpha_pll_postdiv_ops;
158extern const struct clk_ops clk_alpha_pll_huayra_ops;
159extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
160extern const struct clk_ops clk_alpha_pll_stromer_ops;
161extern const struct clk_ops clk_alpha_pll_stromer_plus_ops;
162
163extern const struct clk_ops clk_alpha_pll_fabia_ops;
164extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
165extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;
166
167extern const struct clk_ops clk_alpha_pll_trion_ops;
168extern const struct clk_ops clk_alpha_pll_fixed_trion_ops;
169extern const struct clk_ops clk_alpha_pll_postdiv_trion_ops;
170
171extern const struct clk_ops clk_alpha_pll_lucid_ops;
172#define clk_alpha_pll_fixed_lucid_ops clk_alpha_pll_fixed_trion_ops
173extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;
174extern const struct clk_ops clk_alpha_pll_agera_ops;
175
176extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops;
177extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops;
178extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops;
179
180extern const struct clk_ops clk_alpha_pll_zonda_ops;
181#define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops
182#define clk_alpha_pll_zonda_ole_ops clk_alpha_pll_zonda_ops
183
184extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
185extern const struct clk_ops clk_alpha_pll_reset_lucid_evo_ops;
186#define clk_alpha_pll_reset_lucid_ole_ops clk_alpha_pll_reset_lucid_evo_ops
187extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
188#define clk_alpha_pll_fixed_lucid_ole_ops clk_alpha_pll_fixed_lucid_evo_ops
189extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
190#define clk_alpha_pll_postdiv_lucid_ole_ops clk_alpha_pll_postdiv_lucid_evo_ops
191
192extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;
193#define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops
194
195void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
196			     const struct alpha_pll_config *config);
197void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
198				const struct alpha_pll_config *config);
199void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
200			     const struct alpha_pll_config *config);
201void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
202				const struct alpha_pll_config *config);
203#define clk_lucid_pll_configure(pll, regmap, config) \
204	clk_trion_pll_configure(pll, regmap, config)
205
206void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
207			     const struct alpha_pll_config *config);
208void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
209				 const struct alpha_pll_config *config);
210void clk_lucid_ole_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
211				 const struct alpha_pll_config *config);
212void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
213				  const struct alpha_pll_config *config);
214void clk_stromer_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
215			       const struct alpha_pll_config *config);
216
217#endif
218