subdev/clk/gk20a.c

65 gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll)
71 	pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH);
72 	pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH);
73 	pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH);
77 gk20a_pllg_write_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll)
82 	val = (pll->m & MASK(GPCPLL_COEFF_M_WIDTH)) << GPCPLL_COEFF_M_SHIFT;
83 	val |= (pll->n & MASK(GPCPLL_COEFF_N_WIDTH)) << GPCPLL_COEFF_N_SHIFT;
84 	val |= (pll->pl & MASK(GPCPLL_COEFF_P_WIDTH)) << GPCPLL_COEFF_P_SHIFT;
89 gk20a_pllg_calc_rate(struct gk20a_clk *clk, struct gk20a_pll *pll)
94 	rate = clk->parent_rate * pll->n;
95 	divider = pll->m * clk->pl_to_div(pll->pl);
102 		    struct gk20a_pll *pll)
197 	pll->m = best_m;
198 	pll->n = best_n;
199 	pll->pl = best_pl;
201 	target_freq = gk20a_pllg_calc_rate(clk, pll);
205 		   target_freq / KHZ, pll->m, pll->n, pll->pl,
206 		   clk->pl_to_div(pll->pl));
215 	struct gk20a_pll pll;
219 	gk20a_pllg_read_mnp(clk, &pll);
221 	if (n == pll.n)
224 	/* pll slowdown mode */
230 	pll.n = n;
232 	gk20a_pllg_write_mnp(clk, &pll);
296 gk20a_pllg_program_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll)
316 	gk20a_pllg_write_mnp(clk, pll);
335 gk20a_pllg_program_mnp_slide(struct gk20a_clk *clk, const struct gk20a_pll *pll)
344 		if (pll->m == cur_pll.m && pll->pl == cur_pll.pl)
345 			return gk20a_pllg_slide(clk, pll->n);
355 	cur_pll = *pll;
362 	return gk20a_pllg_slide(clk, pll->n);
465 	struct gk20a_pll pll;
471 		gk20a_pllg_read_mnp(clk, &pll);
472 		return gk20a_pllg_calc_rate(clk, &pll) / GK20A_CLK_GPC_MDIV;
485 					 GK20A_CLK_GPC_MDIV, &clk->pll);
494 	ret = gk20a_pllg_program_mnp_slide(clk, &clk->pll);
496 		ret = gk20a_pllg_program_mnp(clk, &clk->pll);
550 		struct gk20a_pll pll;
553 		gk20a_pllg_read_mnp(clk, &pll);
554 		n_lo = gk20a_pllg_n_lo(clk, &pll);