Searched refs:pll (Results 276 - 300 of 339) sorted by relevance

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/linux-master/drivers/media/pci/bt8xx/
H A Dbttv-driver.c784 if (!btv->pll.pll_crystal)
787 if (btv->pll.pll_ofreq == btv->pll.pll_current) {
792 if (btv->pll.pll_ifreq == btv->pll.pll_ofreq) {
794 if (btv->pll.pll_current == 0)
798 btv->c.nr, btv->pll.pll_ifreq);
801 btv->pll.pll_current = 0;
808 btv->pll.pll_ifreq, btv->pll
[all...]
H A Dbttvp.h326 struct bttv_pll_info pll; member in struct:bttv
/linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dpllnv04.c23 #include "pll.h"
26 #include <subdev/bios/pll.h>
243 nvkm_error(subdev, "unable to compute acceptable pll values\n");
/linux-master/drivers/video/fbdev/nvidia/
H A Dnv_type.h69 u32 pll; member in struct:_riva_hw_state
/linux-master/drivers/media/tuners/
H A Dtda18271-priv.h204 enum tda18271_pll pll, int force);
/linux-master/sound/soc/codecs/
H A Dnau8810.h281 struct nau8810_pll pll; member in struct:nau8810
H A Dtwl6040.c55 int pll; member in struct:twl6040_data
69 /* set of rates for each pll: low-power and high-performance */
887 if (unlikely(priv->pll == TWL6040_SYSCLK_SEL_HPPLL)) {
923 ret = twl6040_set_pll(twl6040, priv->pll, priv->clk_in, priv->sysclk);
941 priv->pll = clk_id;
H A Dnau8822.c673 struct nau8822_pll *pll = &nau8822->pll; local
704 if (pll->mclk_scaler != div) {
729 struct nau8822_pll *pll_param = &nau8822->pll;
/linux-master/include/video/
H A Dsstfb.h239 * pll parameter register:
245 #define DACREG_ICS_PLL_CLK0_1_INI 0x55 /* initial pll M value for freq f1 */
346 struct pll_timing pll; member in struct:sstfb_par
/linux-master/drivers/media/pci/cx88/
H A Dcx88-core.c757 u64 pll; local
766 pll = ofreq * 8 * prescale * (u64)(1 << 20);
767 do_div(pll, xtal);
768 reg = (pll & 0x3ffffff) | (pre[prescale] << 26);
770 pr_err("pll out of range\n");
780 dprintk(1, "pll locked [pre=%d,ofreq=%d]\n",
784 dprintk(1, "pll not locked yet, waiting ...\n");
787 dprintk(1, "pll NOT locked [pre=%d,ofreq=%d]\n", prescale, ofreq);
/linux-master/drivers/clk/ingenic/
H A Djz4755-cgu.c52 "pll", CGU_CLK_PLL,
54 .pll = {
77 "pll half", CGU_CLK_DIV,
/linux-master/drivers/media/i2c/ccs/
H A Dccs.h25 #include "../ccs-pll.h"
246 struct ccs_pll pll; member in struct:ccs_sensor
/linux-master/drivers/accel/ivpu/
H A Dvpu_boot_api.h204 u32 pll[VPU_BOOT_PLL_COUNT][VPU_BOOT_PLL_OUT_COUNT]; member in struct:vpu_boot_params
H A Divpu_hw.h60 } pll; member in struct:ivpu_hw_info
/linux-master/drivers/clk/meson/
H A Da1-pll.c13 #include "a1-pll.h"
17 #include <dt-bindings/clock/amlogic,a1-pll-clkc.h>
345 { .compatible = "amlogic,a1-pll-clkc", },
353 .name = "a1-pll-clkc",
/linux-master/drivers/media/i2c/
H A Dov2659.c210 struct ov2659_pll_ctrl pll; member in struct:ov2659
924 ov2659->pll.ctrl1 = ctrl1_reg;
925 ov2659->pll.ctrl2 = ctrl2_reg;
926 ov2659->pll.ctrl3 = ctrl3_reg;
937 {REG_SC_PLL_CTRL1, ov2659->pll.ctrl1},
938 {REG_SC_PLL_CTRL2, ov2659->pll.ctrl2},
939 {REG_SC_PLL_CTRL3, ov2659->pll.ctrl3},
H A Dmt9m114.c385 } pll; member in struct:mt9m114
749 MT9M114_CAM_SYSCTL_PLL_DIVIDER_VALUE(sensor->pll.m,
750 sensor->pll.n),
753 MT9M114_CAM_SYSCTL_PLL_DIVIDER_P_VALUE(sensor->pll.p), &ret);
2243 sensor->pll.m = 32;
2244 sensor->pll.n = 1;
2245 sensor->pll.p = 7;
2252 sensor->pixrate = clk_get_rate(sensor->clk) * sensor->pll.m
2253 / ((sensor->pll.n + 1) * (sensor->pll
[all...]
/linux-master/drivers/clk/tegra/
H A Dclk-tegra210.c1143 static void pllx_check_defaults(struct tegra_clk_pll *pll) argument
1149 _pll_misc_chk_default(clk_base, pll->params, 0, default_val,
1153 _pll_misc_chk_default(clk_base, pll->params, 1, default_val,
1158 _pll_misc_chk_default(clk_base, pll->params, 2,
1162 _pll_misc_chk_default(clk_base, pll->params, 3, default_val,
1166 _pll_misc_chk_default(clk_base, pll->params, 4, default_val,
1170 _pll_misc_chk_default(clk_base, pll->params, 5, default_val,
1276 static void pllp_check_defaults(struct tegra_clk_pll *pll, bool enabled) argument
1285 _pll_misc_chk_default(clk_base, pll->params, 0, val,
1291 _pll_misc_chk_default(clk_base, pll
1413 tegra210_wait_for_mask(struct tegra_clk_pll *pll, u32 reg, u32 mask) argument
1482 struct tegra_clk_pll *pll = to_clk_pll(hw); local
[all...]
/linux-master/drivers/media/usb/dvb-usb/
H A Ddib0700_devices.c1199 .pll = &dib807x_bw_config_12_mhz,
1216 .pll = &dib807x_bw_config_12_mhz,
1560 .pll = &dib8090_pll_config_12mhz,
1579 .pll = &dib8090_pll_config_12mhz,
1976 .pll = &dib8096p_clock_config_12_mhz,
2109 struct dibx000_bandwidth_config pll; local
2117 memset(&pll, 0, sizeof(struct dibx000_bandwidth_config));
2126 pll.pll_ratio = adc.pll_loopdiv;
2127 pll.pll_prediv = adc.pll_prediv;
2130 state->dib8000_ops.update_pll(fe, &pll, f
2635 struct dibx000_bandwidth_config pll; local
[all...]
/linux-master/drivers/gpu/drm/tegra/
H A Dhdmi.c69 struct regulator *pll; member in struct:tegra_hdmi
1609 err = regulator_enable(hdmi->pll);
1632 regulator_disable(hdmi->pll);
1650 regulator_disable(hdmi->pll);
1841 hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1842 err = PTR_ERR_OR_ZERO(hdmi->pll);
/linux-master/drivers/video/fbdev/matrox/
H A Dmatroxfb_base.h410 struct matrox_pll_features pll; member in struct:matrox_fb_info::__anon2896
476 } pll; member in struct:matrox_fb_info::__anon2902
/linux-master/drivers/clk/
H A DMakefile42 obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
/linux-master/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.c28 #include <subdev/bios/pll.h>
255 * beyond the pll limits. for some reason this causes the chip to
256 * lock up when reading the dac palette regs, so set a valid pll here
266 enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0; local
268 if (nvbios_pll_parse(bios, pll, &pll_lim))
270 nouveau_hw_get_pllvals(dev, pll, &pv);
820 /* NB: no attempt is made to restore the bad pll later on */
/linux-master/drivers/media/dvb-frontends/
H A DMakefile88 obj-$(CONFIG_DVB_PLL) += dvb-pll.o
/linux-master/drivers/clk/rockchip/
H A Dclk-rk3188.c861 struct rockchip_pll_clock *pll = &rk3188_pll_clks[i]; local
864 if (!pll->rate_table)
867 rate = pll->rate_table;

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