Searched refs:mmio_base (Results 101 - 125 of 162) sorted by relevance

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/linux-master/drivers/gpu/drm/i915/gt/
H A Dintel_engine_cs.c491 engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases);
1623 const i915_reg_t mode = RING_MI_MODE(engine->mmio_base);
1633 intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
1768 u32 mmio_base = engine->mmio_base; local
1777 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1811 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1824 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1838 if (I915_SELFTEST_ONLY(!engine->mmio_base))
2411 drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base);
[all...]
H A Dintel_engine_types.h389 u32 mmio_base; member in struct:intel_engine_cs
H A Dselftest_workarounds.c102 const u32 base = engine->mmio_base;
182 RING_NOPID(engine->mmio_base);
438 reg = (reg - engine->mmio_base) & ~RING_FORCE_TO_NONPRIV_ACCESS_MASK;
/linux-master/sound/soc/intel/skylake/
H A Dskl-messages.c251 void __iomem *mmio_base; local
264 mmio_base = pci_ioremap_bar(skl->pci, 4);
265 if (mmio_base == NULL) {
277 ret = ops->init(bus->dev, mmio_base, irq,
309 iounmap(mmio_base);
/linux-master/drivers/ata/
H A Dsata_sx4.c747 void __iomem *mmio_base; local
752 mmio_base = host->iomap[PDC_MMIO_BAR];
755 mmio_base += PDC_CHIP0_OFS;
756 mask = readl(mmio_base + PDC_20621_SEQMASK);
784 mmio_base);
H A Dsata_mv.c1254 static void mv_dump_all_regs(void __iomem *mmio_base, argument
1272 mv_dump_mem(&pdev->dev, mmio_base+0xc00, 0x3c);
1273 mv_dump_mem(&pdev->dev, mmio_base+0xd00, 0x34);
1274 mv_dump_mem(&pdev->dev, mmio_base+0xf00, 0x4);
1275 mv_dump_mem(&pdev->dev, mmio_base+0x1d00, 0x6c);
1277 hc_base = mv_hc_base(mmio_base, hc);
1282 port_base = mv_port_base(mmio_base, p);
/linux-master/drivers/spi/
H A Dspi-pxa2xx.c347 drv_data->lpss_base = drv_data->ssp->mmio_base + config->offset;
1281 ssp->mmio_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1282 if (IS_ERR(ssp->mmio_base))
1283 return PTR_ERR(ssp->mmio_base);
1427 if (!ssp->mmio_base)
H A Dspi-pxa2xx-pci.c287 ssp->mmio_base = pcim_iomap_table(dev)[0];
/linux-master/drivers/gpu/drm/xe/
H A Dxe_query.c155 RING_TIMESTAMP(hwe->mmio_base),
156 RING_TIMESTAMP_UDW(hwe->mmio_base),
H A Dxe_guc_ads.c568 { .reg = RING_MODE(hwe->mmio_base), },
569 { .reg = RING_HWS_PGA(hwe->mmio_base), },
570 { .reg = RING_IMR(hwe->mmio_base), },
H A Dxe_ring_ops.c195 RING_NOPID(hwe->mmio_base).addr, 0);
/linux-master/drivers/scsi/pcmcia/
H A Dnsp_cs.c719 unsigned long mmio_base = SCpnt->device->host->base; local
773 nsp_mmio_fifo32_read(mmio_base, scsi_pointer->ptr,
822 unsigned long mmio_base = SCpnt->device->host->base; local
876 nsp_mmio_fifo32_write(mmio_base, scsi_pointer->ptr,
/linux-master/drivers/pci/hotplug/
H A Dshpchp.h103 unsigned long mmio_base; member in struct:controller
/linux-master/drivers/gpu/drm/i915/selftests/
H A Di915_perf.c307 gpr0 = i915_mmio_reg_offset(GEN8_RING_CS_GPR(stream->engine->mmio_base, 0));
/linux-master/include/ufs/
H A Dufshcd.h798 * @mmio_base: UFSHCI base register address
921 void __iomem *mmio_base; member in struct:ufs_hba
1226 writel((val), (hba)->mmio_base + (reg))
1228 readl((hba)->mmio_base + (reg))
/linux-master/drivers/gpu/drm/i915/gvt/
H A Dscheduler.c273 reg = RING_INSTDONE(engine->mmio_base);
277 reg = RING_ACTHD(engine->mmio_base);
281 reg = RING_ACTHD_UDW(engine->mmio_base);
652 vgpu_vreg_t(workload->vgpu, RING_START(workload->engine->mmio_base)) =
970 ring_base = rq->engine->mmio_base;
/linux-master/drivers/iommu/amd/
H A Diommu.c823 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
824 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
831 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
852 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
853 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
866 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
908 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
913 writel(mask, iommu->mmio_base + MMIO_STATUS_OFFSET);
937 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
1022 writel(tail, iommu->mmio_base
[all...]
/linux-master/drivers/video/fbdev/
H A Dsm712fb.c1500 unsigned long mmio_base; local
1541 mmio_base = pci_resource_start(pdev, 0);
1551 sfb->fb->fix.mmio_start = mmio_base + 0x00400000;
1553 sfb->lfb = ioremap(mmio_base, mmio_addr);
1582 sfb->fb->fix.mmio_start = mmio_base;
1584 sfb->dp_regs = ioremap(mmio_base, 0x00200000 + smem_size);
H A Dpxafb.c98 return __raw_readl(fbi->mmio_base + off);
104 __raw_writel(val, fbi->mmio_base + off);
2301 fbi->mmio_base = devm_platform_ioremap_resource(dev, 0);
2302 if (IS_ERR(fbi->mmio_base)) {
2304 ret = PTR_ERR(fbi->mmio_base);
/linux-master/drivers/ufs/host/
H A Dufs-renesas.c300 ret = readl_poll_timeout_atomic(hba->mmio_base + p->reg,
/linux-master/drivers/thermal/intel/int340x_thermal/
H A Dprocessor_thermal_device.c375 proc_priv->mmio_base = pcim_iomap_table(pdev)[MCHBAR];
/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_gmbus.c873 i915->display.gmbus.mmio_base = VLV_DISPLAY_BASE;
879 i915->display.gmbus.mmio_base = PCH_DISPLAY_BASE;
/linux-master/drivers/pci/
H A Dquirks.c3928 void __iomem *mmio_base; local
3935 mmio_base = pci_iomap(dev, 0, 0);
3936 if (!mmio_base)
3939 iowrite32(0x00000002, mmio_base + MSG_CTL);
3947 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3949 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3950 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3954 val = ioread32(mmio_base + PCH_PP_STATUS);
3962 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3964 pci_iounmap(dev, mmio_base);
[all...]
/linux-master/drivers/scsi/sym53c8xx_2/
H A Dsym_glue.c1334 np->mmio_ba = (u32)dev->mmio_base;
1562 device->mmio_base = bus_addr.start;
1577 if (device->mmio_base)
/linux-master/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_context.c926 *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE(engine->mmio_base));
1617 const u32 GPR0 = engine->mmio_base + 0x600;
1652 const u32 reg = engine->mmio_base + 0x420;

Completed in 288 milliseconds

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