Searched refs:hwirq (Results 151 - 175 of 384) sorted by relevance

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/linux-master/drivers/irqchip/
H A Dirq-stm32-exti.c356 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
464 irq_hw_number_t hwirq; local
466 hwirq = fwspec->param[0];
468 irq_map_generic_chip(d, virq, hwirq);
508 u32 val = BIT(d->hwirq % IRQS_PER_BANK);
520 val |= BIT(d->hwirq % IRQS_PER_BANK);
533 val &= ~BIT(d->hwirq % IRQS_PER_BANK);
623 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
679 u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
720 irq_hw_number_t hwirq; local
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H A Dirq-ath79-misc.c63 unsigned int irq = d->hwirq;
76 unsigned int irq = d->hwirq;
89 unsigned int irq = d->hwirq;
H A Dirq-ts4800.c37 u16 mask = 1 << d->hwirq;
46 u16 mask = 1 << d->hwirq;
65 irq_hw_number_t hwirq)
64 ts4800_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) argument
H A Dirq-riscv-imsic-early.c97 err = generic_handle_domain_irq(imsic->base_domain, vec->hwirq);
99 pr_warn_ratelimited("hwirq 0x%x mapping not found\n", vec->hwirq);
H A Dirq-loongson-pch-lpc.c47 writel(0x1 << d->hwirq, priv->base + LPC_INT_CLR);
57 writel(readl(priv->base + LPC_INT_ENA) & (~(0x1 << (d->hwirq))),
68 writel(readl(priv->base + LPC_INT_ENA) | (0x1 << (d->hwirq)),
76 u32 mask = 0x1 << (d->hwirq);
H A Dirq-apple-aic.c36 * - FIQ hwirq numbers are assigned after true hwirqs, and are per-cpu.
38 * - <0 nr flags> - hwirq #nr
216 * FIQ hwirq index definitions: FIQ sources use the DT binding defines
335 irq_hw_number_t hwirq = irqd_to_hwirq(d); local
338 u32 off = AIC_HWIRQ_DIE(hwirq) * ic->info.die_stride;
339 u32 irq = AIC_HWIRQ_IRQ(hwirq);
346 irq_hw_number_t hwirq = irqd_to_hwirq(d); local
349 u32 off = AIC_HWIRQ_DIE(hwirq) * ic->info.die_stride;
350 u32 irq = AIC_HWIRQ_IRQ(hwirq);
409 irq_hw_number_t hwirq local
638 aic_irq_domain_translate(struct irq_domain *id, struct irq_fwspec *fwspec, unsigned long *hwirq, unsigned int *type) argument
707 irq_hw_number_t hwirq; local
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H A Dirq-al-fic.c113 u32 hwirq; local
120 for_each_set_bit(hwirq, &pending, NR_FIC_IRQS)
121 generic_handle_domain_irq(domain, hwirq);
131 writel_relaxed(BIT(data->hwirq), fic->base + AL_FIC_SET_CAUSE);
H A Dirq-versatile-fpga.c55 u32 mask = 1 << d->hwirq;
63 u32 mask = 1 << d->hwirq;
142 irq_hw_number_t hwirq)
147 if (!(f->valid & BIT(hwirq)))
141 fpga_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) argument
/linux-master/kernel/irq/
H A Dipi-mux.c123 irq_hw_number_t hwirq; local
140 for_each_set_bit(hwirq, &ipis, BITS_PER_TYPE(int))
141 generic_handle_domain_irq(ipi_mux_domain, hwirq);
/linux-master/drivers/pci/controller/
H A Dpcie-xilinx-dma-pl.c202 mask = BIT(data->hwirq + XILINX_PCIE_DMA_IDRN_SHIFT);
215 mask = BIT(data->hwirq + XILINX_PCIE_DMA_IDRN_SHIFT);
229 unsigned int irq, irq_hw_number_t hwirq)
332 switch (d->hwirq) {
340 if (intr_cause[d->hwirq].str)
341 dev_warn(dev, "%s\n", intr_cause[d->hwirq].str);
343 dev_warn(dev, "Unknown IRQ %ld\n", d->hwirq);
370 msg->data = data->hwirq;
418 bitmap_release_region(msi->bitmap, data->hwirq,
510 val &= ~BIT(d->hwirq);
228 xilinx_pl_dma_pcie_intx_map(struct irq_domain *domain, unsigned int irq, irq_hw_number_t hwirq) argument
533 xilinx_pl_dma_pcie_event_map(struct irq_domain *domain, unsigned int irq, irq_hw_number_t hwirq) argument
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/linux-master/include/linux/
H A Dirqdesc.h186 int generic_handle_domain_irq(struct irq_domain *domain, unsigned int hwirq);
187 int generic_handle_domain_irq_safe(struct irq_domain *domain, unsigned int hwirq);
188 int generic_handle_domain_nmi(struct irq_domain *domain, unsigned int hwirq);
/linux-master/drivers/gpio/
H A Dgpio-pcf857x.c228 irq_hw_number_t hwirq = irqd_to_hwirq(data); local
230 gpiochip_enable_irq(&gpio->chip, hwirq);
231 gpio->irq_enabled |= (1 << hwirq);
237 irq_hw_number_t hwirq = irqd_to_hwirq(data); local
239 gpio->irq_enabled &= ~(1 << hwirq);
240 gpiochip_disable_irq(&gpio->chip, hwirq);
H A Dgpio-max77620.c56 gpio->irq_enabled[data->hwirq] = false;
57 gpiochip_disable_irq(chip, data->hwirq);
65 gpiochip_enable_irq(chip, data->hwirq);
66 gpio->irq_enabled[data->hwirq] = true;
93 gpio->irq_type[data->hwirq] = irq_type;
110 unsigned int value, offset = data->hwirq;
H A Dgpio-cadence.c72 iowrite32(BIT(d->hwirq), cgpio->regs + CDNS_GPIO_IRQ_DIS);
82 iowrite32(BIT(d->hwirq), cgpio->regs + CDNS_GPIO_IRQ_EN);
92 u32 mask = BIT(d->hwirq);
130 int hwirq; local
137 for_each_set_bit(hwirq, &status, chip->ngpio)
138 generic_handle_domain_irq(chip->irq.domain, hwirq);
H A Dgpio-sifive.c78 irq_hw_number_t hwirq = irqd_to_hwirq(d); local
79 int offset = hwirq % SIFIVE_GPIO_MAX;
83 gpiochip_enable_irq(gc, hwirq);
106 irq_hw_number_t hwirq = irqd_to_hwirq(d); local
107 int offset = hwirq % SIFIVE_GPIO_MAX;
112 gpiochip_disable_irq(gc, hwirq);
H A Dgpio-uniphier.c218 unsigned int hwirq)
236 if (base <= hwirq && hwirq < base + size)
237 return hwirq - base + parent_base;
263 irq_hw_number_t hwirq; local
270 ret = uniphier_gpio_irq_domain_translate(domain, arg, &hwirq, &type);
274 ret = uniphier_gpio_irq_get_parent_hwirq(priv, hwirq);
285 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
217 uniphier_gpio_irq_get_parent_hwirq(struct uniphier_gpio_priv *priv, unsigned int hwirq) argument
H A Dgpio-graniterapids.c194 irq_hw_number_t hwirq = irqd_to_hwirq(d); local
196 gnr_gpio_irq_mask_unmask(gc, hwirq, true);
197 gpiochip_disable_irq(gc, hwirq);
203 irq_hw_number_t hwirq = irqd_to_hwirq(d); local
205 gpiochip_enable_irq(gc, hwirq);
206 gnr_gpio_irq_mask_unmask(gc, hwirq, false);
275 unsigned int hwirq = i * GNR_PINS_PER_REG + bit_idx; local
277 generic_handle_domain_irq(priv->gc.irq.domain, hwirq);
H A Dgpio-siox.c103 ddata->irq_status &= ~(1 << d->hwirq);
113 ddata->irq_enable &= ~(1 << d->hwirq);
125 ddata->irq_enable |= 1 << d->hwirq;
135 ddata->irq_type[d->hwirq] = type;
/linux-master/drivers/pci/controller/dwc/
H A Dpcie-dw-rockchip.c79 unsigned long reg, hwirq; local
85 for_each_set_bit(hwirq, &reg, 4)
86 generic_handle_domain_irq(rockchip->irq_domain, hwirq);
94 HIWORD_UPDATE_BIT(BIT(data->hwirq)),
101 HIWORD_DISABLE_BIT(BIT(data->hwirq)),
113 irq_hw_number_t hwirq)
112 rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq, irq_hw_number_t hwirq) argument
/linux-master/drivers/watchdog/
H A Docteon-wdt-main.c313 int hwirq; local
317 hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | coreid;
318 irq = irq_find_mapping(domain, hwirq);
353 int hwirq; local
371 hwirq = WD_BLOCK_NUMBER << 12 | 0x200 | core;
372 irq = irq_create_mapping(domain, hwirq);
/linux-master/arch/arm/mach-exynos/
H A Dsuspend.c42 * @hwirq: Hardware IRQ signal of the PMU
46 unsigned int hwirq; member in struct:exynos_wkup_irq
111 if (wkup_irq->hwirq == data->hwirq) {
138 unsigned long *hwirq,
149 *hwirq = fwspec->param[1];
163 irq_hw_number_t hwirq; local
171 hwirq = fwspec->param[1];
174 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
136 exynos_pmu_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, unsigned long *hwirq, unsigned int *type) argument
/linux-master/drivers/mfd/
H A Dstmfx.c186 stmfx->irq_src &= ~BIT(data->hwirq % 8);
193 stmfx->irq_src |= BIT(data->hwirq % 8);
234 irq_hw_number_t hwirq)
258 int hwirq; local
260 for (hwirq = 0; hwirq < STMFX_REG_IRQ_SRC_MAX; hwirq++)
261 irq_dispose_mapping(irq_find_mapping(stmfx->irq_domain, hwirq));
233 stmfx_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq) argument
/linux-master/drivers/spmi/
H A Dspmi-pmic-arb.c119 #define hwirq_to_sid(hwirq) (((hwirq) >> 28) & 0xF)
120 #define hwirq_to_per(hwirq) (((hwirq) >> 20) & 0xFF)
121 #define hwirq_to_irq(hwirq) (((hwirq) >> 16) & 0x7)
122 #define hwirq_to_apid(hwirq) (((hwirq) >> 0) & 0x3FF)
602 u8 sid = hwirq_to_sid(d->hwirq);
603 u8 per = hwirq_to_per(d->hwirq);
944 qpnpint_irq_domain_map(struct spmi_pmic_arb_bus *bus, struct irq_domain *domain, unsigned int virq, irq_hw_number_t hwirq, unsigned int type) argument
971 irq_hw_number_t hwirq; local
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/linux-master/arch/powerpc/include/asm/
H A Dpnv-ocxl.h67 int pnv_ocxl_get_xsl_irq(struct pci_dev *dev, int *hwirq);
/linux-master/arch/xtensa/include/asm/
H A Dtraps.h60 void do_IRQ(int hwirq, struct pt_regs *regs);

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