Searched refs:hwirq (Results 101 - 125 of 384) sorted by relevance

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/linux-master/drivers/irqchip/
H A Dirq-riscv-imsic-state.h23 unsigned int hwirq; member in struct:imsic_vector
97 struct imsic_vector *imsic_vector_alloc(unsigned int hwirq, const struct cpumask *mask);
H A Dirq-owl-sirq.c143 data->hwirq);
152 owl_sirq_clear_set_extctl(chip_data, INTC_EXTCTL_EN, 0, data->hwirq);
160 owl_sirq_clear_set_extctl(chip_data, 0, INTC_EXTCTL_EN, data->hwirq);
194 data->hwirq);
213 unsigned long *hwirq,
222 *hwirq = fwspec->param[0];
234 irq_hw_number_t hwirq; local
241 ret = owl_sirq_domain_translate(domain, fwspec, &hwirq, &type);
259 irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &owl_sirq_chip,
265 parent_fwspec.param[1] = chip_data->ext_irqs[hwirq];
211 owl_sirq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, unsigned long *hwirq, unsigned int *type) argument
[all...]
H A Dirq-qcom-mpm.c72 /* MPM pin map to GIC hwirq */
75 irq_hw_number_t hwirq; member in struct:mpm_gic_map
112 int pin = d->hwirq;
159 int pin = d->hwirq;
248 parent_fwspec.param[1] = map->hwirq;
309 static bool gic_hwirq_is_mapped(struct mpm_gic_map *maps, int cnt, u32 hwirq) argument
314 if (maps[i].hwirq == hwirq)
363 u32 pin, hwirq; local
366 of_property_read_u32_index(np, "qcom,mpm-pin-map", i * 2 + 1, &hwirq);
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H A Dirq-tegra.c87 mask = BIT(d->hwirq % 32);
118 u32 irq = d->hwirq;
217 unsigned long *hwirq,
228 *hwirq = fwspec->param[1];
243 irq_hw_number_t hwirq; local
251 hwirq = fwspec->param[1];
252 if (hwirq >= (num_ictlrs * 32))
256 int ictlr = (hwirq + i) / 32;
258 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
215 tegra_ictlr_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, unsigned long *hwirq, unsigned int *type) argument
H A Dirq-loongson-htvec.c69 writel(BIT(VEC_REG_BIT(d->hwirq)),
70 priv->base + VEC_REG_IDX(d->hwirq) * 4);
81 addr += VEC_REG_IDX(d->hwirq) * 4;
83 reg &= ~BIT(VEC_REG_BIT(d->hwirq));
96 addr += VEC_REG_IDX(d->hwirq) * 4;
98 reg |= BIT(VEC_REG_BIT(d->hwirq));
114 unsigned long hwirq; local
118 ret = irq_domain_translate_onecell(domain, arg, &hwirq, &type);
123 irq_domain_set_info(domain, virq + i, hwirq + i, &htvec_irq_chip,
H A Dqcom-pdc.c88 __pdc_enable_intr(d->hwirq, on);
168 old_pdc_type = pdc_reg_read(IRQ_i_CFG, d->hwirq);
170 pdc_reg_write(IRQ_i_CFG, d->hwirq, pdc_type);
229 irq_hw_number_t hwirq; local
233 ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type);
237 if (hwirq == GPIO_NO_WAKE_IRQ)
240 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
245 region = get_pin_region(hwirq);
258 parent_fwspec.param[1] = pin_to_hwirq(region, hwirq);
344 pr_err("%pOF: failed to init PDC pin-hwirq mappin
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H A Dirq-bcm6345-l1.c128 irq_hw_number_t hwirq; local
133 for_each_set_bit(hwirq, &pending, IRQS_PER_WORD) {
134 if (generic_handle_domain_irq(intc->domain, base + hwirq))
145 u32 word = d->hwirq / IRQS_PER_WORD;
146 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
157 u32 word = d->hwirq / IRQS_PER_WORD;
158 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
191 u32 word = d->hwirq / IRQS_PER_WORD;
192 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
H A Dirq-bcm7038-l1.c137 int hwirq; local
144 for_each_set_bit(hwirq, &pending, IRQS_PER_WORD)
145 generic_handle_domain_irq(intc->domain, base + hwirq);
154 u32 word = d->hwirq / IRQS_PER_WORD;
155 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
165 u32 word = d->hwirq / IRQS_PER_WORD;
166 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
179 __bcm7038_l1_unmask(d, intc->affinity[d->hwirq]);
189 __bcm7038_l1_mask(d, intc->affinity[d->hwirq]);
200 irq_hw_number_t hw = d->hwirq;
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H A Dirq-gic-v3.c84 * with hwirq IDs, is simplified by accounting for all 16.
159 static enum gic_intid_range __get_intid_range(irq_hw_number_t hwirq) argument
161 switch (hwirq) {
181 return __get_intid_range(d->hwirq);
199 irq_hw_number_t hwirq = irqd_to_hwirq(d); local
213 switch (__get_intid_range(hwirq)) {
215 chip = (hwirq - 32) / 320;
314 *index = d->hwirq;
322 *index = d->hwirq - EPPI_BASE_INTID + 32;
325 *index = d->hwirq
494 __gic_get_ppi_index(irq_hw_number_t hwirq) argument
506 __gic_get_rdist_index(irq_hw_number_t hwirq) argument
1559 gic_irq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, unsigned long *hwirq, unsigned int *type) argument
1636 irq_hw_number_t hwirq; local
1665 fwspec_is_partitioned_ppi(struct irq_fwspec *fwspec, irq_hw_number_t hwirq) argument
1691 irq_hw_number_t hwirq; local
1727 partition_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, unsigned long *hwirq, unsigned int *type) argument
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H A Dirq-sa11x0.c39 reg &= ~BIT(d->hwirq);
48 reg |= BIT(d->hwirq);
54 return sa11x0_sc_set_wake(d->hwirq, on);
66 unsigned int irq, irq_hw_number_t hwirq)
65 sa1100_normal_irqdomain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) argument
H A Dirq-mvebu-pic.c47 writel(1 << d->hwirq, pic->base + PIC_CAUSE);
56 reg |= (1 << d->hwirq);
66 reg &= ~(1 << d->hwirq);
85 irq_hw_number_t hwirq)
84 mvebu_pic_irq_map(struct irq_domain *domain, unsigned int virq, irq_hw_number_t hwirq) argument
H A Dirq-ls-scfg-msi.c92 msg->data = data->hwirq;
177 pos = d->hwirq;
179 pr_err("failed to teardown msi. Invalid hwirq %d\n", pos);
198 int pos, size, hwirq; local
208 hwirq = ((msir->bit_end - pos) << msi_data->cfg->ibs_shift) |
210 generic_handle_domain_irq(msi_data->parent, hwirq);
244 int virq, i, hwirq; local
280 hwirq = i << msi_data->cfg->ibs_shift | msir->index;
281 bitmap_clear(msi_data->used, hwirq, 1);
291 int i, hwirq; local
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/linux-master/arch/mips/sgi-ip30/
H A Dip30-irq.c141 heart_write(BIT_ULL(d->hwirq), &heart_regs->clear_isr);
149 clear_bit(d->hwirq, mask);
158 clear_bit(d->hwirq, mask);
160 heart_write(BIT_ULL(d->hwirq), &heart_regs->clear_isr);
168 set_bit(d->hwirq, mask);
207 int hwirq; local
216 hwirq = heart_alloc_int();
217 if (hwirq < 0) {
221 irq_domain_set_info(domain, virq, hwirq, &heart_irq_chip, hd,
237 clear_bit(irqd->hwirq, heart_irq_ma
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/linux-master/drivers/pinctrl/qcom/
H A Dpinctrl-msm.c218 !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux))
260 test_and_clear_bit(d->hwirq, pctrl->disabled_for_mux)) {
265 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
855 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
858 g = &pctrl->soc->groups[d->hwirq];
889 clear_bit(d->hwirq, pctrl->enabled_irqs);
905 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
908 g = &pctrl->soc->groups[d->hwirq];
917 set_bit(d->hwirq, pctrl->enabled_irqs);
927 gpiochip_enable_irq(gc, d->hwirq);
[all...]
/linux-master/drivers/gpio/
H A Dgpio-rcar.c97 irq_hw_number_t hwirq = irqd_to_hwirq(d); local
99 gpio_rcar_write(p, INTMSK, ~BIT(hwirq));
100 gpiochip_disable_irq(gc, hwirq);
107 irq_hw_number_t hwirq = irqd_to_hwirq(d); local
109 gpiochip_enable_irq(gc, hwirq);
110 gpio_rcar_write(p, MSKCLR, BIT(hwirq));
114 unsigned int hwirq,
129 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
132 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
136 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, bot
113 gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p, unsigned int hwirq, bool active_high_rising_edge, bool level_trigger, bool both) argument
152 unsigned int hwirq = irqd_to_hwirq(d); local
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H A Dgpio-rtd.c383 unsigned int hwirq; local
406 hwirq = i + j - 1;
407 if (rtd_gpio_check_ie(data, hwirq)) {
408 int girq = irq_find_mapping(domain, hwirq);
413 generic_handle_domain_irq(domain, hwirq);
425 irq_hw_number_t hwirq = irqd_to_hwirq(d); local
428 u32 clr_mask = BIT(hwirq % 31) << 1;
430 u32 ie_mask = BIT(hwirq % 32);
436 ie_reg_offset = rtd_gpio_ie_offset(data, hwirq);
437 gpa_reg_offset = rtd_gpio_gpa_offset(data, hwirq);
456 irq_hw_number_t hwirq = irqd_to_hwirq(d); local
476 irq_hw_number_t hwirq = irqd_to_hwirq(d); local
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H A Dgpio-xlp.c107 xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
108 __clear_bit(d->hwirq, priv->gpio_enabled_mask);
120 xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x0);
121 xlp_gpio_set_reg(priv->gpio_intr_stat, d->hwirq, 0x1);
122 __clear_bit(d->hwirq, priv->gpio_enabled_mask);
133 xlp_gpio_set_reg(priv->gpio_intr_en, d->hwirq, 0x1);
134 __set_bit(d->hwirq, priv->gpio_enabled_mask);
165 xlp_gpio_set_reg(priv->gpio_intr_type, d->hwirq, irq_type);
166 xlp_gpio_set_reg(priv->gpio_intr_pol, d->hwirq, pol);
H A Dgpio-brcmstb.c91 static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq, argument
94 return hwirq - bank->gc.offset;
98 unsigned int hwirq, bool enable)
102 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));
120 int hwirq = offset + gc->offset; local
122 if (hwirq >= priv->num_gpios)
124 return irq_create_mapping(priv->irq_domain, hwirq);
134 brcmstb_gpio_set_imask(bank, d->hwirq, false);
142 brcmstb_gpio_set_imask(bank, d->hwirq, true);
150 u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, ban
97 brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank, unsigned int hwirq, bool enable) argument
297 brcmstb_gpio_hwirq_to_bank( struct brcmstb_gpio_priv *priv, irq_hw_number_t hwirq) argument
320 brcmstb_gpio_irq_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) argument
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/linux-master/arch/arm/mach-omap2/
H A Domap-wakeupgen.c138 _wakeupgen_clear(d->hwirq, irq_target_cpu[d->hwirq]);
151 _wakeupgen_set(d->hwirq, irq_target_cpu[d->hwirq]);
179 if (inverted && d->hwirq != SYS_NIRQ1_EXT_SYS_IRQ_1 &&
180 d->hwirq != SYS_NIRQ2_EXT_SYS_IRQ_2)
182 d->hwirq);
490 unsigned long *hwirq,
501 *hwirq = fwspec->param[1];
515 irq_hw_number_t hwirq; local
488 wakeupgen_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec, unsigned long *hwirq, unsigned int *type) argument
[all...]
/linux-master/drivers/pci/controller/
H A Dpcie-altera-msi.c92 phys_addr_t addr = msi->vector_phy + (data->hwirq * sizeof(u32));
96 msg->data = data->hwirq;
99 (int)data->hwirq, msg->address_hi, msg->address_lo);
154 if (!test_bit(d->hwirq, msi->used)) {
156 d->hwirq);
158 __clear_bit(d->hwirq, msi->used);
160 mask &= ~(1 << d->hwirq);
/linux-master/arch/powerpc/platforms/powernv/
H A Dopal-irqchip.c49 int hwirq; local
51 hwirq = fls64(e) - 1;
52 e &= ~BIT_ULL(hwirq);
56 generic_handle_domain_irq(opal_event_irqchip.domain, hwirq);
79 clear_bit(d->hwirq, &opal_event_irqchip.mask);
84 set_bit(d->hwirq, &opal_event_irqchip.mask);
113 irq_hw_number_t hwirq)
112 opal_event_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) argument
/linux-master/arch/arc/kernel/
H A Dintc-arcv2.c101 write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
107 write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
114 write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
/linux-master/drivers/scsi/cxlflash/
H A Docxl_hw.h14 int hwirq; member in struct:ocxlflash_irqs
/linux-master/drivers/mfd/
H A Dlp8788-irq.c66 irqd->enabled[data->hwirq] = 1;
73 irqd->enabled[data->hwirq] = 0;
86 enum lp8788_int_id irq = data->hwirq;
132 irq_hw_number_t hwirq)
131 lp8788_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq) argument
/linux-master/arch/arc/include/asm/
H A Dsmp.h39 * Takes @cpu and @hwirq to which the arch-common ISR is hooked up
41 extern int smp_ipi_irq_setup(int cpu, irq_hw_number_t hwirq);

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