1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * CXL Flash Device Driver
4 *
5 * Written by: Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
6 *	       Uma Krishnan <ukrishn@linux.vnet.ibm.com>, IBM Corporation
7 *
8 * Copyright (C) 2018 IBM Corporation
9 */
10
11#define OCXL_MAX_IRQS	4	/* Max interrupts per process */
12
13struct ocxlflash_irqs {
14	int hwirq;
15	u32 virq;
16	void __iomem *vtrig;
17};
18
19/* OCXL hardware AFU associated with the host */
20struct ocxl_hw_afu {
21	struct ocxlflash_context *ocxl_ctx; /* Host context */
22	struct pci_dev *pdev;		/* PCI device */
23	struct device *dev;		/* Generic device */
24	bool perst_same_image;		/* Same image loaded on perst */
25
26	struct ocxl_fn_config fcfg;	/* DVSEC config of the function */
27	struct ocxl_afu_config acfg;	/* AFU configuration data */
28
29	int fn_actag_base;		/* Function acTag base */
30	int fn_actag_enabled;		/* Function acTag number enabled */
31	int afu_actag_base;		/* AFU acTag base */
32	int afu_actag_enabled;		/* AFU acTag number enabled */
33
34	phys_addr_t ppmmio_phys;	/* Per process MMIO space */
35	phys_addr_t gmmio_phys;		/* Global AFU MMIO space */
36	void __iomem *gmmio_virt;	/* Global MMIO map */
37
38	void *link_token;		/* Link token for the SPA */
39	struct idr idr;			/* IDR to manage contexts */
40	int max_pasid;			/* Maximum number of contexts */
41	bool is_present;		/* Function has AFUs defined */
42};
43
44enum ocxlflash_ctx_state {
45	CLOSED,
46	OPENED,
47	STARTED
48};
49
50struct ocxlflash_context {
51	struct ocxl_hw_afu *hw_afu;	/* HW AFU back pointer */
52	struct address_space *mapping;	/* Mapping for pseudo filesystem */
53	bool master;			/* Whether this is a master context */
54	int pe;				/* Process element */
55
56	phys_addr_t psn_phys;		/* Process mapping */
57	u64 psn_size;			/* Process mapping size */
58
59	spinlock_t slock;		/* Protects irq/fault/event updates */
60	wait_queue_head_t wq;		/* Wait queue for poll and interrupts */
61	struct mutex state_mutex;	/* Mutex to update context state */
62	enum ocxlflash_ctx_state state;	/* Context state */
63
64	struct ocxlflash_irqs *irqs;	/* Pointer to array of structures */
65	int num_irqs;			/* Number of interrupts */
66	bool pending_irq;		/* Pending interrupt on the context */
67	ulong irq_bitmap;		/* Bits indicating pending irq num */
68
69	u64 fault_addr;			/* Address that triggered the fault */
70	u64 fault_dsisr;		/* Value of dsisr register at fault */
71	bool pending_fault;		/* Pending translation fault */
72};
73