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27030ff7 |
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27-Nov-2023 |
Richard Acayan <mailingradian@gmail.com> |
pinctrl: qcom: fail to retrieve configuration from invalid pin groups The pinconf-groups debugfs file dumps each valid configuration item of all pin groups. Some platforms and devices may have pin groups which cannot be accessed, according to commit 691bf5d5a7bf ("pinctrl: qcom: Don't allow protected pins to be requested"). Fail for each configuration item of an invalid pin group by checking the GPIO chip's valid mask. The validity of the pin group cannot be checked in the generic pinconf dump (function "pinconf_generic_dump_one"), as it does not directly interact with the gpiochip or the pinmux callbacks (which would give it access to the request callback). Instead, an entry contains the ID and name of the pingroup with no properties when all items fail. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Link: https://lore.kernel.org/r/20231128020202.728156-3-mailingradian@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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76b446f5 |
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06-Nov-2023 |
Neil Armstrong <neil.armstrong@linaro.org> |
pinctrl: qcom: handle intr_target_reg wakeup_present/enable bits New platforms uses a new set of bits to control the wakeirq delivery to the PDC block. The intr_wakeup_present_bit indicates if the GPIO supports wakeirq and intr_wakeup_enable_bit enables wakeirq delivery to the PDC block. While the name seems to imply this only enables wakeup events, it is required to allow interrupts events to the PDC block. Enable this bit in the irq resource request/free if: - gpio is in wakeirq map - has the intr_wakeup_present_bit - the intr_wakeup_enable_bit is set Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-tlmm-v3-2-0e179c368933@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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22ee670a |
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09-Oct-2023 |
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> |
pinctrl: qcom/msm: Convert to platform remove callback returning void The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new(), which already returns void. Eventually after all drivers are converted, .remove_new() will be renamed to .remove(). To convert all those qcom pinctrl drivers, make msm_pinctrl_remove() return void (instead of zero) and use .remove_new in all drivers. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20231009162510.335208-3-u.kleine-koenig@pengutronix.de Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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9757300d |
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09-Aug-2023 |
Ninad Naik <quic_ninanaik@quicinc.com> |
pinctrl: qcom: Add intr_target_width field to support increased number of interrupt targets SA8775 and newer target have added support for an increased number of interrupt targets. To implement this change, the intr_target field, which is used to configure the interrupt target in the interrupt configuration register is increased from 3 bits to 4 bits. In accordance to these updates, a new intr_target_width member is introduced in msm_pingroup structure. This member stores the value of width of intr_target field in the interrupt configuration register. This value is used to dynamically calculate and generate mask for setting the intr_target field. By default, this mask is set to 3 bit wide, to ensure backward compatibility with the older targets. Fixes: 4b6b18559927 ("pinctrl: qcom: add the tlmm driver sa8775p platforms") Tested-by: Andrew Halaney <ahalaney@redhat.com> # sa8775p-ride Signed-off-by: Ninad Naik <quic_ninanaik@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20230809100634.3961-1-quic_ninanaik@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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6a16d1a5 |
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14-May-2023 |
Rohit Agarwal <quic_rohiagar@quicinc.com> |
pinctrl: qcom: Refactor generic qcom pinctrl driver Reuse the generic pingroup struct from pinctrl.h in msm_pingroup along with the macro defined. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1684133170-18540-3-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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c7a291db |
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14-May-2023 |
Rohit Agarwal <quic_rohiagar@quicinc.com> |
pinctrl: qcom: Remove the msm_function struct Remove the msm_function struct to reuse the generic pinfunction struct. Also, define a generic PINFUNCTION macro that can be used across qcom target specific pinctrl files to avoid code repetition. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1684133170-18540-2-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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b391efee |
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07-Apr-2023 |
Douglas Anderson <dianders@chromium.org> |
pinctrl: qcom: Add "and" to PIN_CONFIG_INPUT_ENABLE comment The comment recently added talking about PIN_CONFIG_INPUT_ENABLE is clearly missing the word "and". Comments live forever, so let's fix it. Fixes: e49eabe3e13f ("pinctrl: qcom: Support OUTPUT_ENABLE; deprecate INPUT_ENABLE") Reported-by: Stephen Boyd <swboyd@chromium.org> Link: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/4409769/comment/9a1d5def_e1e71db7/ Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20230407142859.1.Ia5d70e320b60d6707c6182879097708e49b8b519@changeid Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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713834cf |
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06-Mar-2023 |
Md Sadre Alam <quic_mdalam@quicinc.com> |
pinctrl: qcom: Use devm_platform_get_and_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> Link: https://lore.kernel.org/r/20230306144641.21955-1-quic_mdalam@quicinc.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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e49eabe3 |
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23-Mar-2023 |
Douglas Anderson <dianders@chromium.org> |
pinctrl: qcom: Support OUTPUT_ENABLE; deprecate INPUT_ENABLE The Qualcomm pinctrl driver has been violating the documented meaning of PIN_CONFIG_INPUT_ENABLE. That documentation says: Note that this does not affect the pin's ability to drive output. ...yet the Qualcomm driver's sole action when asked to "enable input" on a pin is to disable its output. The Qualcomm driver's implementation stems from the fact that "output-disable" is a "new" property from 2017. It was introduced in commit 425562429d4f ("pinctrl: generic: Add output-enable property"). The "input-enable" handling in Qualcomm drivers is from 2015 introduced in commit 407f5e392f9c ("pinctrl: qcom: handle input-enable pinconf property"). Let's change the Qualcomm driver to move us in the right direction. As part of this: 1. We'll now support PIN_CONFIG_OUTPUT_ENABLE 2. We'll still support using PIN_CONFIG_INPUT_ENABLE to disable a pin's output (in violation of the docs) with a big comment in the code. This is needed because old device trees have "input-enable" in them and, in some cases, people might need the old behavior. While we could programmatically change all old device trees, it doesn't really hurt to keep supporting the old behavior and we're _supposed_ to try to be compatible with old device trees anyway. It can also be noted that the PIN_CONFIG_INPUT_ENABLE handling code seems to have purposefully ignored its argument. That means that old boards that had _either_ "input-disable" or "input-enable" in them would have had the effect of disabling a pin's output. While we could change this behavior, since we're only leaving the PIN_CONFIG_INPUT_ENABLE there for backward compatibility we might as well be fully backward compatible. NOTE: despite the fact that we'll still support PIN_CONFIG_INPUT_ENABLE for _setting_ config, we take it away from msm_config_group_get(). This appears to be only used for populating debugfs and fixing debugfs to "output enabled" where relevant instead of "input enabled" makes more sense and has more truthiness. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20230323102605.8.Id740ae6a993f9313b58add6b10f6a92795d510d4@changeid Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
3bf90eca |
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03-Feb-2023 |
Elliot Berman <quic_eberman@quicinc.com> |
firmware: qcom_scm: Move qcom_scm.h to include/linux/firmware/qcom/ Move include/linux/qcom_scm.h to include/linux/firmware/qcom/qcom_scm.h. This removes 1 of a few remaining Qualcomm-specific headers into a more approciate subdirectory under include/. Suggested-by: Bjorn Andersson <andersson@kernel.org> Signed-off-by: Elliot Berman <quic_eberman@quicinc.com> Reviewed-by: Guru Das Srinagesh <quic_gurus@quicinc.com> Acked-by: Mukesh Ojha <quic_mojha@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230203210956.3580811-1-quic_eberman@quicinc.com
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099f37a5 |
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09-Feb-2023 |
Abel Vesa <abel.vesa@linaro.org> |
pinctrl: qcom: Add support for i2c specific pull feature Add support for the new i2c_pull property introduced for SM8550 setting a I2C specific pull mode on I2C able pins. Add the bit to the SM8550 specific driver while at it. Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230209074510.4153294-1-abel.vesa@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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9bd73ce0 |
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13-Jan-2023 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: qcom: Unify accessing to device fwnode The device fwnode can be get via dev_fwnode() getter. Use it where it makes sense. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20230113220703.45686-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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cf2fc8f8 |
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22-Nov-2022 |
ye xingchen <ye.xingchen@zte.com.cn> |
pinctrl: qcom: remove duplicate included header files linux/seq_file.h is included more than once. Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn> Link: https://lore.kernel.org/r/202211221631577017318@zte.com.cn Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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aa9430f8 |
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07-Oct-2022 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: qcom: Add missing header(s) Do not imply that some of the generic headers may be always included. Instead, include explicitly what we are direct user of. While at it, sort headers alphabetically. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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f764b848 |
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13-Oct-2022 |
Richard Acayan <mailingradian@gmail.com> |
pinctrl: qcom: do not reinitialize gpio valid mask It may be necessary for some devices to specify reserved gpios in the device-specific DTS, in addition to the reserved gpios common to all devices with a given SoC. Remove this bitmap_fill() call so that the settings applied to the gpio valid mask by DTS are not overridden by the driver's reserved gpios. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Reviewed-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221014001934.4995-3-mailingradian@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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d21f4b7f |
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14-Oct-2022 |
Douglas Anderson <dianders@chromium.org> |
pinctrl: qcom: Avoid glitching lines when we first mux to output Back in the description of commit e440e30e26dd ("arm64: dts: qcom: sc7180: Avoid glitching SPI CS at bootup on trogdor") we described a problem that we were seeing on trogdor devices. I'll re-summarize here but you can also re-read the original commit. On trogdor devices, the BIOS is setting up the SPI chip select as: - mux special function (SPI chip select) - output enable - output low (unused because we've muxed as special function) In the kernel, however, we've moved away from using the chip select line as special function. Since the kernel wants to fully control the chip select it's far more efficient to treat the line as a GPIO rather than sending packet-like commands to the GENI firmware every time we want the line to toggle. When we transition from how the BIOS had the pin configured to how the kernel has the pin configured we end up glitching the line. That's because we _first_ change the mux of the line and then later set its output. This glitch is bad and can confuse the device on the other end of the line. The old commit e440e30e26dd ("arm64: dts: qcom: sc7180: Avoid glitching SPI CS at bootup on trogdor") fixed the glitch, though the solution was far from elegant. It essentially did the thing that everyone always hates: encoding a sequential program in device tree, even if it's a simple one. It also, unfortunately, got broken by commit b991f8c3622c ("pinctrl: core: Handling pinmux and pinconf separately"). After that commit we did all the muxing _first_ even though the config (set the pin to output high) was listed first. :( I looked at ideas for how to solve this more properly. My first thought was to use the "init" pinctrl state. In theory the "init" pinctrl state is supposed to be exactly for achieving glitch-free transitions. My dream would have been for the "init" pinctrl to do nothing at all. That would let us delay the automatic pin muxing until the driver could set things up and call pinctrl_init_done(). In other words, my dream was: /* Request the GPIO; init it 1 (because DT says GPIO_ACTIVE_LOW) */ devm_gpiod_get_index(dev, "cs", GPIOD_OUT_LOW); /* Output should be right, so we can remux, yay! */ pinctrl_init_done(dev); Unfortunately, it didn't work out. The primary reason is that the MSM GPIO driver implements gpio_request_enable(). As documented in pinmux.h, that function automatically remuxes a line as a GPIO. ...and it does this remuxing _before_ specifying the output of the pin. You can see in gpiod_get_index() that we call gpiod_request() before gpiod_configure_flags(). gpiod_request() isn't passed any flags so it has no idea what the eventual output will be. We could have debates about whether or not the automatic remuxing to GPIO for the MSM pinctrl was a good idea or not, but at this point I think there is a plethora of code that's relying on it and I certainly wouldn't suggest changing it. Alternatively, we could try to come up with a way to pass the initial output state to gpio_request_enable() and plumb all that through. That seems like it would be doable, but we'd have to plumb it through several layers in the stack. This patch implements yet another alternative. Here, we specifically avoid glitching the first time a pin is muxed to GPIO function if the direction of the pin is output. The idea is that we can read the state of the pin before we set the mux and make sure that the re-mux won't change the state. NOTES: - We only do this the first time since later swaps between mux states might want to preserve the old output value. In other words, I wouldn't want to break a driver that did: gpiod_set_value(g, 1); pinctrl_select_state(pinctrl, special_state); pinctrl_select_default_state(); /* We should be driving 1 even if "special_state" made the pin 0 */ - It's safe to do this the first time since the driver _couldn't_ have explicitly set a state. In order to even be able to control the GPIO (at least using gpiod) we have to have requested it which would have counted as the first mux. - In theory, instead of keeping track of the first time a pin was set as a GPIO we could enable the glitch-free behavior only when msm_pinmux_request_gpio() is in the callchain. That works an enables my "dream" implementation above where we use an "init" state to solve this. However, it's nice not to have to do this. By handling just the first transition to GPIO we can simply let the normal "default" remuxing happen and we can be assured that there won't be a glitch. Before this change I could see the glitch reported on the EC console when booting. It would say this when booting the kernel: Unexpected state 1 in CSNRE ISR After this change there is no error reported. Note that I haven't reproduced the original problem described in e440e30e26dd ("arm64: dts: qcom: sc7180: Avoid glitching SPI CS at bootup on trogdor") but I could believe it might happen in certain timing conditions. Fixes: b991f8c3622c ("pinctrl: core: Handling pinmux and pinconf separately") Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20221014103217.1.I656bb2c976ed626e5d37294eb252c1cf3be769dc@changeid Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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14dbe186 |
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19-Apr-2022 |
Marc Zyngier <maz@kernel.org> |
pinctrl: msmgpio: Make the irqchip immutable Prevent gpiolib from messing with the irqchip by advertising the irq_chip structure as immutable, making it const, and adding the various calls that gpiolib relies upon. Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220419141846.598305-8-maz@kernel.org
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06e12b79 |
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10-Feb-2022 |
Jonathan Marek <jonathan@marek.ca> |
pinctrl: qcom: print egpio mode in debugfs When egpio_enable bit is cleared, the gpio is driven by SSC/LPASS TLMM and the APSS TLMM settings are ignored. Reflect that in the debugfs dump. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20220210131210.24605-2-jonathan@marek.ca Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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b9dc88de |
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13-Jan-2022 |
Manivannan Sadhasivam <mani@kernel.org> |
pinctrl: qcom: Return -EINVAL for setting affinity if no IRQ parent The MSM GPIO IRQ controller relies on the parent IRQ controller to set the CPU affinity for the IRQ. And this is only valid if there is any wakeup parent available and defined in DT. For the case of no parent IRQ controller defined in DT, msm_gpio_irq_set_affinity() and msm_gpio_irq_set_vcpu_affinity() should return -EINVAL instead of 0 as the affinity can't be set. Otherwise, below warning will be printed by genirq: genirq: irq_chip msmgpio did not update eff. affinity mask of irq 70 Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20220113162617.131697-1-manivannan.sadhasivam@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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8a8d6bbe |
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14-Dec-2021 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: Get rid of duplicate of_node assignment in the drivers GPIO library does copy the of_node from the parent device of the GPIO chip, there is no need to repeat this in the individual drivers. Remove these assignment all at once. For the details one may look into the of_gpio_dev_init() implementation. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20211214125855.33207-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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bebc49c1 |
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15-Nov-2021 |
Prasad Sodagudi <psodagud@codeaurora.org> |
pinctrl: qcom: Add egpio feature support egpio is a scheme which allows special power Island Domain IOs (LPASS,SSC) to be reused as regular chip GPIOs by muxing regular TLMM functions with Island Domain functions. With this scheme, an IO can be controlled both by the cpu running linux and the Island processor. This provides great flexibility to re-purpose the Island IOs for regular TLMM usecases. 2 new bits are added to ctl_reg, egpio_present is a read only bit which shows if egpio feature is available or not on a given gpio. egpio_enable is the read/write bit and only effective if egpio_present is 1. Once its set, the Island IO is controlled from Chip TLMM. egpio_enable when set to 0 means the GPIO is used as Island Domain IO. To support this we add a new function 'egpio' which can be used to set the egpio_enable to 0, for any other TLMM controlled functions we set the egpio_enable to 1. Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1637041084-3299-1-git-send-email-rnayak@codeaurora.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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a9cb09b7 |
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04-May-2021 |
Marc Zyngier <maz@kernel.org> |
pinctrl: Bulk conversion to generic_handle_domain_irq() Wherever possible, replace constructs that match either generic_handle_irq(irq_find_mapping()) or generic_handle_irq(irq_linear_revmap()) to a single call to generic_handle_domain_irq(). Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org>
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cf9d052a |
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14-Jan-2021 |
Douglas Anderson <dianders@chromium.org> |
pinctrl: qcom: Don't clear pending interrupts when enabling In Linux, if a driver does disable_irq() and later does enable_irq() on its interrupt, I believe it's expecting these properties: * If an interrupt was pending when the driver disabled then it will still be pending after the driver re-enables. * If an edge-triggered interrupt comes in while an interrupt is disabled it should assert when the interrupt is re-enabled. If you think that the above sounds a lot like the disable_irq() and enable_irq() are supposed to be masking/unmasking the interrupt instead of disabling/enabling it then you've made an astute observation. Specifically when talking about interrupts, "mask" usually means to stop posting interrupts but keep tracking them and "disable" means to fully shut off interrupt detection. It's unfortunate that this is so confusing, but presumably this is all the way it is for historical reasons. Perhaps more confusing than the above is that, even though clients of IRQs themselves don't have a way to request mask/unmask vs. disable/enable calls, IRQ chips themselves can implement both. ...and yet more confusing is that if an IRQ chip implements disable/enable then they will be called when a client driver calls disable_irq() / enable_irq(). It does feel like some of the above could be cleared up. However, without any other core interrupt changes it should be clear that when an IRQ chip gets a request to "disable" an IRQ that it has to treat it like a mask of that IRQ. In any case, after that long interlude you can see that the "unmask and clear" can break things. Maulik tried to fix it so that we no longer did "unmask and clear" in commit 71266d9d3936 ("pinctrl: qcom: Move clearing pending IRQ to .irq_request_resources callback"), but it only handled the PDC case and it had problems (it caused sc7180-trogdor devices to fail to suspend). Let's fix. >From my understanding the source of the phantom interrupt in the were these two things: 1. One that could have been introduced in msm_gpio_irq_set_type() (only for the non-PDC case). 2. Edges could have been detected when a GPIO was muxed away. Fixing case #1 is easy. We can just add a clear in msm_gpio_irq_set_type(). Fixing case #2 is harder. Let's use a concrete example. In sc7180-trogdor.dtsi we configure the uart3 to have two pinctrl states, sleep and default, and mux between the two during runtime PM and system suspend (see geni_se_resources_{on,off}() for more details). The difference between the sleep and default state is that the RX pin is muxed to a GPIO during sleep and muxed to the UART otherwise. As per Qualcomm, when we mux the pin over to the UART function the PDC (or the non-PDC interrupt detection logic) is still watching it / latching edges. These edges don't cause interrupts because the current code masks the interrupt unless we're entering suspend. However, as soon as we enter suspend we unmask the interrupt and it's counted as a wakeup. Let's deal with the problem like this: * When we mux away, we'll mask our interrupt. This isn't necessary in the above case since the client already masked us, but it's a good idea in general. * When we mux back will clear any interrupts and unmask. Fixes: 4b7618fdc7e6 ("pinctrl: qcom: Add irq_enable callback for msm gpio") Fixes: 71266d9d3936 ("pinctrl: qcom: Move clearing pending IRQ to .irq_request_resources callback") Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Maulik Shah <mkshah@codeaurora.org> Tested-by: Maulik Shah <mkshah@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20210114191601.v7.4.I7cf3019783720feb57b958c95c2b684940264cd1@changeid Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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a95881d6 |
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14-Jan-2021 |
Douglas Anderson <dianders@chromium.org> |
pinctrl: qcom: Properly clear "intr_ack_high" interrupts when unmasking In commit 4b7618fdc7e6 ("pinctrl: qcom: Add irq_enable callback for msm gpio") we tried to Ack interrupts during unmask. However, that patch forgot to check "intr_ack_high" so, presumably, it only worked for a certain subset of SoCs. Let's add a small accessor so we don't need to open-code the logic in both places. This was found by code inspection. I don't have any access to the hardware in question nor software that needs the Ack during unmask. Fixes: 4b7618fdc7e6 ("pinctrl: qcom: Add irq_enable callback for msm gpio") Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Maulik Shah <mkshah@codeaurora.org> Tested-by: Maulik Shah <mkshah@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210114191601.v7.3.I32d0f4e174d45363b49ab611a13c3da8f1e87d0f@changeid Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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4079d35f |
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14-Jan-2021 |
Douglas Anderson <dianders@chromium.org> |
pinctrl: qcom: No need to read-modify-write the interrupt status When the Qualcomm pinctrl driver wants to Ack an interrupt, it does a read-modify-write on the interrupt status register. On some SoCs it makes sure that the status bit is 1 to "Ack" and on others it makes sure that the bit is 0 to "Ack". Presumably the first type of interrupt controller is a "write 1 to clear" type register and the second just let you directly set the interrupt status register. As far as I can tell from scanning structure definitions, the interrupt status bit is always in a register by itself. Thus with both types of interrupt controllers it is safe to "Ack" interrupts without doing a read-modify-write. We can do a simple write. It should be noted that if the interrupt status bit _was_ ever in a register with other things (like maybe status bits for other GPIOs): a) For "write 1 clear" type controllers then read-modify-write would be totally wrong because we'd accidentally end up clearing interrupts we weren't looking at. b) For "direct set" type controllers then read-modify-write would also be wrong because someone setting one of the other bits in the register might accidentally clear (or set) our interrupt. I say this simply to show that the current read-modify-write doesn't provide any sort of "future proofing" of the code. In fact (for "write 1 clear" controllers) the new code is slightly more "future proof" since it would allow more than one interrupt status bits to share a register. NOTE: this code fixes no bugs--it simply avoids an extra register read. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Maulik Shah <mkshah@codeaurora.org> Tested-by: Maulik Shah <mkshah@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210114191601.v7.2.I3635de080604e1feda770591c5563bd6e63dd39d@changeid Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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a82e5378 |
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14-Jan-2021 |
Douglas Anderson <dianders@chromium.org> |
pinctrl: qcom: Allow SoCs to specify a GPIO function that's not 0 There's currently a comment in the code saying function 0 is GPIO. Instead of hardcoding it, let's add a member where an SoC can specify it. No known SoCs use a number other than 0, but this just makes the code clearer. NOTE: no SoC code needs to be updated since we can rely on zero-initialization. Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Maulik Shah <mkshah@codeaurora.org> Tested-by: Maulik Shah <mkshah@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210114191601.v7.1.I3ad184e3423d8e479bc3e86f5b393abb1704a1d1@changeid Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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38e86f5c |
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05-Nov-2020 |
John Stultz <john.stultz@linaro.org> |
pinctrl: qcom: Allow pinctrl-msm code to be loadable as a module Tweaks to allow pinctrl-msm code to be loadable as a module. This is needed in order to support having the qcom-scm driver, which pinctrl-msm calls into, configured as a module. This requires that we tweak Kconfigs selecting PINCTRL_MSM to also depend on QCOM_SCM || QCOM_SCM=n so that we match the module setting of QCOM_SCM. Signed-off-by: John Stultz <john.stultz@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Joerg Roedel <joro@8bytes.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <maz@kernel.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Vinod Koul <vkoul@kernel.org> Cc: Kalle Valo <kvalo@codeaurora.org> Cc: Maulik Shah <mkshah@codeaurora.org> Cc: Lina Iyer <ilina@codeaurora.org> Cc: Saravana Kannan <saravanak@google.com> Cc: Todd Kjos <tkjos@google.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: linux-arm-msm@vger.kernel.org Cc: iommu@lists.linux-foundation.org Cc: linux-gpio@vger.kernel.org Link: https://lore.kernel.org/r/20201106042710.55979-2-john.stultz@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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71266d9d |
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05-Nov-2020 |
Maulik Shah <mkshah@codeaurora.org> |
pinctrl: qcom: Move clearing pending IRQ to .irq_request_resources callback When GPIOs that are routed to PDC are used as output they can still latch the IRQ pending at GIC. As a result the spurious IRQ was handled when the client driver change the direction to input to starts using it as IRQ. Currently such erroneous latched IRQ are cleared with .irq_enable callback however if the driver continue to use GPIO as interrupt and invokes disable_irq() followed by enable_irq() then everytime during enable_irq() previously latched interrupt gets cleared. This can make edge IRQs not seen after enable_irq() if they had arrived after the driver has invoked disable_irq() and were pending at GIC. Move clearing erroneous IRQ to .irq_request_resources callback as this is the place where GPIO direction is changed as input and its locked as IRQ. While at this add a missing check to invoke msm_gpio_irq_clear_unmask() from .irq_enable callback only when GPIO is not routed to PDC. Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy") Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Link: https://lore.kernel.org/r/1604561884-10166-1-git-send-email-mkshah@codeaurora.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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dd87bd09 |
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27-Sep-2020 |
Maulik Shah <mkshah@codeaurora.org> |
pinctrl: qcom: Set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flag Set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND flag to enable/unmask the wakeirqs during suspend entry. Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/1601267524-20199-5-git-send-email-mkshah@codeaurora.org
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f41aaca5 |
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27-Sep-2020 |
Maulik Shah <mkshah@codeaurora.org> |
pinctrl: qcom: Use return value from irq_set_wake() call msmgpio irqchip was not using return value of irq_set_irq_wake() callback since previously GIC-v3 irqchip neither had IRQCHIP_SKIP_SET_WAKE flag nor it implemented .irq_set_wake callback. This lead to irq_set_irq_wake() return error -ENXIO. However from 'commit 4110b5cbb014 ("irqchip/gic-v3: Allow interrupt to be configured as wake-up sources")' GIC irqchip has IRQCHIP_SKIP_SET_WAKE flag. Use return value from irq_set_irq_wake() and irq_chip_set_wake_parent() instead of always returning success. Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy") Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/1601267524-20199-3-git-send-email-mkshah@codeaurora.org
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c5f72aeb |
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27-Sep-2020 |
Maulik Shah <mkshah@codeaurora.org> |
pinctrl: qcom: Set IRQCHIP_SET_TYPE_MASKED and IRQCHIP_MASK_ON_SUSPEND flags Both IRQCHIP_SET_TYPE_MASKED and IRQCHIP_MASK_ON_SUSPEND flags are already set for msmgpio's parent PDC irqchip but GPIO interrupts do not get masked during suspend or during setting irq type since genirq checks irqchip flag of msmgpio irqchip which forwards these calls to its parent PDC irqchip. Add irqchip specific flags for msmgpio irqchip to mask non wakeirqs during suspend and mask before setting irq type. Masking before changing type make sures any spurious interrupt is not detected during this operation. Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy") Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/1601267524-20199-2-git-send-email-mkshah@codeaurora.org
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c3c0c2e1 |
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14-Jul-2020 |
Douglas Anderson <dianders@chromium.org> |
pinctrl: qcom: Handle broken/missing PDC dual edge IRQs on sc7180 Depending on how you look at it, you can either say that: a) There is a PDC hardware issue (with the specific IP rev that exists on sc7180) that causes the PDC not to work properly when configured to handle dual edges. b) The dual edge feature of the PDC hardware was only added in later HW revisions and thus isn't in all hardware. Regardless of how you look at it, let's work around the lack of dual edge support by only ever letting our parent see requests for single edge interrupts on affected hardware. NOTE: it's possible that a driver requesting a dual edge interrupt might get several edges coalesced into a single IRQ. For instance if a line starts low and then goes high and low again, the driver that requested the IRQ is not guaranteed to be called twice. However, it is guaranteed that once the driver's interrupt handler starts running its first instruction that any new edges coming in will cause the interrupt to fire again. This is relatively commonplace for dual-edge gpio interrupts (many gpio controllers require software to emulate dual edge with single edge) so client drivers should be setup to handle it. Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy") Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200714080254.v3.1.Ie0d730120b232a86a4eac1e2909bcbec844d1766@changeid Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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0b33c72a |
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13-Jul-2020 |
Lee Jones <lee.jones@linaro.org> |
pinctrl: qcom: pinctrl-msm: Complete 'struct msm_pinctrl' documentation Add missing descriptions for attributes and fix 1 formatting issue. Fixes the following W=1 kernel build warning(s): drivers/pinctrl/qcom/pinctrl-msm.c:75: warning: Function parameter or member 'desc' not described in 'msm_pinctrl' drivers/pinctrl/qcom/pinctrl-msm.c:75: warning: Function parameter or member 'irq_chip' not described in 'msm_pinctrl' drivers/pinctrl/qcom/pinctrl-msm.c:75: warning: Function parameter or member 'intr_target_use_scm' not described in 'msm_pinctrl' drivers/pinctrl/qcom/pinctrl-msm.c:75: warning: Function parameter or member 'soc' not described in 'msm_pinctrl' drivers/pinctrl/qcom/pinctrl-msm.c:75: warning: Function parameter or member 'phys_base' not described in 'msm_pinctrl' Signed-off-by: Lee Jones <lee.jones@linaro.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Andy Gross <agross@kernel.org> Cc: linux-arm-msm@vger.kernel.org Link: https://lore.kernel.org/r/20200713144930.1034632-6-lee.jones@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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13355ca3 |
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03-Jul-2020 |
Jaiganesh Narayanan <njaigane@codeaurora.org> |
pinctrl: qcom: ipq4019: add open drain support [ Brian: adapted from from the Chromium OS kernel used on IPQ4019-based WiFi APs. ] Signed-off-by: Jaiganesh Narayanan <njaigane@codeaurora.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Link: https://lore.kernel.org/r/20200703080646.23233-1-computersforpeace@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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dca4f407 |
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30-Apr-2020 |
Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> |
pinctrl: qcom: Add affinity callbacks to msmgpio IRQ chip Wakeup capable GPIO IRQs routed via PDC are not being migrated when a CPU is hotplugged. Add affinity callbacks to msmgpio IRQ chip to update the affinity of wakeup capable IRQs. Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy") Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> [mkshah: updated commit text and minor code fixes] Signed-off-by: Maulik Shah <mkshah@codeaurora.org> Tested-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1588314617-4556-1-git-send-email-mkshah@codeaurora.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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5da42a3d |
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08-Apr-2020 |
YueHaibing <yuehaibing@huawei.com> |
pinctrl: qcom: Remove duplicated include from pinctrl-msm.c Remove duplicated include. Fixes: 13bec8d49bdf ("pinctrl: qcom: use scm_call to route GPIO irq to Apps") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20200408070504.134847-1-yuehaibing@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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90bcb0c3 |
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13-Apr-2020 |
Ansuel Smith <ansuelsmth@gmail.com> |
pinctrl: qcom: fix wrong write in update_dual_edge Fix a typo in the readl/writel accessor conversion where val is used instead of pol changing the behavior of the original code. Cc: stable@vger.kernel.org Fixes: 6c73698904aa pinctrl: qcom: Introduce readl/writel accessors Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20200414003726.25347-1-ansuelsmth@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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c42f69b4 |
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31-Mar-2020 |
Ansuel Smith <ansuelsmth@gmail.com> |
pinctrl: qcom: fix compilation error pinctrl: qcom: use scm_call to route GPIO irq to Apps has a typo in the patch and introduced a compilation error. Fixes: 13bec8d4 pinctrl: qcom: use scm_call to route GPIO irq to Apps Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Link: https://lore.kernel.org/r/20200331134603.13513-1-ansuelsmth@gmail.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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13bec8d4 |
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27-Mar-2020 |
Ajay Kishore <akisho@codeaurora.org> |
pinctrl: qcom: use scm_call to route GPIO irq to Apps For IPQ806x targets, TZ protects the registers that are used to configure the routing of interrupts to a target processor. To resolve this, this patch uses scm call to route GPIO interrupts to application processor. Also the scm call interface is changed. Signed-off-by: Ajay Kishore <akisho@codeaurora.org> Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Link: https://lore.kernel.org/r/20200327223209.20409-1-ansuelsmth@gmail.com Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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1cada2f3 |
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09-Mar-2020 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: qcom: Assign irq_eoi conditionally The hierarchical parts of MSM pinctrl/GPIO is only used when the device tree has a "wakeup-parent" as a phandle, but the .irq_eoi is anyway assigned leading to semantic problems on elder Qualcomm chipsets. When the drivers/mfd/qcom-pm8xxx.c driver calls chained_irq_exit() that call will in turn call chip->irq_eoi() which is set to irq_chip_eoi_parent() by default on a hierachical IRQ chip, and the parent is pinctrl-msm.c so that will in turn unconditionally call irq_chip_eoi_parent() again, but its parent is invalid so we get the following crash: Unnable to handle kernel NULL pointer dereference at virtual address 00000010 pgd = (ptrval) [00000010] *pgd=00000000 Internal error: Oops: 5 [#1] PREEMPT SMP ARM (...) PC is at irq_chip_eoi_parent+0x4/0x10 LR is at pm8xxx_irq_handler+0x1b4/0x2d8 If we solve this crash by avoiding to call up to irq_chip_eoi_parent(), the machine will hang and get reset by the watchdog, because of semantic issues, probably inside irq_chip. As a solution, just assign the .irq_eoi conditionally if we are actually using a wakeup parent. Cc: David Heidelberg <david@ixit.cz> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Lina Iyer <ilina@codeaurora.org> Cc: Stephen Boyd <swboyd@chromium.org> Cc: stable@vger.kernel.org Fixes: e35a6ae0eb3a ("pinctrl/msm: Setup GPIO chip in hierarchy") Link: https://lore.kernel.org/r/20200306121221.1231296-1-linus.walleij@linaro.org Link: https://lore.kernel.org/r/20200309125207.571840-1-linus.walleij@linaro.org Link: https://lore.kernel.org/r/20200309152604.585112-1-linus.walleij@linaro.org Tested-by: David Heidelberg <david@ixit.cz> Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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3c827873 |
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14-Feb-2020 |
Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> |
pinctrl: Use new GPIO_LINE_DIRECTION Use newly added GPIO defines GPIO_LINE_DIRECTION_IN and GPIO_LINE_DIRECTION_OUT instead of using hard-coded 1 and 0. Main benefit is to make it easier to see which values mean IN and which OUT. As a side effect this helps GPIO framework to change the direction defines to something else if ever needed. Please note that return value from get_direction call on pinctrl-axp209 driver was changed. Previously pinctrl-axp209 might have returned value 2 for direction INPUT. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Reported-by: kbuild test robot <lkp@intel.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Link: https://lore.kernel.org/r/20200214135712.GA14557@localhost.localdomain Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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1d44616e |
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21-Jan-2020 |
Stephen Boyd <swboyd@chromium.org> |
pinctrl: qcom: Don't lock around irq_set_irq_wake() We don't need to hold the local pinctrl lock here to set irq wake on the summary irq line. Doing so only leads to lockdep warnings instead of protecting us from anything. Remove the locking. WARNING: possible circular locking dependency detected 5.4.11 #2 Tainted: G W ------------------------------------------------------ cat/3083 is trying to acquire lock: ffffff81f4fa58c0 (&irq_desc_lock_class){-.-.}, at: __irq_get_desc_lock+0x64/0x94 but task is already holding lock: ffffff81f4880c18 (&pctrl->lock){-.-.}, at: msm_gpio_irq_set_wake+0x48/0x7c which lock already depends on the new lock. the existing dependency chain (in reverse order) is: -> #1 (&pctrl->lock){-.-.}: _raw_spin_lock_irqsave+0x64/0x80 msm_gpio_irq_ack+0x68/0xf4 __irq_do_set_handler+0xe0/0x180 __irq_set_handler+0x60/0x9c irq_domain_set_info+0x90/0xb4 gpiochip_hierarchy_irq_domain_alloc+0x110/0x200 __irq_domain_alloc_irqs+0x130/0x29c irq_create_fwspec_mapping+0x1f0/0x300 irq_create_of_mapping+0x70/0x98 of_irq_get+0xa4/0xd4 spi_drv_probe+0x4c/0xb0 really_probe+0x138/0x3f0 driver_probe_device+0x70/0x140 __device_attach_driver+0x9c/0x110 bus_for_each_drv+0x88/0xd0 __device_attach+0xb0/0x160 device_initial_probe+0x20/0x2c bus_probe_device+0x34/0x94 device_add+0x35c/0x3f0 spi_add_device+0xbc/0x194 of_register_spi_devices+0x2c8/0x408 spi_register_controller+0x57c/0x6fc spi_geni_probe+0x260/0x328 platform_drv_probe+0x90/0xb0 really_probe+0x138/0x3f0 driver_probe_device+0x70/0x140 device_driver_attach+0x4c/0x6c __driver_attach+0xcc/0x154 bus_for_each_dev+0x84/0xcc driver_attach+0x2c/0x38 bus_add_driver+0x108/0x1fc driver_register+0x64/0xf8 __platform_driver_register+0x4c/0x58 spi_geni_driver_init+0x1c/0x24 do_one_initcall+0x1a4/0x3e8 do_initcall_level+0xb4/0xcc do_basic_setup+0x30/0x48 kernel_init_freeable+0x124/0x1a8 kernel_init+0x14/0x100 ret_from_fork+0x10/0x18 -> #0 (&irq_desc_lock_class){-.-.}: __lock_acquire+0xeb4/0x2388 lock_acquire+0x1cc/0x210 _raw_spin_lock_irqsave+0x64/0x80 __irq_get_desc_lock+0x64/0x94 irq_set_irq_wake+0x40/0x144 msm_gpio_irq_set_wake+0x5c/0x7c set_irq_wake_real+0x40/0x5c irq_set_irq_wake+0x70/0x144 cros_ec_rtc_suspend+0x38/0x4c platform_pm_suspend+0x34/0x60 dpm_run_callback+0x64/0xcc __device_suspend+0x310/0x41c dpm_suspend+0xf8/0x298 dpm_suspend_start+0x84/0xb4 suspend_devices_and_enter+0xbc/0x620 pm_suspend+0x210/0x348 state_store+0xb0/0x108 kobj_attr_store+0x14/0x24 sysfs_kf_write+0x4c/0x64 kernfs_fop_write+0x15c/0x1fc __vfs_write+0x54/0x18c vfs_write+0xe4/0x1a4 ksys_write+0x7c/0xe4 __arm64_sys_write+0x20/0x2c el0_svc_common+0xa8/0x160 el0_svc_handler+0x7c/0x98 el0_svc+0x8/0xc other info that might help us debug this: Possible unsafe locking scenario: CPU0 CPU1 ---- ---- lock(&pctrl->lock); lock(&irq_desc_lock_class); lock(&pctrl->lock); lock(&irq_desc_lock_class); *** DEADLOCK *** 7 locks held by cat/3083: #0: ffffff81f06d1420 (sb_writers#7){.+.+}, at: vfs_write+0xd0/0x1a4 #1: ffffff81c8935680 (&of->mutex){+.+.}, at: kernfs_fop_write+0x12c/0x1fc #2: ffffff81f4c322f0 (kn->count#337){.+.+}, at: kernfs_fop_write+0x134/0x1fc #3: ffffffe89a641d60 (system_transition_mutex){+.+.}, at: pm_suspend+0x108/0x348 #4: ffffff81f190e970 (&dev->mutex){....}, at: __device_suspend+0x168/0x41c #5: ffffff81f183d8c0 (lock_class){-.-.}, at: __irq_get_desc_lock+0x64/0x94 #6: ffffff81f4880c18 (&pctrl->lock){-.-.}, at: msm_gpio_irq_set_wake+0x48/0x7c stack backtrace: CPU: 4 PID: 3083 Comm: cat Tainted: G W 5.4.11 #2 Hardware name: Google Cheza (rev3+) (DT) Call trace: dump_backtrace+0x0/0x174 show_stack+0x20/0x2c dump_stack+0xc8/0x124 print_circular_bug+0x2ac/0x2c4 check_noncircular+0x1a0/0x1a8 __lock_acquire+0xeb4/0x2388 lock_acquire+0x1cc/0x210 _raw_spin_lock_irqsave+0x64/0x80 __irq_get_desc_lock+0x64/0x94 irq_set_irq_wake+0x40/0x144 msm_gpio_irq_set_wake+0x5c/0x7c set_irq_wake_real+0x40/0x5c irq_set_irq_wake+0x70/0x144 cros_ec_rtc_suspend+0x38/0x4c platform_pm_suspend+0x34/0x60 dpm_run_callback+0x64/0xcc __device_suspend+0x310/0x41c dpm_suspend+0xf8/0x298 dpm_suspend_start+0x84/0xb4 suspend_devices_and_enter+0xbc/0x620 pm_suspend+0x210/0x348 state_store+0xb0/0x108 kobj_attr_store+0x14/0x24 sysfs_kf_write+0x4c/0x64 kernfs_fop_write+0x15c/0x1fc __vfs_write+0x54/0x18c vfs_write+0xe4/0x1a4 ksys_write+0x7c/0xe4 __arm64_sys_write+0x20/0x2c el0_svc_common+0xa8/0x160 el0_svc_handler+0x7c/0x98 el0_svc+0x8/0xc Fixes: 6aced33f4974 ("pinctrl: msm: drop wake_irqs bitmap") Cc: Douglas Anderson <dianders@chromium.org> Cc: Brian Masney <masneyb@onstation.org> Cc: Lina Iyer <ilina@codeaurora.org> Cc: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20200121180950.36959-1-swboyd@chromium.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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e35a6ae0 |
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15-Nov-2019 |
Lina Iyer <ilina@codeaurora.org> |
pinctrl/msm: Setup GPIO chip in hierarchy Some GPIOs are marked as wakeup capable and are routed to another interrupt controller that is an always-domain and can detect interrupts even when most of the SoC is powered off. The wakeup interrupt controller wakes up the GIC and replays the interrupt at the GIC. Setup the TLMM irqchip in hierarchy with the wakeup interrupt controller and ensure the wakeup GPIOs are handled correctly. Co-developed-by: Maulik Shah <mkshah@codeaurora.org> Signed-off-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1573855915-9841-9-git-send-email-ilina@codeaurora.org ---- Changes in v2: - Address review comments - Fix Co-developed-by tag Changes in v1: - Address minor review comments - Remove redundant call to set irq handler - Move irq_domain_qcom_handle_wakeup() to this patch Changes in RFC v2: - Rebase on top of GPIO hierarchy support in linux-next - Set the chained irq handler for summary line
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#
4b024225 |
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04-Nov-2019 |
YueHaibing <yuehaibing@huawei.com> |
pinctrl: use devm_platform_ioremap_resource() to simplify code devm_platform_ioremap_resource() internally have platform_get_resource() and devm_ioremap_resource() in it. So instead of calling them separately use devm_platform_ioremap_resource() directly. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20191104142654.39256-1-yuehaibing@huawei.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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eb1e8bd6 |
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19-Aug-2019 |
Linus Walleij <linus.walleij@linaro.org> |
gpio: Use callback presence to determine need of valid_mask After we switched the two drivers that have .need_valid_mask set to use the callback for setting up the .valid_mask, we can just use the presence of the .init_valid_mask() callback (or the OF reserved ranges, nota bene) to determine whether to allocate the mask or not and we can drop the .need_valid_mask field altogether. Cc: Benjamin Gaignard <benjamin.gaignard@st.com> Cc: Amelie Delaunay <amelie.delaunay@st.com> Cc: Stephen Boyd <swboyd@chromium.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20190819093058.10863-1-linus.walleij@linaro.org
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c9fc5aff |
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19-Aug-2019 |
Linus Walleij <linus.walleij@linaro.org> |
gpio: Pass mask and size with the init_valid_mask() It is more helpful for drivers to have the affected fields directly available when we use the callback to set up the valid mask. Change this and switch over the only user (MSM) to use the passed parameters. If we do this we can also move the mask out of publicly visible struct fields. Cc: Stephen Boyd <swboyd@chromium.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20190819084904.30027-1-linus.walleij@linaro.or Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
64c4dcbf |
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30-Jul-2019 |
Stephen Boyd <swboyd@chromium.org> |
pinctrl: Remove dev_err() usage after platform_get_irq() We don't need dev_err() messages when platform_get_irq() fails now that platform_get_irq() prints an error message itself when something goes wrong. Let's remove these prints with a simple semantic patch. // <smpl> @@ expression ret; struct platform_device *E; @@ ret = ( platform_get_irq(E, ...) | platform_get_irq_byname(E, ...) ); if ( \( ret < 0 \| ret <= 0 \) ) { ( -if (ret != -EPROBE_DEFER) -{ ... -dev_err(...); -... } | ... -dev_err(...); ) ... } // </smpl> While we're here, remove braces on if statements that only have one statement (manually). Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20190730181557.90391-34-swboyd@chromium.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
720b8ec6 |
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23-Jul-2019 |
Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
pinctrl: msm: Switch to use device_property_count_uXX() Use use device_property_count_uXX() directly, that makes code neater. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20190723192738.68486-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
0ce242ad |
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24-Jul-2019 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: qcom: Pass irqchip when adding gpiochip We need to convert all old gpio irqchips to pass the irqchip setup along when adding the gpio_chip. For chained irqchips this is a pretty straight-forward conversion. Cc: Thierry Reding <treding@nvidia.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Co-developed-by: Lina Iyer <ilina@codeaurora.org> Link: https://lore.kernel.org/r/20190724083828.7496-1-linus.walleij@linaro.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
4b7618fd |
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25-Jun-2019 |
Srinivas Ramana <sramana@codeaurora.org> |
pinctrl: qcom: Add irq_enable callback for msm gpio Introduce the irq_enable callback which will be same as irq_unmask except that it will also clear the status bit before unmask. This will help in clearing any erroneous interrupts that would have got latched when the interrupt is not in use. There may be devices like UART which can use the same gpio line for data rx as well as a wakeup gpio when in suspend. The data that was flowing on the line may latch the interrupt and when we enable the interrupt before going to suspend, this would trigger the unexpected interrupt. This change helps clearing the interrupt so that these unexpected interrupts gets cleared. Signed-off-by: Srinivas Ramana <sramana@codeaurora.org> Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org> Link: https://lore.kernel.org/r/1561472086-23360-1-git-send-email-neeraju@codeaurora.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
4c0efbfb |
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10-Jun-2019 |
Lee Jones <lee.jones@linaro.org> |
pinctrl: msm: Add ability for drivers to supply a reserved GPIO list When booting MSM based platforms with Device Tree or some ACPI implementations, it is possible to provide a list of reserved pins via the 'gpio-reserved-ranges' and 'gpios' properties respectively. However some ACPI tables are not populated with this information, thus it has to come from a knowledgable device driver instead. Here we provide the MSM common driver with additional support to parse this informtion and correctly populate the widely used 'valid_mask'. Signed-off-by: Lee Jones <lee.jones@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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97fb5e8d |
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29-May-2019 |
Thomas Gleixner <tglx@linutronix.de> |
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 284 Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 and only version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 294 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.825281744@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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d1040ea0 |
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10-Dec-2018 |
Arnd Bergmann <arnd@arndb.de> |
pinctrl: msm: mark PM functions as __maybe_unused Without CONFIG_PM_SLEEP, we get annoying warnings about unused functions: drivers/pinctrl/qcom/pinctrl-msm.c:1082:12: error: 'msm_pinctrl_resume' defined but not used [-Werror=unused-function] static int msm_pinctrl_resume(struct device *dev) ^~~~~~~~~~~~~~~~~~ drivers/pinctrl/qcom/pinctrl-msm.c:1075:12: error: 'msm_pinctrl_suspend' defined but not used [-Werror=unused-function] static int msm_pinctrl_suspend(struct device *dev) Mark them as __maybe_unused to shut up the warning and silently drop the functions without having to add ugly #ifdefs. Fixes: 977d057ad346 ("pinctrl: msm: Add sleep pinctrl state transitions") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Evan Green <evgreen@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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977d057a |
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16-Nov-2018 |
Evan Green <evgreen@chromium.org> |
pinctrl: msm: Add sleep pinctrl state transitions Add PM suspend callbacks to the msm core driver that select the sleep and default pinctrl states. Then wire those callbacks up in the sdm845 driver, for those boards that may have GPIO hogs that need to change state during suspend. Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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6f0ec09a |
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05-Oct-2018 |
Ricardo Ribalda <ribalda@kernel.org> |
pinctrl: msm: Use init_valid_mask exported function The current code produces XPU violation if get_direction is called just after the initialization. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Acked-by: Timur Tabi <timur@kernel.org> Tested-by: Jeffrey Hugo <jhugo@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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de0c18a8 |
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01-Oct-2018 |
Stephen Boyd <swboyd@chromium.org> |
pinctrl: msm: Actually use function 0 for gpio selection This code needs to select function #0, which is the first int in the array of functions, not the number 0 which may or may not be the function for "GPIO mode" per the enum mapping. We were getting lucky on SDM845, where this was tested, because the function 0 matched the enum value for "GPIO mode". On other platforms, e.g. MSM8996, the gpio enum value is the last one in the list so this code doesn't work and we see a warning at boot. Fix it by grabbing the first element out of the array of functions. Cc: Doug Anderson <dianders@chromium.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Niklas Cassel <niklas.cassel@linaro.org> Reported-by: Niklas Cassel <niklas.cassel@linaro.org> Fixes: 1de7ddb3a15c ("pinctrl: msm: Mux out gpio function with gpio_request()") Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Tested-by: Niklas Cassel <niklas.cassel@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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a46d5e98 |
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24-Sep-2018 |
Bjorn Andersson <bjorn.andersson@linaro.org> |
pinctrl: qcom: Support dispersed tiles On some new platforms the tiles have been placed too far apart to be covered in a single ioremap. Turn "regs" into an array of base addresses and make the pingroup carry the information about which tile the pin resides in. For existing platforms we map the first entry regs and the existing pingroups will all use tile 0, meaning that there's no functional change. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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6c736989 |
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24-Sep-2018 |
Bjorn Andersson <bjorn.andersson@linaro.org> |
pinctrl: qcom: Introduce readl/writel accessors In preparation for the support for dispersed tiles move all readl and writel calls to helper functions. This will allow us to isolate the added complexity of another indirection. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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1c5fb66a |
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13-Sep-2018 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: Include <linux/gpio/driver.h> nothing else These drivers are GPIO drivers, and the do not need to use the legacy header in <linux/gpio.h>, go directly for <linux/gpio/driver.h> instead. Replace any use of GPIOF_* with 0/1, these flags are for consumers, not drivers. Get rid of a few gpio_to_irq() users that was littering around the place, use local callbacks or avoid using it at all. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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fe273121 |
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16-Aug-2018 |
Stephen Boyd <swboyd@chromium.org> |
pinctrl: msm: Configure interrupts as input and gpio mode When requesting a gpio as an interrupt, we should make sure to mux the pin as the GPIO function and configure it to be an input so that various functions or output signals don't affect the interrupt state of the pin. So far, we've relied on pinmux configurations in DT to handle this, but let's explicitly configure this in the code so that DT implementers don't have to get this part right. Cc: Doug Anderson <dianders@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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1de7ddb3 |
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16-Aug-2018 |
Stephen Boyd <swboyd@chromium.org> |
pinctrl: msm: Mux out gpio function with gpio_request() We rely on devices to use pinmuxing configurations in DT to select the GPIO function (function 0) if they're going to use the gpio in GPIO mode. Let's simplify things for driver authors by implementing gpio_request_enable() for this pinctrl driver to mux out the GPIO function when the gpio is use from gpiolib. Cc: Doug Anderson <dianders@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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b55326dc |
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16-Aug-2018 |
Stephen Boyd <swboyd@chromium.org> |
pinctrl: msm: Really mask level interrupts to prevent latching The interrupt controller hardware in this pin controller has two status enable bits. The first "normal" status enable bit enables or disables the summary interrupt line being raised when a gpio interrupt triggers and the "raw" status enable bit allows or prevents the hardware from latching an interrupt into the status register for a gpio interrupt. Currently we just toggle the "normal" status enable bit in the mask and unmask ops so that the summary irq interrupt going to the CPU's interrupt controller doesn't trigger for the masked gpio interrupt. For a level triggered interrupt, the flow would be as follows: the pin controller sees the interrupt, latches the status into the status register, raises the summary irq to the CPU, summary irq handler runs and calls handle_level_irq(), handle_level_irq() masks and acks the gpio interrupt, the interrupt handler runs, and finally unmask the interrupt. When the interrupt handler completes, we expect that the interrupt line level will go back to the deasserted state so the genirq code can unmask the interrupt without it triggering again. If we only mask the interrupt by clearing the "normal" status enable bit then we'll ack the interrupt but it will continue to show up as pending in the status register because the raw status bit is enabled, the hardware hasn't deasserted the line, and thus the asserted state latches into the status register again. When the hardware deasserts the interrupt the pin controller still thinks there is a pending unserviced level interrupt because it latched it earlier. This behavior causes software to see an extra interrupt for level type interrupts each time the interrupt is handled. Let's fix this by clearing the raw status enable bit for level type interrupts so that the hardware stops latching the status of the interrupt after we ack it. We don't do this for edge type interrupts because it seems that toggling the raw status enable bit for edge type interrupts causes spurious edge interrupts. Signed-off-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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05e0c828 |
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02-Jul-2018 |
Douglas Anderson <dianders@chromium.org> |
pinctrl: msm: Fix msm_config_group_get() to be compliant If you do this on an sdm845 board: cat /sys/kernel/debug/pinctrl/3400000.pinctrl/pinconf-groups ...it looks like nonsense. For every pin you see listed: input bias bus hold, input bias disabled, input bias pull down, input bias pull up That's because msm_config_group_get() isn't complying with the rules that pinconf_generic_dump_one() expects. Specifically for boolean parameters (anything with a "struct pin_config_item" where has_arg is false) the function expects that the function should return its value not through the "config" parameter but should return "0" if the value is set and "-EINVAL" if the value isn't set. Let's fix this. From a quick sample of other pinctrl drivers, it appears to be tradition to also return 1 through the config parameter for these boolean parameters when they exist. I'm not one to knock tradition, so I'll follow tradition and return 1 in these cases. While I'm at it, I'll also continue searching for four leaf clovers, kocking on wood three times, and trying not to break mirrors. Fixes: f365be092572 ("pinctrl: Add Qualcomm TLMM driver") Signed-off-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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a86caa9b |
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21-May-2018 |
Christian Lamparter <chunkeey@gmail.com> |
pinctrl: msm: fix gpio-hog related boot issues Sven Eckelmann reported an issue with the current IPQ4019 pinctrl. Setting up any gpio-hog in the device-tree for his device would "kill the bootup completely": | [ 0.477838] msm_serial 78af000.serial: could not find pctldev for node /soc/pinctrl@1000000/serial_pinmux, deferring probe | [ 0.499828] spi_qup 78b5000.spi: could not find pctldev for node /soc/pinctrl@1000000/spi_0_pinmux, deferring probe | [ 1.298883] requesting hog GPIO enable USB2 power (chip 1000000.pinctrl, offset 58) failed, -517 | [ 1.299609] gpiochip_add_data: GPIOs 0..99 (1000000.pinctrl) failed to register | [ 1.308589] ipq4019-pinctrl 1000000.pinctrl: Failed register gpiochip | [ 1.316586] msm_serial 78af000.serial: could not find pctldev for node /soc/pinctrl@1000000/serial_pinmux, deferring probe | [ 1.322415] spi_qup 78b5000.spi: could not find pctldev for node /soc/pinctrl@1000000/spi_0_pinmux, deferri This was also verified on a RT-AC58U (IPQ4018) which would no longer boot, if a gpio-hog was specified. (Tried forcing the USB LED PIN (GPIO0) to high.). The problem is that Pinctrl+GPIO registration is currently peformed in the following order in pinctrl-msm.c: 1. pinctrl_register() 2. gpiochip_add() 3. gpiochip_add_pin_range() The actual error code -517 == -EPROBE_DEFER is coming from pinctrl_get_device_gpio_range(), which is called through: gpiochip_add of_gpiochip_add of_gpiochip_scan_gpios gpiod_hog gpiochip_request_own_desc __gpiod_request chip->request gpiochip_generic_request pinctrl_gpio_request pinctrl_get_device_gpio_range pinctrl_get_device_gpio_range() is unable to find any valid pin ranges, since nothing has been added to the pinctrldev_list yet. so the range can't be found, and the operation fails with -EPROBE_DEFER. This patch fixes the issue by adding the "gpio-ranges" property to the pinctrl device node of all upstream Qcom SoC. The pin ranges are then added by the gpio core. In order to remain compatible with older, existing DTs (and ACPI) a check for the "gpio-ranges" property has been added to msm_gpio_init(). This prevents the driver of adding the same entry to the pinctrldev_list twice. Reported-by: Sven Eckelmann <sven.eckelmann@openmesh.com> Tested-by: Sven Eckelmann <sven.eckelmann@openmesh.com> [ipq4019] Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Christian Lamparter <chunkeey@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
59a18c24 |
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07-May-2018 |
Stephen Boyd <swboyd@chromium.org> |
pinctrl: qcom: Print high/low status of gpios in debugfs I was debugging some gpio issues and I thought that the output of gpio debugfs was telling me the high or low level of the gpios with a '1' or a '0'. We saw a line like this though: gpio93 : in 4 2mA pull down and I started to think that there may be a gas leak in the building because '4' doesn't mean high or low, and other pins said '0' or '1'. It turns out, '4' is the function selection for the pinmux of the gpio and not the value on the pin. Reading code helps decipher what debugfs is actually saying. Add support to read the input or output pin depending on how the pin is configured so we can easily see the high or low value of the pin in debugfs. Now the output looks like gpio93 : in low func4 2mA pull down which clearly shows that the pin is an input, low, with function 4 and a 2mA drive strength plus a pull down. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Alexandru M Stan <amstan@chromium.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
53e73a28 |
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04-May-2018 |
Clément Péron <peron.clem@gmail.com> |
pinctrl: qcom: fix wrong pull status display for no_keeper SoC DebugFS strings about pin pull status for no_keeper SoC are wrong Fix this by adding a different string array for no_keeper SoC Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
f265e8b9 |
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25-Apr-2018 |
Timur Tabi <timur@codeaurora.org> |
pinctrl: qcom: remove static globals to allow multiple TLMMs Two data structures are declared as static globals but are intended to be per-TLMM. Move them into the msm_pinctrl structure and initialize them at runtime. Signed-off-by: Timur Tabi <timur@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
691bf5d5 |
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23-Mar-2018 |
Stephen Boyd <sboyd@codeaurora.org> |
pinctrl: qcom: Don't allow protected pins to be requested Some qcom platforms make some GPIOs or pins unavailable for use by non-secure operating systems, and thus reading or writing the registers for those pins will cause access control issues and reset the device. With a DT/ACPI property to describe the set of pins that are available for use, parse the available pins and set the irq valid bits for gpiolib to know what to consider 'valid'. This should avoid any issues with gpiolib. Furthermore, implement the pinmux_ops::request function so that pinmux can also make sure to not use pins that are unavailable. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Tested-by: Timur Tabi <timur@codeaurora.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
a7aa75a2 |
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28-Jan-2018 |
Bjorn Andersson <bjorn.andersson@linaro.org> |
pinctrl: msm: Use dynamic GPIO numbering The base of the TLMM gpiochip should not be statically defined as 0, fix this to not artificially restrict the existence of multiple pinctrl-msm devices. Fixes: f365be092572 ("pinctrl: Add Qualcomm TLMM driver") Reported-by: Timur Tabi <timur@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
203f4b06 |
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27-Dec-2017 |
Markus Elfring <elfring@users.sourceforge.net> |
pinctrl: msm: Delete an error message for a failed memory allocation in msm_pinctrl_probe() Omit an extra message for a memory allocation failure in this function. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
bd8ed930 |
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28-Dec-2017 |
Linus Walleij <linus.walleij@linaro.org> |
Revert "pinctrl: qcom: disable GPIO groups with no pins" This reverts commit 93ebe8636bb0d95e2e711f2a53abbb72a9d9cf8d. After discussion and review of the v11 patchset, a new approach was found so that this patch is not needed. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
93ebe863 |
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20-Dec-2017 |
Timur Tabi <timur@codeaurora.org> |
pinctrl: qcom: disable GPIO groups with no pins pinctrl-msm only accepts an array of GPIOs from 0 to n-1, and it expects each group to support have only one pin (npins == 1). We can support "sparse" GPIO maps if we allow for some groups to have zero pins (npins == 0). These pins are "hidden" from the rest of the driver and gpiolib. Access to unavailable GPIOs is blocked via a request callback. If the requested GPIO is unavailable, -EACCES is returned, which prevents further access to that GPIO. Signed-off-by: Timur Tabi <timur@codeaurora.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
f0fbe7bc |
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07-Nov-2017 |
Thierry Reding <treding@nvidia.com> |
gpio: Move irqdomain into struct gpio_irq_chip In order to consolidate the multiple ways to associate an IRQ chip with a GPIO chip, move more fields into the new struct gpio_irq_chip. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
12cb90ba |
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11-Jul-2017 |
Gustavo A. R. Silva <garsilva@embeddedor.com> |
pinctrl: qcom: msm: constify gpio_chip structure This structure is only used to copy into other structure, so declare it as const. This issue was detected using Coccinelle and the following semantic patch: @r disable optional_qualifier@ identifier i; position p; @@ static struct gpio_chip i@p = { ... }; @ok@ identifier r.i; expression e; position p; @@ e = i@p; @bad@ position p != {r.p,ok.p}; identifier r.i; struct gpio_chip e; @@ e@i@p @depends on !bad disable optional_qualifier@ identifier r.i; @@ static +const struct gpio_chip i = { ... }; In the following log you can see a significant difference in the code size and data segment, hence in the dec segment. This log is the output of the size command, before and after the code change: before: text data bss dec hex filename 13129 2808 192 16129 3f01 drivers/pinctrl/qcom/pinctrl-msm.o after: text data bss dec hex filename 12839 2720 192 15751 3d87 drivers/pinctrl/qcom/pinctrl-msm.o Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
83cf5fae |
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14-Jul-2017 |
Ram Chandra Jangir <rjangir@codeaurora.org> |
pinctrl: msm: add support to configure ipq40xx GPIO_PULL bits GPIO_PULL bits configurations in TLMM_GPIO_CFG register differs for IPQ40xx from rest of the other qcom SoCs. As it does not support the keeper state and therefore can't support bias-bus-hold property. This patch adds a pull_no_keeper setting which configures the msm_gpio_pull bits for ipq40xx. This is required to fix the proper configurations of gpio-pull bits for nand pins mux. IPQ40xx SoC: 2'b10: Internal pull up enable. 2'b11: Unsupport For other SoC's: 2'b10: Keeper 2'b11: Pull-Up Note: Due to pull_no_keeper length, all kerneldoc entries in the msm_pinctrl_soc_data struct had to be realigned. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org> Signed-off-by: Christian Lamparter <chunkeey@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
a6566710 |
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14-Mar-2017 |
Bjorn Andersson <bjorn.andersson@linaro.org> |
pinctrl: qcom: Don't clear status bit on irq_unmask Clearing the status bit on irq_unmask will discard any pending interrupt that did arrive after the irq_ack, i.e. while the IRQ handler function was executing. Fixes: f365be092572 ("pinctrl: Add Qualcomm TLMM driver") Cc: stable@vger.kernel.org Cc: Stephen Boyd <sboyd@codeaurora.org> Reported-by: Timur Tabi <timur@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
8e515337 |
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10-Feb-2017 |
Timur Tabi <timur@codeaurora.org> |
pinctrl: qcom: add get_direction function The get_direction callback function allows gpiolib to know the current direction (input vs output) for a given GPIO. This is particularly useful on ACPI systems, where the GPIOs are configured only by firmware (typically UEFI), so the only way to know the initial values to query the hardware directly. Without this function, gpiolib thinks that all GPIOs are configured for input. Signed-off-by: Timur Tabi <timur@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
47b03ca9 |
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20-Jan-2017 |
Julia Cartwright <julia@ni.com> |
pinctrl: qcom: Use raw spinlock variants The MSM pinctrl driver currently implements an irq_chip for handling GPIO interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. On real-time kernels, this fixes an OOPs which looks like the following, as reported by Brian Wrenn: kernel BUG at kernel/locking/rtmutex.c:1014! Internal error: Oops - BUG: 0 [#1] PREEMPT SMP Modules linked in: spidev_irq(O) smsc75xx wcn36xx [last unloaded: spidev] CPU: 0 PID: 1163 Comm: irq/144-mmc0 Tainted: G W O 4.4.9-linaro-lt-qcom #1 PC is at rt_spin_lock_slowlock+0x80/0x2d8 LR is at rt_spin_lock_slowlock+0x68/0x2d8 [..] Call trace: rt_spin_lock_slowlock rt_spin_lock msm_gpio_irq_ack handle_edge_irq generic_handle_irq msm_gpio_irq_handler generic_handle_irq __handle_domain_irq gic_handle_irq Reported-by: Brian Wrenn <dcbrianw@gmail.com> Tested-by: Brian Wrenn <dcbrianw@gmail.com> Signed-off-by: Julia Cartwright <julia@ni.com> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
6bcf3f63 |
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12-Sep-2016 |
John Crispin <john@phrozen.org> |
pinctrl: qcom: fix masking of pinmux functions The following commit introduced a regression by not properly masking the calculated value. Fixes: 47a01ee9a6c3 ("pinctrl: qcom: Clear all function selection bits") Signed-off-by: John Crispin <john@phrozen.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
47a01ee9 |
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25-Jun-2016 |
Stephen Boyd <stephen.boyd@linaro.org> |
pinctrl: qcom: Clear all function selection bits The function selection bitfield is not always 3 bits wide. Sometimes it is 4 bits wide. Let's use the npins struct member to determine how many bits wide the function selection bitfield is so we clear the correct amount of bits in the register while remuxing the pins. Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
fe0267f4 |
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24-Feb-2016 |
Laxman Dewangan <ldewangan@nvidia.com> |
pinctrl: msm: Use devm_pinctrl_register() for pinctrl registration Use devm_pinctrl_register() for pin control registration and clean the error path. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Lee Jones <lee.jones@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
d32f7fd3 |
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31-Mar-2016 |
Irina Tirdea <irina.tirdea@intel.com> |
pinctrl: Rename pinctrl_utils_dt_free_map to pinctrl_utils_free_map Rename pinctrl_utils_dt_free_map to pinctrl_utils_free_map, since it does not depend on device tree despite the current name. This will enforce a consistent naming in pinctr-utils.c and will make it clear it can be called from outside device tree (e.g. from ACPI handling code). Signed-off-by: Irina Tirdea <irina.tirdea@intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
fded3f40 |
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08-Dec-2015 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: msm: use gpiochip data pointer This makes the driver use the data pointer added to the gpio_chip to store a pointer to the state container instead of relying on container_of(). Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Björn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
58383c78 |
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04-Nov-2015 |
Linus Walleij <linus.walleij@linaro.org> |
gpio: change member .dev to .parent The name .dev in a struct is normally reserved for a struct device that is let us say a superclass to the thing described by the struct. struct gpio_chip stands out by confusingly using a struct device *dev to point to the parent device (such as a platform_device) that represents the hardware. As we want to give gpio_chip:s real devices, this is not working. We need to rename this member to parent. This was done by two coccinelle scripts, I guess it is possible to combine them into one, but I don't know such stuff. They look like this: @@ struct gpio_chip *var; @@ -var->dev +var->parent and: @@ struct gpio_chip var; @@ -var.dev +var.parent and: @@ struct bgpio_chip *var; @@ -var->gc.dev +var->gc.parent Plus a few instances of bgpio that I couldn't figure out how to teach Coccinelle to rewrite. This patch hits all over the place, but I *strongly* prefer this solution to any piecemal approaches that just exercise patch mechanics all over the place. It mainly hits drivers/gpio and drivers/pinctrl which is my own backyard anyway. Cc: Haavard Skinnemoen <hskinnemoen@gmail.com> Cc: Rafał Miłecki <zajec5@gmail.com> Cc: Richard Purdie <rpurdie@rpsys.net> Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com> Cc: Alek Du <alek.du@intel.com> Cc: Jaroslav Kysela <perex@perex.cz> Cc: Takashi Iwai <tiwai@suse.com> Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Jiri Kosina <jkosina@suse.cz> Acked-by: Hans-Christian Egtvedt <egtvedt@samfundet.no> Acked-by: Jacek Anaszewski <j.anaszewski@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
98c85d58 |
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11-Oct-2015 |
Jonas Gorski <jogo@openwrt.org> |
pinctrl: replace trivial implementations of gpio_chip request/free Replace all trivial request/free callbacks that do nothing but call into pinctrl code with the generic versions. Signed-off-by: Jonas Gorski <jogo@openwrt.org> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Eric Anholt <eric@anholt.net> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Andrew Bresticker <abrestic@chromium.org> Acked-by: Baruch Siach <baruch@tkos.co.il> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Lee Jones <lee@kernel.org> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
bd0b9ac4 |
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14-Sep-2015 |
Thomas Gleixner <tglx@linutronix.de> |
genirq: Remove irq argument from irq flow handlers Most interrupt flow handlers do not use the irq argument. Those few which use it can retrieve the irq number from the irq descriptor. Remove the argument. Search and replace was done with coccinelle and some extra helper scripts around it. Thanks to Julia for her help! Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Jiang Liu <jiang.liu@linux.intel.com>
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#
d1800c23 |
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12-Jul-2015 |
Thomas Gleixner <tglx@linutronix.de> |
pinctrl/qcom/msm: Prepare msm_gpio_irq_handler for irq argument removal The irq argument of most interrupt flow handlers is unused or merily used instead of a local variable. The handlers which need the irq argument can retrieve the irq number from the irq descriptor. Search and update was done with coccinelle and the invaluable help of Julia Lawall. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Julia Lawall <Julia.Lawall@lip6.fr> Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org
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#
5663bb27 |
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03-Jun-2015 |
Jiang Liu <jiang.liu@linux.intel.com> |
pinctrl: Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc Use irq_desc_get_xxx() to avoid redundant lookup of irq_desc while we already have a pointer to corresponding irq_desc. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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#
34c0ad84 |
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23-Jun-2015 |
Thomas Gleixner <tglx@linutronix.de> |
pinctrl/qcom: Use irq_set_handler_locked() Use irq_set_handler_locked() as it avoids a redundant lookup of the irq descriptor. Search and replacement was done with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: Julia Lawall <julia.lawall@lip6.fr> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org
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#
ad644987 |
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06-Jul-2015 |
Stephen Boyd <sboyd@codeaurora.org> |
pinctrl: qcom: Hook pm_power_down for shutdown support Assign pm_power_off() if we have the PS_HOLD functionality so that we can properly shutdown the SoC. Otherwise, shutdown won't do anything besides put the CPU into a tight loop. Unfortunately, we have to use a singleton here because pm_power_off() doesn't take any arguments. Fortunately there's only one instance of the pinctrl device on a running system so this isn't a problem. Cc: Pramod Gurav <pramod.gurav@smartplayin.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
323de9ef |
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08-Jun-2015 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
pinctrl: make pinctrl_register() return proper error code Currently, pinctrl_register() just returns NULL on error, so the callers can not know the exact reason of the failure. Some of the pinctrl drivers return -EINVAL, some -ENODEV, and some -ENOMEM on error of pinctrl_register(), although the error code might be different from the real cause of the error. This commit reworks pinctrl_register() to return the appropriate error code and modifies all of the pinctrl drivers to use IS_ERR() for the error checking and PTR_ERR() for getting the error code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Lee Jones <lee@kernel.org> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Ray Jui <rjui@broadcom.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com> Acked-by: Wei Chen <Wei.Chen@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
407f5e39 |
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03-Mar-2015 |
Stanimir Varbanov <svarbanov@mm-sol.com> |
pinctrl: qcom: handle input-enable pinconf property This enables support of 'input-enable' pinconf generic property in the pinctrl driver. Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
38d756af |
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03-Mar-2015 |
Stanimir Varbanov <svarbanov@mm-sol.com> |
pinctrl: qcom: enable generic pinconf This makes the pinctrl driver to use the generic pinconf interface. Mainly it gives us a way to use debugfs to dump group configurations. Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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#
fc0d8fda |
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29-Jan-2015 |
Stanimir Varbanov <svarbanov@mm-sol.com> |
pinctrl: qcom: delete pin_config_get/set pinconf operations The .pin_config_get/set operation are not supported in qcom pinctrl driver. As the pinconf core is smart enough it doesn't complain about that. Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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bcd53f85 |
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19-Jan-2015 |
Stephen Boyd <sboyd@codeaurora.org> |
pinctrl: qcom: Don't iterate past end of function array Timur reports that this code crashes if nfunctions is 0. Fix the loop iteration to only consider valid elements of the functions array. Reported-by: Timur Tabi <timur@codeaurora.org> Cc: Pramod Gurav <pramod.gurav@smartplayin.com> Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Cc: Ivan T. Ivanov <iivanov@mm-sol.com> Cc: Andy Gross <agross@codeaurora.org> Fixes: 327455817a92 "pinctrl: qcom: Add support for reset for apq8064" Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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cf1fc187 |
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23-Sep-2014 |
Josh Cartwright <joshc@codeaurora.org> |
pinctrl: qcom: use restart_notifier mechanism for ps_hold By converting to the restart_notifier mechanism for restart, we allow for other mechanisms, like the watchdog, to be used for restart in the case where PS_HOLD has failed to reset the chip. Since this mechanism may be one of several mechanisms registered, change the post-ps_hold write timeout to be a more reasonable 1 second instead of 10 seconds. Choose priority 128, as according to documentation, this mechanism "is sufficient to restart the entire system". Tested-by: Pramod Gurav <pramod.gurav@smartplayin.com> Signed-off-by: Josh Cartwright <joshc@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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2fcea6ce |
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16-Sep-2014 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: remove remaining users of gpiochip_remove() retval Some drivers accidentally still use the return value from gpiochip_remove(). Get rid of them so we can simplify this function and get rid of the return value. Cc: Abdoulaye Berthe <berthe.ab@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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f712c554 |
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03-Sep-2014 |
Georgi Djakov <gdjakov@mm-sol.com> |
pinctrl: qcom: Make the target processor value configurable Currently the value used to specify that interrupts from the gpio should be routed to the application processor is hardcoded for all Qualcomm SoCs. But the new APQ8084 SoC uses a different value. To resolve this, we make this value configurable for each SoC. For all existing SoCs we continue to use the current value, and only for APQ8084 we use the new value. Suggested-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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03e9f0ca |
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03-Sep-2014 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: clean up after enable refactoring commit 2243a87d90b42eb38bc281957df3e57c712b5e56 "pinctrl: avoid duplicated calling enable_pinmux_setting for a pin" removed the .disable callback from the struct pinmux_ops, making the .enable() callback the only remaining callback. However .enable() is a bad name as it seems to imply that a muxing can also be disabled. Rename the callback to .set_mux() and also take this opportunity to clean out any remaining mentions of .disable() from the documentation. Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Acked-by: Fan Wu <fwu@marvell.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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32745581 |
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29-Aug-2014 |
Pramod Gurav <pramod.gurav@smartplayin.com> |
pinctrl: qcom: Add support for reset for apq8064 This patch adds support for reset functions to reboot the boards with soc apq8064. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: "Ivan T. Ivanov" <iivanov@mm-sol.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Andy Gross <agross@codeaurora.org> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Pramod Gurav <pramod.gurav@smartplayin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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c6e927a2 |
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29-Aug-2014 |
Pramod Gurav <pramod.gurav@smartplayin.com> |
pinctrl: qcom: remove gpiochip in failure cases This patch releases gpiochip related resources by calling gpiochip_remove when either of gpiochip_add_pin_range and gpiochip_irqchip_add fails. CC: Linus Walleij <linus.walleij@linaro.org> CC: "Ivan T. Ivanov" <iivanov@mm-sol.com> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Pramod Gurav <pramod.gurav@smartplayin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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1c349551 |
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17-Jul-2014 |
Andrey Utkin <andrey.krieger.utkin@gmail.com> |
pinctrl: msm: drop negativity check on unsigned value [linux-3.16-rc5/drivers/pinctrl/pinctrl-msm.c:145]: (style) Checking if unsigned variable 'mux_bit' is less than zero. if (WARN_ON(g->mux_bit < 0)) return -EINVAL; Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=80491 Reported-by: David Binderman <dcb314@hotmail.com> Signed-off-by: Andrey Utkin <andrey.krieger.utkin@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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69b78b8d |
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09-Jul-2014 |
Linus Walleij <linus.walleij@linaro.org> |
pinctrl: msm: move all qualcomm drivers to subdir We have four Qualcomm-related pin control drivers, and now there are drivers coming in for the PMICs on these systems, so let's create a qcom subdirectory to hold all the Qualcomm stuff. Acked-by: Ivan T. Ivanov <iivanov@mm-sol.com> Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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