1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013, Sony Mobile Communications AB. 4 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 5 */ 6 7#include <linux/delay.h> 8#include <linux/err.h> 9#include <linux/gpio/driver.h> 10#include <linux/interrupt.h> 11#include <linux/io.h> 12#include <linux/log2.h> 13#include <linux/module.h> 14#include <linux/of.h> 15#include <linux/platform_device.h> 16#include <linux/pm.h> 17#include <linux/firmware/qcom/qcom_scm.h> 18#include <linux/reboot.h> 19#include <linux/seq_file.h> 20#include <linux/slab.h> 21#include <linux/spinlock.h> 22 23#include <linux/pinctrl/machine.h> 24#include <linux/pinctrl/pinconf-generic.h> 25#include <linux/pinctrl/pinconf.h> 26#include <linux/pinctrl/pinmux.h> 27 28#include <linux/soc/qcom/irq.h> 29 30#include "../core.h" 31#include "../pinconf.h" 32#include "../pinctrl-utils.h" 33 34#include "pinctrl-msm.h" 35 36#define MAX_NR_GPIO 300 37#define MAX_NR_TILES 4 38#define PS_HOLD_OFFSET 0x820 39 40/** 41 * struct msm_pinctrl - state for a pinctrl-msm device 42 * @dev: device handle. 43 * @pctrl: pinctrl handle. 44 * @chip: gpiochip handle. 45 * @desc: pin controller descriptor 46 * @restart_nb: restart notifier block. 47 * @irq: parent irq for the TLMM irq_chip. 48 * @intr_target_use_scm: route irq to application cpu using scm calls 49 * @lock: Spinlock to protect register resources as well 50 * as msm_pinctrl data structures. 51 * @enabled_irqs: Bitmap of currently enabled irqs. 52 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge 53 * detection. 54 * @skip_wake_irqs: Skip IRQs that are handled by wakeup interrupt controller 55 * @disabled_for_mux: These IRQs were disabled because we muxed away. 56 * @ever_gpio: This bit is set the first time we mux a pin to gpio_func. 57 * @soc: Reference to soc_data of platform specific data. 58 * @regs: Base addresses for the TLMM tiles. 59 * @phys_base: Physical base address 60 */ 61struct msm_pinctrl { 62 struct device *dev; 63 struct pinctrl_dev *pctrl; 64 struct gpio_chip chip; 65 struct pinctrl_desc desc; 66 struct notifier_block restart_nb; 67 68 int irq; 69 70 bool intr_target_use_scm; 71 72 raw_spinlock_t lock; 73 74 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); 75 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); 76 DECLARE_BITMAP(skip_wake_irqs, MAX_NR_GPIO); 77 DECLARE_BITMAP(disabled_for_mux, MAX_NR_GPIO); 78 DECLARE_BITMAP(ever_gpio, MAX_NR_GPIO); 79 80 const struct msm_pinctrl_soc_data *soc; 81 void __iomem *regs[MAX_NR_TILES]; 82 u32 phys_base[MAX_NR_TILES]; 83}; 84 85#define MSM_ACCESSOR(name) \ 86static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \ 87 const struct msm_pingroup *g) \ 88{ \ 89 return readl(pctrl->regs[g->tile] + g->name##_reg); \ 90} \ 91static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \ 92 const struct msm_pingroup *g) \ 93{ \ 94 writel(val, pctrl->regs[g->tile] + g->name##_reg); \ 95} 96 97MSM_ACCESSOR(ctl) 98MSM_ACCESSOR(io) 99MSM_ACCESSOR(intr_cfg) 100MSM_ACCESSOR(intr_status) 101MSM_ACCESSOR(intr_target) 102 103static void msm_ack_intr_status(struct msm_pinctrl *pctrl, 104 const struct msm_pingroup *g) 105{ 106 u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0; 107 108 msm_writel_intr_status(val, pctrl, g); 109} 110 111static int msm_get_groups_count(struct pinctrl_dev *pctldev) 112{ 113 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 114 115 return pctrl->soc->ngroups; 116} 117 118static const char *msm_get_group_name(struct pinctrl_dev *pctldev, 119 unsigned group) 120{ 121 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 122 123 return pctrl->soc->groups[group].grp.name; 124} 125 126static int msm_get_group_pins(struct pinctrl_dev *pctldev, 127 unsigned group, 128 const unsigned **pins, 129 unsigned *num_pins) 130{ 131 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 132 133 *pins = pctrl->soc->groups[group].grp.pins; 134 *num_pins = pctrl->soc->groups[group].grp.npins; 135 return 0; 136} 137 138static const struct pinctrl_ops msm_pinctrl_ops = { 139 .get_groups_count = msm_get_groups_count, 140 .get_group_name = msm_get_group_name, 141 .get_group_pins = msm_get_group_pins, 142 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 143 .dt_free_map = pinctrl_utils_free_map, 144}; 145 146static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset) 147{ 148 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 149 struct gpio_chip *chip = &pctrl->chip; 150 151 return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL; 152} 153 154static int msm_get_functions_count(struct pinctrl_dev *pctldev) 155{ 156 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 157 158 return pctrl->soc->nfunctions; 159} 160 161static const char *msm_get_function_name(struct pinctrl_dev *pctldev, 162 unsigned function) 163{ 164 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 165 166 return pctrl->soc->functions[function].name; 167} 168 169static int msm_get_function_groups(struct pinctrl_dev *pctldev, 170 unsigned function, 171 const char * const **groups, 172 unsigned * const num_groups) 173{ 174 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 175 176 *groups = pctrl->soc->functions[function].groups; 177 *num_groups = pctrl->soc->functions[function].ngroups; 178 return 0; 179} 180 181static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev, 182 unsigned function, 183 unsigned group) 184{ 185 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 186 struct gpio_chip *gc = &pctrl->chip; 187 unsigned int irq = irq_find_mapping(gc->irq.domain, group); 188 struct irq_data *d = irq_get_irq_data(irq); 189 unsigned int gpio_func = pctrl->soc->gpio_func; 190 unsigned int egpio_func = pctrl->soc->egpio_func; 191 const struct msm_pingroup *g; 192 unsigned long flags; 193 u32 val, mask; 194 int i; 195 196 g = &pctrl->soc->groups[group]; 197 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit); 198 199 for (i = 0; i < g->nfuncs; i++) { 200 if (g->funcs[i] == function) 201 break; 202 } 203 204 if (WARN_ON(i == g->nfuncs)) 205 return -EINVAL; 206 207 /* 208 * If an GPIO interrupt is setup on this pin then we need special 209 * handling. Specifically interrupt detection logic will still see 210 * the pin twiddle even when we're muxed away. 211 * 212 * When we see a pin with an interrupt setup on it then we'll disable 213 * (mask) interrupts on it when we mux away until we mux back. Note 214 * that disable_irq() refcounts and interrupts are disabled as long as 215 * at least one disable_irq() has been called. 216 */ 217 if (d && i != gpio_func && 218 !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux)) 219 disable_irq(irq); 220 221 raw_spin_lock_irqsave(&pctrl->lock, flags); 222 223 val = msm_readl_ctl(pctrl, g); 224 225 /* 226 * If this is the first time muxing to GPIO and the direction is 227 * output, make sure that we're not going to be glitching the pin 228 * by reading the current state of the pin and setting it as the 229 * output. 230 */ 231 if (i == gpio_func && (val & BIT(g->oe_bit)) && 232 !test_and_set_bit(group, pctrl->ever_gpio)) { 233 u32 io_val = msm_readl_io(pctrl, g); 234 235 if (io_val & BIT(g->in_bit)) { 236 if (!(io_val & BIT(g->out_bit))) 237 msm_writel_io(io_val | BIT(g->out_bit), pctrl, g); 238 } else { 239 if (io_val & BIT(g->out_bit)) 240 msm_writel_io(io_val & ~BIT(g->out_bit), pctrl, g); 241 } 242 } 243 244 if (egpio_func && i == egpio_func) { 245 if (val & BIT(g->egpio_present)) 246 val &= ~BIT(g->egpio_enable); 247 } else { 248 val &= ~mask; 249 val |= i << g->mux_bit; 250 /* Claim ownership of pin if egpio capable */ 251 if (egpio_func && val & BIT(g->egpio_present)) 252 val |= BIT(g->egpio_enable); 253 } 254 255 msm_writel_ctl(val, pctrl, g); 256 257 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 258 259 if (d && i == gpio_func && 260 test_and_clear_bit(d->hwirq, pctrl->disabled_for_mux)) { 261 /* 262 * Clear interrupts detected while not GPIO since we only 263 * masked things. 264 */ 265 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) 266 irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false); 267 else 268 msm_ack_intr_status(pctrl, g); 269 270 enable_irq(irq); 271 } 272 273 return 0; 274} 275 276static int msm_pinmux_request_gpio(struct pinctrl_dev *pctldev, 277 struct pinctrl_gpio_range *range, 278 unsigned offset) 279{ 280 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 281 const struct msm_pingroup *g = &pctrl->soc->groups[offset]; 282 283 /* No funcs? Probably ACPI so can't do anything here */ 284 if (!g->nfuncs) 285 return 0; 286 287 return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset); 288} 289 290static const struct pinmux_ops msm_pinmux_ops = { 291 .request = msm_pinmux_request, 292 .get_functions_count = msm_get_functions_count, 293 .get_function_name = msm_get_function_name, 294 .get_function_groups = msm_get_function_groups, 295 .gpio_request_enable = msm_pinmux_request_gpio, 296 .set_mux = msm_pinmux_set_mux, 297}; 298 299static int msm_config_reg(struct msm_pinctrl *pctrl, 300 const struct msm_pingroup *g, 301 unsigned param, 302 unsigned *mask, 303 unsigned *bit) 304{ 305 switch (param) { 306 case PIN_CONFIG_BIAS_DISABLE: 307 case PIN_CONFIG_BIAS_PULL_DOWN: 308 case PIN_CONFIG_BIAS_BUS_HOLD: 309 case PIN_CONFIG_BIAS_PULL_UP: 310 *bit = g->pull_bit; 311 *mask = 3; 312 if (g->i2c_pull_bit) 313 *mask |= BIT(g->i2c_pull_bit) >> *bit; 314 break; 315 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 316 *bit = g->od_bit; 317 *mask = 1; 318 break; 319 case PIN_CONFIG_DRIVE_STRENGTH: 320 *bit = g->drv_bit; 321 *mask = 7; 322 break; 323 case PIN_CONFIG_OUTPUT: 324 case PIN_CONFIG_INPUT_ENABLE: 325 case PIN_CONFIG_OUTPUT_ENABLE: 326 *bit = g->oe_bit; 327 *mask = 1; 328 break; 329 default: 330 return -ENOTSUPP; 331 } 332 333 return 0; 334} 335 336#define MSM_NO_PULL 0 337#define MSM_PULL_DOWN 1 338#define MSM_KEEPER 2 339#define MSM_PULL_UP_NO_KEEPER 2 340#define MSM_PULL_UP 3 341#define MSM_I2C_STRONG_PULL_UP 2200 342 343static unsigned msm_regval_to_drive(u32 val) 344{ 345 return (val + 1) * 2; 346} 347 348static int msm_config_group_get(struct pinctrl_dev *pctldev, 349 unsigned int group, 350 unsigned long *config) 351{ 352 const struct msm_pingroup *g; 353 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 354 unsigned param = pinconf_to_config_param(*config); 355 unsigned mask; 356 unsigned arg; 357 unsigned bit; 358 int ret; 359 u32 val; 360 361 /* Pin information can only be requested from valid pin groups */ 362 if (!gpiochip_line_is_valid(&pctrl->chip, group)) 363 return -EINVAL; 364 365 g = &pctrl->soc->groups[group]; 366 367 ret = msm_config_reg(pctrl, g, param, &mask, &bit); 368 if (ret < 0) 369 return ret; 370 371 val = msm_readl_ctl(pctrl, g); 372 arg = (val >> bit) & mask; 373 374 /* Convert register value to pinconf value */ 375 switch (param) { 376 case PIN_CONFIG_BIAS_DISABLE: 377 if (arg != MSM_NO_PULL) 378 return -EINVAL; 379 arg = 1; 380 break; 381 case PIN_CONFIG_BIAS_PULL_DOWN: 382 if (arg != MSM_PULL_DOWN) 383 return -EINVAL; 384 arg = 1; 385 break; 386 case PIN_CONFIG_BIAS_BUS_HOLD: 387 if (pctrl->soc->pull_no_keeper) 388 return -ENOTSUPP; 389 390 if (arg != MSM_KEEPER) 391 return -EINVAL; 392 arg = 1; 393 break; 394 case PIN_CONFIG_BIAS_PULL_UP: 395 if (pctrl->soc->pull_no_keeper) 396 arg = arg == MSM_PULL_UP_NO_KEEPER; 397 else if (arg & BIT(g->i2c_pull_bit)) 398 arg = MSM_I2C_STRONG_PULL_UP; 399 else 400 arg = arg == MSM_PULL_UP; 401 if (!arg) 402 return -EINVAL; 403 break; 404 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 405 /* Pin is not open-drain */ 406 if (!arg) 407 return -EINVAL; 408 arg = 1; 409 break; 410 case PIN_CONFIG_DRIVE_STRENGTH: 411 arg = msm_regval_to_drive(arg); 412 break; 413 case PIN_CONFIG_OUTPUT: 414 /* Pin is not output */ 415 if (!arg) 416 return -EINVAL; 417 418 val = msm_readl_io(pctrl, g); 419 arg = !!(val & BIT(g->in_bit)); 420 break; 421 case PIN_CONFIG_OUTPUT_ENABLE: 422 if (!arg) 423 return -EINVAL; 424 break; 425 default: 426 return -ENOTSUPP; 427 } 428 429 *config = pinconf_to_config_packed(param, arg); 430 431 return 0; 432} 433 434static int msm_config_group_set(struct pinctrl_dev *pctldev, 435 unsigned group, 436 unsigned long *configs, 437 unsigned num_configs) 438{ 439 const struct msm_pingroup *g; 440 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 441 unsigned long flags; 442 unsigned param; 443 unsigned mask; 444 unsigned arg; 445 unsigned bit; 446 int ret; 447 u32 val; 448 int i; 449 450 g = &pctrl->soc->groups[group]; 451 452 for (i = 0; i < num_configs; i++) { 453 param = pinconf_to_config_param(configs[i]); 454 arg = pinconf_to_config_argument(configs[i]); 455 456 ret = msm_config_reg(pctrl, g, param, &mask, &bit); 457 if (ret < 0) 458 return ret; 459 460 /* Convert pinconf values to register values */ 461 switch (param) { 462 case PIN_CONFIG_BIAS_DISABLE: 463 arg = MSM_NO_PULL; 464 break; 465 case PIN_CONFIG_BIAS_PULL_DOWN: 466 arg = MSM_PULL_DOWN; 467 break; 468 case PIN_CONFIG_BIAS_BUS_HOLD: 469 if (pctrl->soc->pull_no_keeper) 470 return -ENOTSUPP; 471 472 arg = MSM_KEEPER; 473 break; 474 case PIN_CONFIG_BIAS_PULL_UP: 475 if (pctrl->soc->pull_no_keeper) 476 arg = MSM_PULL_UP_NO_KEEPER; 477 else if (g->i2c_pull_bit && arg == MSM_I2C_STRONG_PULL_UP) 478 arg = BIT(g->i2c_pull_bit) | MSM_PULL_UP; 479 else 480 arg = MSM_PULL_UP; 481 break; 482 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 483 arg = 1; 484 break; 485 case PIN_CONFIG_DRIVE_STRENGTH: 486 /* Check for invalid values */ 487 if (arg > 16 || arg < 2 || (arg % 2) != 0) 488 arg = -1; 489 else 490 arg = (arg / 2) - 1; 491 break; 492 case PIN_CONFIG_OUTPUT: 493 /* set output value */ 494 raw_spin_lock_irqsave(&pctrl->lock, flags); 495 val = msm_readl_io(pctrl, g); 496 if (arg) 497 val |= BIT(g->out_bit); 498 else 499 val &= ~BIT(g->out_bit); 500 msm_writel_io(val, pctrl, g); 501 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 502 503 /* enable output */ 504 arg = 1; 505 break; 506 case PIN_CONFIG_INPUT_ENABLE: 507 /* 508 * According to pinctrl documentation this should 509 * actually be a no-op. 510 * 511 * The docs are explicit that "this does not affect 512 * the pin's ability to drive output" but what we do 513 * here is to modify the output enable bit. Thus, to 514 * follow the docs we should remove that. 515 * 516 * The docs say that we should enable any relevant 517 * input buffer, but TLMM there is no input buffer that 518 * can be enabled/disabled. It's always on. 519 * 520 * The points above, explain why this _should_ be a 521 * no-op. However, for historical reasons and to 522 * support old device trees, we'll violate the docs 523 * and still affect the output. 524 * 525 * It should further be noted that this old historical 526 * behavior actually overrides arg to 0. That means 527 * that "input-enable" and "input-disable" in a device 528 * tree would _both_ disable the output. We'll 529 * continue to preserve this behavior as well since 530 * we have no other use for this attribute. 531 */ 532 arg = 0; 533 break; 534 case PIN_CONFIG_OUTPUT_ENABLE: 535 arg = !!arg; 536 break; 537 default: 538 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", 539 param); 540 return -EINVAL; 541 } 542 543 /* Range-check user-supplied value */ 544 if (arg & ~mask) { 545 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); 546 return -EINVAL; 547 } 548 549 raw_spin_lock_irqsave(&pctrl->lock, flags); 550 val = msm_readl_ctl(pctrl, g); 551 val &= ~(mask << bit); 552 val |= arg << bit; 553 msm_writel_ctl(val, pctrl, g); 554 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 555 } 556 557 return 0; 558} 559 560static const struct pinconf_ops msm_pinconf_ops = { 561 .is_generic = true, 562 .pin_config_group_get = msm_config_group_get, 563 .pin_config_group_set = msm_config_group_set, 564}; 565 566static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 567{ 568 const struct msm_pingroup *g; 569 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 570 unsigned long flags; 571 u32 val; 572 573 g = &pctrl->soc->groups[offset]; 574 575 raw_spin_lock_irqsave(&pctrl->lock, flags); 576 577 val = msm_readl_ctl(pctrl, g); 578 val &= ~BIT(g->oe_bit); 579 msm_writel_ctl(val, pctrl, g); 580 581 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 582 583 return 0; 584} 585 586static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) 587{ 588 const struct msm_pingroup *g; 589 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 590 unsigned long flags; 591 u32 val; 592 593 g = &pctrl->soc->groups[offset]; 594 595 raw_spin_lock_irqsave(&pctrl->lock, flags); 596 597 val = msm_readl_io(pctrl, g); 598 if (value) 599 val |= BIT(g->out_bit); 600 else 601 val &= ~BIT(g->out_bit); 602 msm_writel_io(val, pctrl, g); 603 604 val = msm_readl_ctl(pctrl, g); 605 val |= BIT(g->oe_bit); 606 msm_writel_ctl(val, pctrl, g); 607 608 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 609 610 return 0; 611} 612 613static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 614{ 615 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 616 const struct msm_pingroup *g; 617 u32 val; 618 619 g = &pctrl->soc->groups[offset]; 620 621 val = msm_readl_ctl(pctrl, g); 622 623 return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT : 624 GPIO_LINE_DIRECTION_IN; 625} 626 627static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) 628{ 629 const struct msm_pingroup *g; 630 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 631 u32 val; 632 633 g = &pctrl->soc->groups[offset]; 634 635 val = msm_readl_io(pctrl, g); 636 return !!(val & BIT(g->in_bit)); 637} 638 639static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 640{ 641 const struct msm_pingroup *g; 642 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 643 unsigned long flags; 644 u32 val; 645 646 g = &pctrl->soc->groups[offset]; 647 648 raw_spin_lock_irqsave(&pctrl->lock, flags); 649 650 val = msm_readl_io(pctrl, g); 651 if (value) 652 val |= BIT(g->out_bit); 653 else 654 val &= ~BIT(g->out_bit); 655 msm_writel_io(val, pctrl, g); 656 657 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 658} 659 660#ifdef CONFIG_DEBUG_FS 661 662static void msm_gpio_dbg_show_one(struct seq_file *s, 663 struct pinctrl_dev *pctldev, 664 struct gpio_chip *chip, 665 unsigned offset, 666 unsigned gpio) 667{ 668 const struct msm_pingroup *g; 669 struct msm_pinctrl *pctrl = gpiochip_get_data(chip); 670 unsigned func; 671 int is_out; 672 int drive; 673 int pull; 674 int val; 675 int egpio_enable; 676 u32 ctl_reg, io_reg; 677 678 static const char * const pulls_keeper[] = { 679 "no pull", 680 "pull down", 681 "keeper", 682 "pull up" 683 }; 684 685 static const char * const pulls_no_keeper[] = { 686 "no pull", 687 "pull down", 688 "pull up", 689 }; 690 691 if (!gpiochip_line_is_valid(chip, offset)) 692 return; 693 694 g = &pctrl->soc->groups[offset]; 695 ctl_reg = msm_readl_ctl(pctrl, g); 696 io_reg = msm_readl_io(pctrl, g); 697 698 is_out = !!(ctl_reg & BIT(g->oe_bit)); 699 func = (ctl_reg >> g->mux_bit) & 7; 700 drive = (ctl_reg >> g->drv_bit) & 7; 701 pull = (ctl_reg >> g->pull_bit) & 3; 702 egpio_enable = 0; 703 if (pctrl->soc->egpio_func && ctl_reg & BIT(g->egpio_present)) 704 egpio_enable = !(ctl_reg & BIT(g->egpio_enable)); 705 706 if (is_out) 707 val = !!(io_reg & BIT(g->out_bit)); 708 else 709 val = !!(io_reg & BIT(g->in_bit)); 710 711 if (egpio_enable) { 712 seq_printf(s, " %-8s: egpio\n", g->grp.name); 713 return; 714 } 715 716 seq_printf(s, " %-8s: %-3s", g->grp.name, is_out ? "out" : "in"); 717 seq_printf(s, " %-4s func%d", val ? "high" : "low", func); 718 seq_printf(s, " %dmA", msm_regval_to_drive(drive)); 719 if (pctrl->soc->pull_no_keeper) 720 seq_printf(s, " %s", pulls_no_keeper[pull]); 721 else 722 seq_printf(s, " %s", pulls_keeper[pull]); 723 seq_puts(s, "\n"); 724} 725 726static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 727{ 728 unsigned gpio = chip->base; 729 unsigned i; 730 731 for (i = 0; i < chip->ngpio; i++, gpio++) 732 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); 733} 734 735#else 736#define msm_gpio_dbg_show NULL 737#endif 738 739static int msm_gpio_init_valid_mask(struct gpio_chip *gc, 740 unsigned long *valid_mask, 741 unsigned int ngpios) 742{ 743 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 744 int ret; 745 unsigned int len, i; 746 const int *reserved = pctrl->soc->reserved_gpios; 747 u16 *tmp; 748 749 /* Remove driver-provided reserved GPIOs from valid_mask */ 750 if (reserved) { 751 for (i = 0; reserved[i] >= 0; i++) { 752 if (i >= ngpios || reserved[i] >= ngpios) { 753 dev_err(pctrl->dev, "invalid list of reserved GPIOs\n"); 754 return -EINVAL; 755 } 756 clear_bit(reserved[i], valid_mask); 757 } 758 759 return 0; 760 } 761 762 /* The number of GPIOs in the ACPI tables */ 763 len = ret = device_property_count_u16(pctrl->dev, "gpios"); 764 if (ret < 0) 765 return 0; 766 767 if (ret > ngpios) 768 return -EINVAL; 769 770 tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL); 771 if (!tmp) 772 return -ENOMEM; 773 774 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len); 775 if (ret < 0) { 776 dev_err(pctrl->dev, "could not read list of GPIOs\n"); 777 goto out; 778 } 779 780 bitmap_zero(valid_mask, ngpios); 781 for (i = 0; i < len; i++) 782 set_bit(tmp[i], valid_mask); 783 784out: 785 kfree(tmp); 786 return ret; 787} 788 789static const struct gpio_chip msm_gpio_template = { 790 .direction_input = msm_gpio_direction_input, 791 .direction_output = msm_gpio_direction_output, 792 .get_direction = msm_gpio_get_direction, 793 .get = msm_gpio_get, 794 .set = msm_gpio_set, 795 .request = gpiochip_generic_request, 796 .free = gpiochip_generic_free, 797 .dbg_show = msm_gpio_dbg_show, 798}; 799 800/* For dual-edge interrupts in software, since some hardware has no 801 * such support: 802 * 803 * At appropriate moments, this function may be called to flip the polarity 804 * settings of both-edge irq lines to try and catch the next edge. 805 * 806 * The attempt is considered successful if: 807 * - the status bit goes high, indicating that an edge was caught, or 808 * - the input value of the gpio doesn't change during the attempt. 809 * If the value changes twice during the process, that would cause the first 810 * test to fail but would force the second, as two opposite 811 * transitions would cause a detection no matter the polarity setting. 812 * 813 * The do-loop tries to sledge-hammer closed the timing hole between 814 * the initial value-read and the polarity-write - if the line value changes 815 * during that window, an interrupt is lost, the new polarity setting is 816 * incorrect, and the first success test will fail, causing a retry. 817 * 818 * Algorithm comes from Google's msmgpio driver. 819 */ 820static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, 821 const struct msm_pingroup *g, 822 struct irq_data *d) 823{ 824 int loop_limit = 100; 825 unsigned val, val2, intstat; 826 unsigned pol; 827 828 do { 829 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); 830 831 pol = msm_readl_intr_cfg(pctrl, g); 832 pol ^= BIT(g->intr_polarity_bit); 833 msm_writel_intr_cfg(pol, pctrl, g); 834 835 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit); 836 intstat = msm_readl_intr_status(pctrl, g); 837 if (intstat || (val == val2)) 838 return; 839 } while (loop_limit-- > 0); 840 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", 841 val, val2); 842} 843 844static void msm_gpio_irq_mask(struct irq_data *d) 845{ 846 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 847 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 848 const struct msm_pingroup *g; 849 unsigned long flags; 850 u32 val; 851 852 if (d->parent_data) 853 irq_chip_mask_parent(d); 854 855 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) 856 return; 857 858 g = &pctrl->soc->groups[d->hwirq]; 859 860 raw_spin_lock_irqsave(&pctrl->lock, flags); 861 862 val = msm_readl_intr_cfg(pctrl, g); 863 /* 864 * There are two bits that control interrupt forwarding to the CPU. The 865 * RAW_STATUS_EN bit causes the level or edge sensed on the line to be 866 * latched into the interrupt status register when the hardware detects 867 * an irq that it's configured for (either edge for edge type or level 868 * for level type irq). The 'non-raw' status enable bit causes the 869 * hardware to assert the summary interrupt to the CPU if the latched 870 * status bit is set. There's a bug though, the edge detection logic 871 * seems to have a problem where toggling the RAW_STATUS_EN bit may 872 * cause the status bit to latch spuriously when there isn't any edge 873 * so we can't touch that bit for edge type irqs and we have to keep 874 * the bit set anyway so that edges are latched while the line is masked. 875 * 876 * To make matters more complicated, leaving the RAW_STATUS_EN bit 877 * enabled all the time causes level interrupts to re-latch into the 878 * status register because the level is still present on the line after 879 * we ack it. We clear the raw status enable bit during mask here and 880 * set the bit on unmask so the interrupt can't latch into the hardware 881 * while it's masked. 882 */ 883 if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK) 884 val &= ~BIT(g->intr_raw_status_bit); 885 886 val &= ~BIT(g->intr_enable_bit); 887 msm_writel_intr_cfg(val, pctrl, g); 888 889 clear_bit(d->hwirq, pctrl->enabled_irqs); 890 891 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 892} 893 894static void msm_gpio_irq_unmask(struct irq_data *d) 895{ 896 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 897 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 898 const struct msm_pingroup *g; 899 unsigned long flags; 900 u32 val; 901 902 if (d->parent_data) 903 irq_chip_unmask_parent(d); 904 905 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) 906 return; 907 908 g = &pctrl->soc->groups[d->hwirq]; 909 910 raw_spin_lock_irqsave(&pctrl->lock, flags); 911 912 val = msm_readl_intr_cfg(pctrl, g); 913 val |= BIT(g->intr_raw_status_bit); 914 val |= BIT(g->intr_enable_bit); 915 msm_writel_intr_cfg(val, pctrl, g); 916 917 set_bit(d->hwirq, pctrl->enabled_irqs); 918 919 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 920} 921 922static void msm_gpio_irq_enable(struct irq_data *d) 923{ 924 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 925 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 926 927 gpiochip_enable_irq(gc, d->hwirq); 928 929 if (d->parent_data) 930 irq_chip_enable_parent(d); 931 932 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) 933 msm_gpio_irq_unmask(d); 934} 935 936static void msm_gpio_irq_disable(struct irq_data *d) 937{ 938 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 939 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 940 941 if (d->parent_data) 942 irq_chip_disable_parent(d); 943 944 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs)) 945 msm_gpio_irq_mask(d); 946 947 gpiochip_disable_irq(gc, d->hwirq); 948} 949 950/** 951 * msm_gpio_update_dual_edge_parent() - Prime next edge for IRQs handled by parent. 952 * @d: The irq dta. 953 * 954 * This is much like msm_gpio_update_dual_edge_pos() but for IRQs that are 955 * normally handled by the parent irqchip. The logic here is slightly 956 * different due to what's easy to do with our parent, but in principle it's 957 * the same. 958 */ 959static void msm_gpio_update_dual_edge_parent(struct irq_data *d) 960{ 961 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 962 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 963 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; 964 int loop_limit = 100; 965 unsigned int val; 966 unsigned int type; 967 968 /* Read the value and make a guess about what edge we need to catch */ 969 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); 970 type = val ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING; 971 972 do { 973 /* Set the parent to catch the next edge */ 974 irq_chip_set_type_parent(d, type); 975 976 /* 977 * Possibly the line changed between when we last read "val" 978 * (and decided what edge we needed) and when set the edge. 979 * If the value didn't change (or changed and then changed 980 * back) then we're done. 981 */ 982 val = msm_readl_io(pctrl, g) & BIT(g->in_bit); 983 if (type == IRQ_TYPE_EDGE_RISING) { 984 if (!val) 985 return; 986 type = IRQ_TYPE_EDGE_FALLING; 987 } else if (type == IRQ_TYPE_EDGE_FALLING) { 988 if (val) 989 return; 990 type = IRQ_TYPE_EDGE_RISING; 991 } 992 } while (loop_limit-- > 0); 993 dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n"); 994} 995 996static void msm_gpio_irq_ack(struct irq_data *d) 997{ 998 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 999 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 1000 const struct msm_pingroup *g; 1001 unsigned long flags; 1002 1003 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { 1004 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) 1005 msm_gpio_update_dual_edge_parent(d); 1006 return; 1007 } 1008 1009 g = &pctrl->soc->groups[d->hwirq]; 1010 1011 raw_spin_lock_irqsave(&pctrl->lock, flags); 1012 1013 msm_ack_intr_status(pctrl, g); 1014 1015 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) 1016 msm_gpio_update_dual_edge_pos(pctrl, g, d); 1017 1018 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1019} 1020 1021static void msm_gpio_irq_eoi(struct irq_data *d) 1022{ 1023 d = d->parent_data; 1024 1025 if (d) 1026 d->chip->irq_eoi(d); 1027} 1028 1029static bool msm_gpio_needs_dual_edge_parent_workaround(struct irq_data *d, 1030 unsigned int type) 1031{ 1032 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1033 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 1034 1035 return type == IRQ_TYPE_EDGE_BOTH && 1036 pctrl->soc->wakeirq_dual_edge_errata && d->parent_data && 1037 test_bit(d->hwirq, pctrl->skip_wake_irqs); 1038} 1039 1040static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) 1041{ 1042 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1043 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 1044 const struct msm_pingroup *g; 1045 u32 intr_target_mask = GENMASK(2, 0); 1046 unsigned long flags; 1047 bool was_enabled; 1048 u32 val; 1049 1050 if (msm_gpio_needs_dual_edge_parent_workaround(d, type)) { 1051 set_bit(d->hwirq, pctrl->dual_edge_irqs); 1052 irq_set_handler_locked(d, handle_fasteoi_ack_irq); 1053 msm_gpio_update_dual_edge_parent(d); 1054 return 0; 1055 } 1056 1057 if (d->parent_data) 1058 irq_chip_set_type_parent(d, type); 1059 1060 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) { 1061 clear_bit(d->hwirq, pctrl->dual_edge_irqs); 1062 irq_set_handler_locked(d, handle_fasteoi_irq); 1063 return 0; 1064 } 1065 1066 g = &pctrl->soc->groups[d->hwirq]; 1067 1068 raw_spin_lock_irqsave(&pctrl->lock, flags); 1069 1070 /* 1071 * For hw without possibility of detecting both edges 1072 */ 1073 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) 1074 set_bit(d->hwirq, pctrl->dual_edge_irqs); 1075 else 1076 clear_bit(d->hwirq, pctrl->dual_edge_irqs); 1077 1078 /* Route interrupts to application cpu. 1079 * With intr_target_use_scm interrupts are routed to 1080 * application cpu using scm calls. 1081 */ 1082 if (g->intr_target_width) 1083 intr_target_mask = GENMASK(g->intr_target_width - 1, 0); 1084 1085 if (pctrl->intr_target_use_scm) { 1086 u32 addr = pctrl->phys_base[0] + g->intr_target_reg; 1087 int ret; 1088 1089 qcom_scm_io_readl(addr, &val); 1090 val &= ~(intr_target_mask << g->intr_target_bit); 1091 val |= g->intr_target_kpss_val << g->intr_target_bit; 1092 1093 ret = qcom_scm_io_writel(addr, val); 1094 if (ret) 1095 dev_err(pctrl->dev, 1096 "Failed routing %lu interrupt to Apps proc", 1097 d->hwirq); 1098 } else { 1099 val = msm_readl_intr_target(pctrl, g); 1100 val &= ~(intr_target_mask << g->intr_target_bit); 1101 val |= g->intr_target_kpss_val << g->intr_target_bit; 1102 msm_writel_intr_target(val, pctrl, g); 1103 } 1104 1105 /* Update configuration for gpio. 1106 * RAW_STATUS_EN is left on for all gpio irqs. Due to the 1107 * internal circuitry of TLMM, toggling the RAW_STATUS 1108 * could cause the INTR_STATUS to be set for EDGE interrupts. 1109 */ 1110 val = msm_readl_intr_cfg(pctrl, g); 1111 was_enabled = val & BIT(g->intr_raw_status_bit); 1112 val |= BIT(g->intr_raw_status_bit); 1113 if (g->intr_detection_width == 2) { 1114 val &= ~(3 << g->intr_detection_bit); 1115 val &= ~(1 << g->intr_polarity_bit); 1116 switch (type) { 1117 case IRQ_TYPE_EDGE_RISING: 1118 val |= 1 << g->intr_detection_bit; 1119 val |= BIT(g->intr_polarity_bit); 1120 break; 1121 case IRQ_TYPE_EDGE_FALLING: 1122 val |= 2 << g->intr_detection_bit; 1123 val |= BIT(g->intr_polarity_bit); 1124 break; 1125 case IRQ_TYPE_EDGE_BOTH: 1126 val |= 3 << g->intr_detection_bit; 1127 val |= BIT(g->intr_polarity_bit); 1128 break; 1129 case IRQ_TYPE_LEVEL_LOW: 1130 break; 1131 case IRQ_TYPE_LEVEL_HIGH: 1132 val |= BIT(g->intr_polarity_bit); 1133 break; 1134 } 1135 } else if (g->intr_detection_width == 1) { 1136 val &= ~(1 << g->intr_detection_bit); 1137 val &= ~(1 << g->intr_polarity_bit); 1138 switch (type) { 1139 case IRQ_TYPE_EDGE_RISING: 1140 val |= BIT(g->intr_detection_bit); 1141 val |= BIT(g->intr_polarity_bit); 1142 break; 1143 case IRQ_TYPE_EDGE_FALLING: 1144 val |= BIT(g->intr_detection_bit); 1145 break; 1146 case IRQ_TYPE_EDGE_BOTH: 1147 val |= BIT(g->intr_detection_bit); 1148 val |= BIT(g->intr_polarity_bit); 1149 break; 1150 case IRQ_TYPE_LEVEL_LOW: 1151 break; 1152 case IRQ_TYPE_LEVEL_HIGH: 1153 val |= BIT(g->intr_polarity_bit); 1154 break; 1155 } 1156 } else { 1157 BUG(); 1158 } 1159 msm_writel_intr_cfg(val, pctrl, g); 1160 1161 /* 1162 * The first time we set RAW_STATUS_EN it could trigger an interrupt. 1163 * Clear the interrupt. This is safe because we have 1164 * IRQCHIP_SET_TYPE_MASKED. 1165 */ 1166 if (!was_enabled) 1167 msm_ack_intr_status(pctrl, g); 1168 1169 if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) 1170 msm_gpio_update_dual_edge_pos(pctrl, g, d); 1171 1172 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1173 1174 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 1175 irq_set_handler_locked(d, handle_level_irq); 1176 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 1177 irq_set_handler_locked(d, handle_edge_irq); 1178 1179 return 0; 1180} 1181 1182static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 1183{ 1184 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1185 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 1186 1187 /* 1188 * While they may not wake up when the TLMM is powered off, 1189 * some GPIOs would like to wakeup the system from suspend 1190 * when TLMM is powered on. To allow that, enable the GPIO 1191 * summary line to be wakeup capable at GIC. 1192 */ 1193 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) 1194 return irq_chip_set_wake_parent(d, on); 1195 1196 return irq_set_irq_wake(pctrl->irq, on); 1197} 1198 1199static int msm_gpio_irq_reqres(struct irq_data *d) 1200{ 1201 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1202 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 1203 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; 1204 unsigned long flags; 1205 int ret; 1206 1207 if (!try_module_get(gc->owner)) 1208 return -ENODEV; 1209 1210 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq); 1211 if (ret) 1212 goto out; 1213 msm_gpio_direction_input(gc, d->hwirq); 1214 1215 if (gpiochip_lock_as_irq(gc, d->hwirq)) { 1216 dev_err(gc->parent, 1217 "unable to lock HW IRQ %lu for IRQ\n", 1218 d->hwirq); 1219 ret = -EINVAL; 1220 goto out; 1221 } 1222 1223 /* 1224 * The disable / clear-enable workaround we do in msm_pinmux_set_mux() 1225 * only works if disable is not lazy since we only clear any bogus 1226 * interrupt in hardware. Explicitly mark the interrupt as UNLAZY. 1227 */ 1228 irq_set_status_flags(d->irq, IRQ_DISABLE_UNLAZY); 1229 1230 /* 1231 * If the wakeup_enable bit is present and marked as available for the 1232 * requested GPIO, it should be enabled when the GPIO is marked as 1233 * wake irq in order to allow the interrupt event to be transfered to 1234 * the PDC HW. 1235 * While the name implies only the wakeup event, it's also required for 1236 * the interrupt event. 1237 */ 1238 if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) { 1239 u32 intr_cfg; 1240 1241 raw_spin_lock_irqsave(&pctrl->lock, flags); 1242 1243 intr_cfg = msm_readl_intr_cfg(pctrl, g); 1244 if (intr_cfg & BIT(g->intr_wakeup_present_bit)) { 1245 intr_cfg |= BIT(g->intr_wakeup_enable_bit); 1246 msm_writel_intr_cfg(intr_cfg, pctrl, g); 1247 } 1248 1249 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1250 } 1251 1252 return 0; 1253out: 1254 module_put(gc->owner); 1255 return ret; 1256} 1257 1258static void msm_gpio_irq_relres(struct irq_data *d) 1259{ 1260 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1261 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 1262 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq]; 1263 unsigned long flags; 1264 1265 /* Disable the wakeup_enable bit if it has been set in msm_gpio_irq_reqres() */ 1266 if (test_bit(d->hwirq, pctrl->skip_wake_irqs) && g->intr_wakeup_present_bit) { 1267 u32 intr_cfg; 1268 1269 raw_spin_lock_irqsave(&pctrl->lock, flags); 1270 1271 intr_cfg = msm_readl_intr_cfg(pctrl, g); 1272 if (intr_cfg & BIT(g->intr_wakeup_present_bit)) { 1273 intr_cfg &= ~BIT(g->intr_wakeup_enable_bit); 1274 msm_writel_intr_cfg(intr_cfg, pctrl, g); 1275 } 1276 1277 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1278 } 1279 1280 gpiochip_unlock_as_irq(gc, d->hwirq); 1281 module_put(gc->owner); 1282} 1283 1284static int msm_gpio_irq_set_affinity(struct irq_data *d, 1285 const struct cpumask *dest, bool force) 1286{ 1287 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1288 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 1289 1290 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) 1291 return irq_chip_set_affinity_parent(d, dest, force); 1292 1293 return -EINVAL; 1294} 1295 1296static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) 1297{ 1298 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1299 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 1300 1301 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs)) 1302 return irq_chip_set_vcpu_affinity_parent(d, vcpu_info); 1303 1304 return -EINVAL; 1305} 1306 1307static void msm_gpio_irq_handler(struct irq_desc *desc) 1308{ 1309 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1310 const struct msm_pingroup *g; 1311 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 1312 struct irq_chip *chip = irq_desc_get_chip(desc); 1313 int handled = 0; 1314 u32 val; 1315 int i; 1316 1317 chained_irq_enter(chip, desc); 1318 1319 /* 1320 * Each pin has it's own IRQ status register, so use 1321 * enabled_irq bitmap to limit the number of reads. 1322 */ 1323 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { 1324 g = &pctrl->soc->groups[i]; 1325 val = msm_readl_intr_status(pctrl, g); 1326 if (val & BIT(g->intr_status_bit)) { 1327 generic_handle_domain_irq(gc->irq.domain, i); 1328 handled++; 1329 } 1330 } 1331 1332 /* No interrupts were flagged */ 1333 if (handled == 0) 1334 handle_bad_irq(desc); 1335 1336 chained_irq_exit(chip, desc); 1337} 1338 1339static int msm_gpio_wakeirq(struct gpio_chip *gc, 1340 unsigned int child, 1341 unsigned int child_type, 1342 unsigned int *parent, 1343 unsigned int *parent_type) 1344{ 1345 struct msm_pinctrl *pctrl = gpiochip_get_data(gc); 1346 const struct msm_gpio_wakeirq_map *map; 1347 int i; 1348 1349 *parent = GPIO_NO_WAKE_IRQ; 1350 *parent_type = IRQ_TYPE_EDGE_RISING; 1351 1352 for (i = 0; i < pctrl->soc->nwakeirq_map; i++) { 1353 map = &pctrl->soc->wakeirq_map[i]; 1354 if (map->gpio == child) { 1355 *parent = map->wakeirq; 1356 break; 1357 } 1358 } 1359 1360 return 0; 1361} 1362 1363static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl) 1364{ 1365 if (pctrl->soc->reserved_gpios) 1366 return true; 1367 1368 return device_property_count_u16(pctrl->dev, "gpios") > 0; 1369} 1370 1371static const struct irq_chip msm_gpio_irq_chip = { 1372 .name = "msmgpio", 1373 .irq_enable = msm_gpio_irq_enable, 1374 .irq_disable = msm_gpio_irq_disable, 1375 .irq_mask = msm_gpio_irq_mask, 1376 .irq_unmask = msm_gpio_irq_unmask, 1377 .irq_ack = msm_gpio_irq_ack, 1378 .irq_eoi = msm_gpio_irq_eoi, 1379 .irq_set_type = msm_gpio_irq_set_type, 1380 .irq_set_wake = msm_gpio_irq_set_wake, 1381 .irq_request_resources = msm_gpio_irq_reqres, 1382 .irq_release_resources = msm_gpio_irq_relres, 1383 .irq_set_affinity = msm_gpio_irq_set_affinity, 1384 .irq_set_vcpu_affinity = msm_gpio_irq_set_vcpu_affinity, 1385 .flags = (IRQCHIP_MASK_ON_SUSPEND | 1386 IRQCHIP_SET_TYPE_MASKED | 1387 IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | 1388 IRQCHIP_IMMUTABLE), 1389}; 1390 1391static int msm_gpio_init(struct msm_pinctrl *pctrl) 1392{ 1393 struct gpio_chip *chip; 1394 struct gpio_irq_chip *girq; 1395 int i, ret; 1396 unsigned gpio, ngpio = pctrl->soc->ngpios; 1397 struct device_node *np; 1398 bool skip; 1399 1400 if (WARN_ON(ngpio > MAX_NR_GPIO)) 1401 return -EINVAL; 1402 1403 chip = &pctrl->chip; 1404 chip->base = -1; 1405 chip->ngpio = ngpio; 1406 chip->label = dev_name(pctrl->dev); 1407 chip->parent = pctrl->dev; 1408 chip->owner = THIS_MODULE; 1409 if (msm_gpio_needs_valid_mask(pctrl)) 1410 chip->init_valid_mask = msm_gpio_init_valid_mask; 1411 1412 np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0); 1413 if (np) { 1414 chip->irq.parent_domain = irq_find_matching_host(np, 1415 DOMAIN_BUS_WAKEUP); 1416 of_node_put(np); 1417 if (!chip->irq.parent_domain) 1418 return -EPROBE_DEFER; 1419 chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq; 1420 /* 1421 * Let's skip handling the GPIOs, if the parent irqchip 1422 * is handling the direct connect IRQ of the GPIO. 1423 */ 1424 skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain); 1425 for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) { 1426 gpio = pctrl->soc->wakeirq_map[i].gpio; 1427 set_bit(gpio, pctrl->skip_wake_irqs); 1428 } 1429 } 1430 1431 girq = &chip->irq; 1432 gpio_irq_chip_set_chip(girq, &msm_gpio_irq_chip); 1433 girq->parent_handler = msm_gpio_irq_handler; 1434 girq->fwnode = dev_fwnode(pctrl->dev); 1435 girq->num_parents = 1; 1436 girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents), 1437 GFP_KERNEL); 1438 if (!girq->parents) 1439 return -ENOMEM; 1440 girq->default_type = IRQ_TYPE_NONE; 1441 girq->handler = handle_bad_irq; 1442 girq->parents[0] = pctrl->irq; 1443 1444 ret = gpiochip_add_data(&pctrl->chip, pctrl); 1445 if (ret) { 1446 dev_err(pctrl->dev, "Failed register gpiochip\n"); 1447 return ret; 1448 } 1449 1450 /* 1451 * For DeviceTree-supported systems, the gpio core checks the 1452 * pinctrl's device node for the "gpio-ranges" property. 1453 * If it is present, it takes care of adding the pin ranges 1454 * for the driver. In this case the driver can skip ahead. 1455 * 1456 * In order to remain compatible with older, existing DeviceTree 1457 * files which don't set the "gpio-ranges" property or systems that 1458 * utilize ACPI the driver has to call gpiochip_add_pin_range(). 1459 */ 1460 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) { 1461 ret = gpiochip_add_pin_range(&pctrl->chip, 1462 dev_name(pctrl->dev), 0, 0, chip->ngpio); 1463 if (ret) { 1464 dev_err(pctrl->dev, "Failed to add pin range\n"); 1465 gpiochip_remove(&pctrl->chip); 1466 return ret; 1467 } 1468 } 1469 1470 return 0; 1471} 1472 1473static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action, 1474 void *data) 1475{ 1476 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb); 1477 1478 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET); 1479 mdelay(1000); 1480 return NOTIFY_DONE; 1481} 1482 1483static struct msm_pinctrl *poweroff_pctrl; 1484 1485static void msm_ps_hold_poweroff(void) 1486{ 1487 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL); 1488} 1489 1490static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) 1491{ 1492 int i; 1493 const struct pinfunction *func = pctrl->soc->functions; 1494 1495 for (i = 0; i < pctrl->soc->nfunctions; i++) 1496 if (!strcmp(func[i].name, "ps_hold")) { 1497 pctrl->restart_nb.notifier_call = msm_ps_hold_restart; 1498 pctrl->restart_nb.priority = 128; 1499 if (register_restart_handler(&pctrl->restart_nb)) 1500 dev_err(pctrl->dev, 1501 "failed to setup restart handler.\n"); 1502 poweroff_pctrl = pctrl; 1503 pm_power_off = msm_ps_hold_poweroff; 1504 break; 1505 } 1506} 1507 1508static __maybe_unused int msm_pinctrl_suspend(struct device *dev) 1509{ 1510 struct msm_pinctrl *pctrl = dev_get_drvdata(dev); 1511 1512 return pinctrl_force_sleep(pctrl->pctrl); 1513} 1514 1515static __maybe_unused int msm_pinctrl_resume(struct device *dev) 1516{ 1517 struct msm_pinctrl *pctrl = dev_get_drvdata(dev); 1518 1519 return pinctrl_force_default(pctrl->pctrl); 1520} 1521 1522SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend, 1523 msm_pinctrl_resume); 1524 1525EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops); 1526 1527int msm_pinctrl_probe(struct platform_device *pdev, 1528 const struct msm_pinctrl_soc_data *soc_data) 1529{ 1530 struct msm_pinctrl *pctrl; 1531 struct resource *res; 1532 int ret; 1533 int i; 1534 1535 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1536 if (!pctrl) 1537 return -ENOMEM; 1538 1539 pctrl->dev = &pdev->dev; 1540 pctrl->soc = soc_data; 1541 pctrl->chip = msm_gpio_template; 1542 pctrl->intr_target_use_scm = of_device_is_compatible( 1543 pctrl->dev->of_node, 1544 "qcom,ipq8064-pinctrl"); 1545 1546 raw_spin_lock_init(&pctrl->lock); 1547 1548 if (soc_data->tiles) { 1549 for (i = 0; i < soc_data->ntiles; i++) { 1550 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1551 soc_data->tiles[i]); 1552 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res); 1553 if (IS_ERR(pctrl->regs[i])) 1554 return PTR_ERR(pctrl->regs[i]); 1555 } 1556 } else { 1557 pctrl->regs[0] = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1558 if (IS_ERR(pctrl->regs[0])) 1559 return PTR_ERR(pctrl->regs[0]); 1560 1561 pctrl->phys_base[0] = res->start; 1562 } 1563 1564 msm_pinctrl_setup_pm_reset(pctrl); 1565 1566 pctrl->irq = platform_get_irq(pdev, 0); 1567 if (pctrl->irq < 0) 1568 return pctrl->irq; 1569 1570 pctrl->desc.owner = THIS_MODULE; 1571 pctrl->desc.pctlops = &msm_pinctrl_ops; 1572 pctrl->desc.pmxops = &msm_pinmux_ops; 1573 pctrl->desc.confops = &msm_pinconf_ops; 1574 pctrl->desc.name = dev_name(&pdev->dev); 1575 pctrl->desc.pins = pctrl->soc->pins; 1576 pctrl->desc.npins = pctrl->soc->npins; 1577 1578 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl); 1579 if (IS_ERR(pctrl->pctrl)) { 1580 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 1581 return PTR_ERR(pctrl->pctrl); 1582 } 1583 1584 ret = msm_gpio_init(pctrl); 1585 if (ret) 1586 return ret; 1587 1588 platform_set_drvdata(pdev, pctrl); 1589 1590 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); 1591 1592 return 0; 1593} 1594EXPORT_SYMBOL(msm_pinctrl_probe); 1595 1596void msm_pinctrl_remove(struct platform_device *pdev) 1597{ 1598 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); 1599 1600 gpiochip_remove(&pctrl->chip); 1601 1602 unregister_restart_handler(&pctrl->restart_nb); 1603} 1604EXPORT_SYMBOL(msm_pinctrl_remove); 1605 1606MODULE_DESCRIPTION("Qualcomm Technologies, Inc. TLMM driver"); 1607MODULE_LICENSE("GPL v2"); 1608