/linux-master/drivers/gpu/drm/i915/display/ |
H A D | intel_dmc.c | 37 * From gen9 onwards we have newly added DMC (Display microcontroller) in display 38 * engine to save and restore the state of display engine when it enter into 74 return i915->display.dmc.dmc; 79 const char *p = i915->display.params.dmc_firmware_path; 564 * Everytime display comes back from low power state this function is called to 569 struct i915_power_domains *power_domains = &i915->display.power.domains; 614 * inactive after the display is uninitialized. 625 intel_dmc_wl_disable(&i915->display); 980 drm_WARN_ON(&i915->drm, i915->display.dmc.wakeref); 981 i915->display [all...] |
H A D | intel_pch_refclk.c | 464 dev_priv->display.dpll.pch_ssc_use = 0; 468 dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_SPLL); 473 dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL1); 478 dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL2); 481 if (dev_priv->display.dpll.pch_ssc_use) 523 has_ck505 = dev_priv->display.vbt.display_clock_mode; 550 /* Ironlake: try to setup display ref clock before DPLL
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H A D | intel_panel.c | 50 struct intel_display *display = &i915->display; local 52 if (display->params.panel_use_ssc >= 0) 53 return display->params.panel_use_ssc != 0; 54 return display->vbt.lvds_use_ssc && 55 !intel_has_quirk(display, QUIRK_LVDS_SSC_DISABLE);
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H A D | intel_fdi.c | 121 dev_priv->display.funcs.fdi->fdi_link_train(crtc, crtc_state); 271 i915->display.fdi.pll_freq = (fdi_pll_clk + 2) * 10000; 273 i915->display.fdi.pll_freq = 270000; 278 drm_dbg(&i915->drm, "FDI PLL freq=%d\n", i915->display.fdi.pll_freq); 287 return i915->display.fdi.pll_freq; 903 rx_ctl_val = dev_priv->display.fdi.rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | 1142 dev_priv->display.funcs.fdi = &ilk_funcs; 1144 dev_priv->display.funcs.fdi = &gen6_funcs; 1147 dev_priv->display.funcs.fdi = &ivb_funcs;
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H A D | intel_global_state.h | 30 list_for_each_entry(obj, &(dev_priv)->display.global.obj_list, head)
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H A D | intel_dpll.c | 312 * display engine's pipe which can be the above fast dot clock rate or a 379 return i915->display.vbt.lvds_ssc_freq; 399 tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe]; 1240 ((intel_panel_use_ssc(i915) && i915->display.vbt.lvds_ssc_freq == 100000) || 1370 dev_priv->display.vbt.lvds_ssc_freq); 1371 refclk = dev_priv->display.vbt.lvds_ssc_freq; 1539 refclk = dev_priv->display.vbt.lvds_ssc_freq; 1588 refclk = dev_priv->display.vbt.lvds_ssc_freq; 1626 refclk = dev_priv->display.vbt.lvds_ssc_freq; 1666 refclk = dev_priv->display [all...] |
/linux-master/tools/perf/ |
H A D | builtin-c2c.c | 109 int display; member in struct:perf_c2c 822 switch (c2c.display) { 1233 switch (c2c.display) { 2116 switch (c2c.display) { 2151 switch (c2c.display) { 2231 bool display = he__display(he, &c2c.shared_clines_stats); local 2236 if (display && c2c_hists) { 2265 if (c2c.display == DISPLAY_SNP_PEER) 2475 if (c2c.display != DISPLAY_SNP_PEER) 2527 display_str[c2c.display]); 2882 const char *display = str; local 3015 const char *display = NULL; local [all...] |
H A D | builtin-help.c | 143 const char *display = getenv("DISPLAY"); local 145 if (display && *display) { 407 * example compat/mingw.h), we use the script web--browse to display
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/linux-master/include/drm/ |
H A D | drm_modes.h | 40 * DVI, etc. And 'screen' refers to the whole of the visible display, which 142 * DRM_MODE_RES_MM - Calculates the display size from resolution and DPI 157 * DRM_MODE_INIT - Initialize display mode 171 * DRM_SIMPLE_MODE - Simple display mode 198 * struct drm_display_mode - DRM kernel-internal display mode structure 199 * @hdisplay: horizontal display size 204 * @vdisplay: vertical display size 209 * @crtc_hdisplay: hardware mode horizontal display size 216 * @crtc_vdisplay: hardware mode vertical display size 223 * This is the kernel API display mod [all...] |
/linux-master/drivers/pinctrl/ |
H A D | pinconf-generic.c | 88 seq_puts(s, items[i].display); 141 seq_printf(s, "%s: 0x%x", conf_items[i].display, 154 pctldev->desc->custom_conf_items[i].display,
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/linux-master/drivers/gpu/drm/i915/gvt/ |
H A D | display.h | 48 (&(vgpu->display.ports[port])) 163 /* per display EDID information */ 165 /* per display DPCD information */
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/linux-master/drivers/gpu/drm/bridge/analogix/ |
H A D | analogix-i2c-dptx.c | 10 #include <drm/display/drm_dp_helper.h>
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/linux-master/drivers/gpu/drm/amd/pm/powerplay/inc/ |
H A D | power_state.h | 159 struct PP_StateDisplayBlock display; member in struct:pp_power_state
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/linux-master/drivers/gpu/drm/nouveau/include/nvif/ |
H A D | outp.h | 6 #include <drm/display/drm_dp.h>
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/linux-master/drivers/media/platform/ti/davinci/ |
H A D | vpif.c | 48 struct platform_device *display; member in struct:vpif_data 464 * where capture and display drivers don't have DT nodes 475 * capture/display drivers. 524 data->display = pdev_display; 546 if (data->display) 547 platform_device_unregister(data->display);
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/linux-master/drivers/gpu/drm/bridge/imx/ |
H A D | imx8mp-hdmi-tx.c | 46 const struct drm_display_info *display, 45 imx8mp_hdmi_phy_init(struct dw_hdmi *dw_hdmi, void *data, const struct drm_display_info *display, const struct drm_display_mode *mode) argument
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/linux-master/drivers/gpu/drm/radeon/ |
H A D | radeon_asic.c | 220 .display = { 288 .display = { 384 .display = { 452 .display = { 520 .display = { 588 .display = { 656 .display = { 724 .display = { 792 .display = { 860 .display [all...] |
/linux-master/drivers/staging/fbtft/ |
H A D | fb_ssd1306.c | 70 /* A[2] = 1b, Enable charge pump during display on */ 108 /* Resume to RAM content display. Output follows RAM content */ 112 * 0 in RAM: OFF in display panel 113 * 1 in RAM: ON in display panel 203 static struct fbtft_display display = { variable in typeref:struct:fbtft_display 219 FBTFT_REGISTER_DRIVER(DRVNAME, "solomon,ssd1306", &display);
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H A D | fb_ili9163.c | 56 * This display: 59 * This particular display has a design error! The controller has 3 pins to 64 * needit so below the parameters for this display. If you have a strain or a 65 * correct display (can happen with chinese) you can copy those parameters and 93 write_reg(par, CMD_DINVCTR, 0x07); /* display inversion */ 105 write_reg(par, MIPI_DCS_SET_DISPLAY_ON); /* display ON */ 230 static struct fbtft_display display = { variable in typeref:struct:fbtft_display 251 FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9163", &display);
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H A D | fb_ili9320.c | 66 /* set non-display area refresh cycle */ 158 write_reg(par, 0x0007, 0x0173); /* 262K color and display ON */ 243 static struct fbtft_display display = { variable in typeref:struct:fbtft_display 258 FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9320", &display);
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H A D | fb_hx8347d.c | 66 /*display on */ 159 static struct fbtft_display display = { variable in typeref:struct:fbtft_display 174 FBTFT_REGISTER_DRIVER(DRVNAME, "himax,hx8347d", &display);
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H A D | fb_bd663474.c | 150 static struct fbtft_display display = { variable in typeref:struct:fbtft_display 162 FBTFT_REGISTER_DRIVER(DRVNAME, "hitachi,bd663474", &display);
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H A D | fb_ili9325.c | 103 write_reg(par, 0x0009, 0x0000); /* set non-display area refresh cycle */ 148 write_reg(par, 0x0007, 0x0133); /* 262K color and display ON */ 235 static struct fbtft_display display = { variable in typeref:struct:fbtft_display 252 FBTFT_REGISTER_DRIVER(DRVNAME, "ilitek,ili9325", &display);
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H A D | fb_ssd1331.c | 179 static struct fbtft_display display = { variable in typeref:struct:fbtft_display 195 FBTFT_REGISTER_DRIVER(DRVNAME, "solomon,ssd1331", &display);
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H A D | fb_ssd1289.c | 155 static struct fbtft_display display = { variable in typeref:struct:fbtft_display 170 FBTFT_REGISTER_DRIVER(DRVNAME, "solomon,ssd1289", &display);
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