Searched refs:dev_priv (Results 126 - 150 of 263) sorted by relevance

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/linux-master/drivers/gpu/drm/gma500/
H A Dpsb_device.c20 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); local
21 psb_intel_lvds_init(dev, &dev_priv->mode_dev);
43 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); local
51 /* get bl_max_freq and pol from dev_priv*/
52 if (!dev_priv->lvds_bl) {
56 bl_max_freq = dev_priv->lvds_bl->freq;
59 core_clock = dev_priv->core_freq;
87 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); local
105 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); local
110 struct psb_state *regs = &dev_priv
149 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); local
250 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); local
[all...]
H A Doaktrail_device.c22 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); local
23 if (dev_priv->iLVDS_enable)
24 oaktrail_lvds_init(dev, &dev_priv->mode_dev);
27 if (dev_priv->hdmi_priv)
28 oaktrail_hdmi_init(dev, &dev_priv->mode_dev);
47 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); local
57 * dev_priv->blc_adj1;
59 blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj1;
63 * dev_priv->blc_adj2;
65 blc_pwm_ctl = blc_pwm_ctl * dev_priv
77 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); local
123 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); local
237 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); local
352 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); local
376 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); local
448 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); local
469 struct drm_psb_private *dev_priv = to_drm_psb_private(dev); local
[all...]
/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_tv.c917 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); local
918 u32 tmp = intel_de_read(dev_priv, TV_CTL);
932 struct drm_i915_private *dev_priv = to_i915(dev); local
937 intel_de_rmw(dev_priv, TV_CTL, 0, TV_ENC_ENABLE);
947 struct drm_i915_private *dev_priv = to_i915(dev); local
949 intel_de_rmw(dev_priv, TV_CTL, TV_ENC_ENABLE, 0);
1095 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); local
1107 tv_ctl = intel_de_read(dev_priv, TV_CTL);
1108 hctl1 = intel_de_read(dev_priv, TV_H_CTL_1);
1109 hctl3 = intel_de_read(dev_priv, TV_H_CTL_
1174 intel_tv_source_too_wide(struct drm_i915_private *dev_priv, int hdisplay) argument
1198 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); local
1358 set_tv_mode_timings(struct drm_i915_private *dev_priv, const struct tv_mode *tv_mode, bool burst_ena) argument
1416 set_color_conversion(struct drm_i915_private *dev_priv, const struct color_conversion *color_conversion) argument
1438 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); local
1589 struct drm_i915_private *dev_priv = to_i915(dev); local
1794 struct drm_i915_private *dev_priv = to_i915(connector->dev); local
1931 intel_tv_init(struct drm_i915_private *dev_priv) argument
[all...]
H A Dintel_display_power_well.h145 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
154 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
157 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
158 void skl_enable_dc6(struct drm_i915_private *dev_priv);
159 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
160 void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state);
161 void gen9_disable_dc_states(struct drm_i915_private *dev_priv);
162 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
163 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
H A Dintel_crtc.c95 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); local
111 if (IS_I965GM(dev_priv) &&
115 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
117 else if (DISPLAY_VER(dev_priv) >= 3)
299 int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) argument
311 crtc->num_scalers = DISPLAY_RUNTIME_INFO(dev_priv)->num_scalers[pipe];
313 if (DISPLAY_VER(dev_priv) >= 9)
314 primary = skl_universal_plane_create(dev_priv, pipe,
317 primary = intel_primary_plane_create(dev_priv, pip
480 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); local
584 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); local
[all...]
H A Di9xx_plane.h25 intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe);
43 intel_primary_plane_create(struct drm_i915_private *dev_priv, int pipe) argument
H A Dintel_bw.h73 void intel_bw_init_hw(struct drm_i915_private *dev_priv);
74 int intel_bw_init(struct drm_i915_private *dev_priv);
78 int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
H A Dintel_dsi_vbt.c105 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); local
111 drm_dbg_kms(&dev_priv->drm, "\n");
123 if (drm_WARN_ON(&dev_priv->drm, !intel_dsi->dsi_hosts[port]))
128 drm_dbg_kms(&dev_priv->drm, "no dsi device for port %c\n",
153 drm_dbg(&dev_priv->drm,
166 drm_dbg(&dev_priv->drm,
174 if (DISPLAY_VER(dev_priv) < 11)
199 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); local
207 gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev, con_id, idx,
210 drm_err(&dev_priv
245 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); local
267 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); local
323 icl_native_gpio_set_value(struct drm_i915_private *dev_priv, int gpio, bool value) argument
614 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); local
750 struct drm_i915_private *dev_priv = to_i915(dev); local
887 struct drm_i915_private *dev_priv = to_i915(dev); local
[all...]
H A Dintel_global_state.c78 void intel_atomic_global_obj_init(struct drm_i915_private *dev_priv, argument
91 list_add_tail(&obj->head, &dev_priv->display.global.obj_list);
94 void intel_atomic_global_obj_cleanup(struct drm_i915_private *dev_priv) argument
98 list_for_each_entry_safe(obj, next, &dev_priv->display.global.obj_list, head) {
101 drm_WARN_ON(&dev_priv->drm, kref_read(&obj->state->ref) != 1);
106 static void assert_global_state_write_locked(struct drm_i915_private *dev_priv) argument
110 for_each_intel_crtc(&dev_priv->drm, crtc)
130 struct drm_i915_private *dev_priv = to_i915(state->base.dev); local
133 for_each_intel_crtc(&dev_priv->drm, crtc) {
138 drm_WARN(&dev_priv
221 struct drm_i915_private *dev_priv = to_i915(state->base.dev); local
268 struct drm_i915_private *dev_priv = to_i915(state->base.dev); local
[all...]
H A Dintel_dsi.c63 struct drm_i915_private *dev_priv = to_i915(connector->dev); local
70 drm_dbg_kms(&dev_priv->drm, "\n");
79 return intel_mode_valid_max_plane_size(dev_priv, mode, false);
119 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); local
126 orientation = dev_priv->display.vbt.orientation;
H A Dintel_psr_regs.h12 #define TRANS_EXITLINE(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_EXITLINE_A)
26 #define EDP_PSR_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _SRD_CTL_A)
69 #define TRANS_PSR_IMR(tran) _MMIO_TRANS2(dev_priv, tran, _PSR_IMR_A)
70 #define TRANS_PSR_IIR(tran) _MMIO_TRANS2(dev_priv, tran, _PSR_IIR_A)
89 #define EDP_PSR_AUX_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _SRD_AUX_CTL_A)
99 #define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(dev_priv, tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */
104 #define EDP_PSR_STATUS(tran) _MMIO_TRANS2(dev_priv, tran, _SRD_STATUS_A)
129 #define EDP_PSR_PERF_CNT(tran) _MMIO_TRANS2(dev_priv, tran, _SRD_PERF_CNT_A)
136 #define EDP_PSR_DEBUG(tran) _MMIO_TRANS2(dev_priv, tran, _SRD_DEBUG_A)
156 #define EDP_PSR2_CTL(tran) _MMIO_TRANS2(dev_priv, tra
[all...]
H A Dintel_dsb.c359 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); local
364 if (drm_WARN_ON(&dev_priv->drm, !IS_ALIGNED(tail, CACHELINE_BYTES)))
367 if (is_dsb_busy(dev_priv, pipe, dsb->id)) {
368 drm_err(&dev_priv->drm, "[CRTC:%d:%s] DSB %d is busy\n",
373 intel_de_write_fw(dev_priv, DSB_CTRL(pipe, dsb->id),
376 intel_de_write_fw(dev_priv, DSB_CHICKEN(pipe, dsb->id),
379 intel_de_write_fw(dev_priv, DSB_HEAD(pipe, dsb->id),
387 intel_de_write_fw(dev_priv, DSB_PMCTRL(pipe, dsb->id),
396 intel_de_write_fw(dev_priv, DSB_PMCTRL_2(pipe, dsb->id),
401 intel_de_write_fw(dev_priv, DSB_TAI
423 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); local
[all...]
/linux-master/drivers/gpu/drm/i915/
H A Dvlv_suspend.c348 static void vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv, argument
364 if (vlv_wait_for_pw_status(dev_priv, mask, val))
365 drm_dbg(&dev_priv->drm,
381 int vlv_suspend_complete(struct drm_i915_private *dev_priv) argument
386 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
393 vlv_wait_for_gt_wells(dev_priv, false);
396 drm_WARN_ON(&dev_priv->drm,
397 (intel_uncore_read(&dev_priv->uncore, VLV_GTLC_WAKE_CTRL) & mask) != mask);
399 vlv_check_no_gt_access(dev_priv);
426 vlv_resume_prepare(struct drm_i915_private *dev_priv, bool rpm_resume) argument
[all...]
H A Di915_debugfs.c329 struct drm_i915_private *dev_priv = node_to_i915(m->private); local
330 struct intel_uncore *uncore = &dev_priv->uncore;
334 swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_x));
336 swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_y));
338 if (dev_priv->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES)
342 if (GRAPHICS_VER(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv))
345 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
347 if (IS_GRAPHICS_VER(dev_priv, 3, 4)) {
356 } else if (GRAPHICS_VER(dev_priv) >
382 struct drm_i915_private *dev_priv = node_to_i915(m->private); local
413 struct drm_i915_private *dev_priv = node_to_i915(m->private); local
733 i915_debugfs_register(struct drm_i915_private *dev_priv) argument
[all...]
H A Di915_gem.c1144 int i915_gem_init(struct drm_i915_private *dev_priv) argument
1164 if (intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv))
1165 RUNTIME_INFO(dev_priv)->page_sizes = I915_GTT_PAGE_SIZE_4K;
1167 for_each_gt(gt, dev_priv, i) {
1170 if (GRAPHICS_VER(dev_priv) >= 8)
1174 ret = i915_init_ggtt(dev_priv);
1189 intel_clock_gating_init(dev_priv);
1191 for_each_gt(gt, dev_priv, i) {
1202 intel_engines_driver_register(dev_priv);
1258 i915_gem_driver_remove(struct drm_i915_private *dev_priv) argument
1272 i915_gem_driver_release(struct drm_i915_private *dev_priv) argument
1300 i915_gem_init_early(struct drm_i915_private *dev_priv) argument
1306 i915_gem_cleanup_early(struct drm_i915_private *dev_priv) argument
[all...]
/linux-master/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_cotable.c184 struct vmw_private *dev_priv = res->dev_priv; local
194 cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
207 vmw_cmd_commit_flush(dev_priv, sizeof(*cmd));
259 struct vmw_private *dev_priv = res->dev_priv; local
275 co_info[vcotbl->type].unbind_func(dev_priv,
282 cmd1 = VMW_CMD_RESERVE(dev_priv, submit_size);
302 vmw_cmd_commit_flush(dev_priv, submit_size);
326 struct vmw_private *dev_priv local
359 struct vmw_private *dev_priv = res->dev_priv; local
402 struct vmw_private *dev_priv = res->dev_priv; local
599 vmw_cotable_alloc(struct vmw_private *dev_priv, struct vmw_resource *ctx, u32 type) argument
[all...]
H A Dvmwgfx_surface.c360 struct vmw_private *dev_priv = res->dev_priv; local
370 cmd = VMW_CMD_RESERVE(dev_priv, vmw_surface_destroy_size());
375 vmw_cmd_commit(dev_priv, vmw_surface_destroy_size());
379 * to avoid taking dev_priv::cmdbuf_mutex in
383 mutex_lock(&dev_priv->cmdbuf_mutex);
384 dev_priv->used_memory_size -= res->guest_memory_size;
385 mutex_unlock(&dev_priv->cmdbuf_mutex);
404 struct vmw_private *dev_priv = res->dev_priv; local
486 struct vmw_private *dev_priv = res->dev_priv; local
566 struct vmw_private *dev_priv = res->dev_priv; local
609 vmw_surface_init(struct vmw_private *dev_priv, struct vmw_surface *srf, void (*res_free) (struct vmw_resource *res)) argument
720 struct vmw_private *dev_priv = vmw_priv(dev); local
897 vmw_surface_handle_reference(struct vmw_private *dev_priv, struct drm_file *file_priv, uint32_t u_handle, enum drm_vmw_handle_type handle_type, struct ttm_base_object **base_p) argument
982 struct vmw_private *dev_priv = vmw_priv(dev); local
1033 struct vmw_private *dev_priv = res->dev_priv; local
1171 struct vmw_private *dev_priv = res->dev_priv; local
1217 struct vmw_private *dev_priv = res->dev_priv; local
1282 struct vmw_private *dev_priv = res->dev_priv; local
1423 struct vmw_private *dev_priv = vmw_priv(dev); local
1593 struct vmw_private *dev_priv = vmw_priv(dev); local
1826 struct vmw_private *dev_priv = res->dev_priv; local
1966 struct vmw_private *dev_priv = res->dev_priv; local
1998 vmw_gb_surface_define(struct vmw_private *dev_priv, const struct vmw_surface_metadata *req, struct vmw_surface **srf_out) argument
[all...]
H A Dvmwgfx_kms.h41 * @dev_priv: Device private.
124 struct vmw_private *dev_priv; member in struct:vmw_du_update_plane
165 * @dev_priv: Pointer to the device private. Set up by the helper.
188 struct vmw_private *dev_priv; member in struct:vmw_kms_dirty
434 int vmw_kms_helper_dirty(struct vmw_private *dev_priv,
446 void vmw_kms_helper_validation_finish(struct vmw_private *dev_priv,
452 int vmw_kms_readback(struct vmw_private *dev_priv,
459 vmw_kms_new_framebuffer(struct vmw_private *dev_priv,
465 void vmw_kms_update_implicit_fb(struct vmw_private *dev_priv);
466 void vmw_kms_create_implicit_placement_property(struct vmw_private *dev_priv);
[all...]
H A Dvmwgfx_scrn.c118 static int vmw_sou_fifo_create(struct vmw_private *dev_priv, argument
135 cmd = VMW_CMD_RESERVE(dev_priv, fifo_size);
156 vmw_cmd_commit(dev_priv, fifo_size);
166 static int vmw_sou_fifo_destroy(struct vmw_private *dev_priv, argument
184 cmd = VMW_CMD_RESERVE(dev_priv, fifo_size);
192 vmw_cmd_commit(dev_priv, fifo_size);
195 ret = vmw_fallback_wait(dev_priv, false, true, 0, false, 3*HZ);
214 struct vmw_private *dev_priv; local
223 dev_priv = vmw_priv(crtc->dev);
231 ret = vmw_sou_fifo_destroy(dev_priv, so
281 struct vmw_private *dev_priv; local
406 struct vmw_private *dev_priv; local
528 vmw_sou_plane_update_bo(struct vmw_private *dev_priv, struct drm_plane *plane, struct drm_plane_state *old_state, struct vmw_framebuffer *vfb, struct vmw_fence_obj **out_fence) argument
688 vmw_sou_plane_update_surface(struct vmw_private *dev_priv, struct drm_plane *plane, struct drm_plane_state *old_state, struct vmw_framebuffer *vfb, struct vmw_fence_obj **out_fence) argument
727 struct vmw_private *dev_priv = vmw_priv(crtc->dev); local
798 vmw_sou_init(struct vmw_private *dev_priv, unsigned unit) argument
919 vmw_kms_sou_init_display(struct vmw_private *dev_priv) argument
942 do_bo_define_gmrfb(struct vmw_private *dev_priv, struct vmw_framebuffer *framebuffer) argument
1089 vmw_kms_sou_do_surface_dirty(struct vmw_private *dev_priv, struct vmw_framebuffer *framebuffer, struct drm_clip_rect *clips, struct drm_vmw_rect *vclips, struct vmw_resource *srf, s32 dest_x, s32 dest_y, unsigned num_clips, int inc, struct vmw_fence_obj **out_fence, struct drm_crtc *crtc) argument
1205 vmw_kms_sou_do_bo_dirty(struct vmw_private *dev_priv, struct vmw_framebuffer *framebuffer, struct drm_clip_rect *clips, struct drm_vmw_rect *vclips, unsigned num_clips, int increment, bool interruptible, struct vmw_fence_obj **out_fence, struct drm_crtc *crtc) argument
1315 vmw_kms_sou_readback(struct vmw_private *dev_priv, struct drm_file *file_priv, struct vmw_framebuffer *vfb, struct drm_vmw_fence_rep __user *user_fence_rep, struct drm_vmw_rect *vclips, uint32_t num_clips, struct drm_crtc *crtc) argument
[all...]
H A Dvmwgfx_ttm_buffer.c137 struct device *dev = vmw_tt->dev_priv->drm.dev;
158 struct device *dev = vmw_tt->dev_priv->drm.dev;
175 struct vmw_private *dev_priv = vmw_tt->dev_priv; local
182 vsgt->mode = dev_priv->map_mode;
188 switch (dev_priv->map_mode) {
198 dma_get_max_seg_size(dev_priv->drm.dev),
217 drm_warn(&dev_priv->drm, "VSG table map failed!");
235 struct vmw_private *dev_priv = vmw_tt->dev_priv; local
440 struct vmw_private *dev_priv = vmw_priv_from_ttm(bdev); local
560 vmw_bo_create_and_populate(struct vmw_private *dev_priv, size_t bo_size, u32 domain, struct vmw_bo **bo_p) argument
[all...]
H A Dvmwgfx_stdu.c153 * @dev_priv: VMW DRM device
165 static int vmw_stdu_define_st(struct vmw_private *dev_priv, argument
175 cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
193 vmw_cmd_commit(dev_priv, sizeof(*cmd));
207 * @dev_priv: VMW DRM device
215 static int vmw_stdu_bind_st(struct vmw_private *dev_priv, argument
236 cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
246 vmw_cmd_commit(dev_priv, sizeof(*cmd));
280 * @dev_priv: VMW DRM device
290 static int vmw_stdu_update_st(struct vmw_private *dev_priv, argument
324 vmw_stdu_destroy_st(struct vmw_private *dev_priv, struct vmw_screen_target_display_unit *stdu) argument
373 struct vmw_private *dev_priv; local
415 struct vmw_private *dev_priv; local
541 vmw_kms_stdu_readback(struct vmw_private *dev_priv, struct drm_file *file_priv, struct vmw_framebuffer *vfb, struct drm_vmw_fence_rep __user *user_fence_rep, struct drm_clip_rect *clips, struct drm_vmw_rect *vclips, uint32_t num_clips, int increment, struct drm_crtc *crtc) argument
708 vmw_kms_stdu_surface_dirty(struct vmw_private *dev_priv, struct vmw_framebuffer *framebuffer, struct drm_clip_rect *clips, struct drm_vmw_rect *vclips, struct vmw_resource *srf, s32 dest_x, s32 dest_y, unsigned num_clips, int inc, struct vmw_fence_obj **out_fence, struct drm_crtc *crtc) argument
902 struct vmw_private *dev_priv = vmw_priv(plane->dev); local
1141 vmw_stdu_plane_update_bo(struct vmw_private *dev_priv, struct drm_plane *plane, struct drm_plane_state *old_state, struct vmw_framebuffer *vfb, struct vmw_fence_obj **out_fence) argument
1304 vmw_stdu_plane_update_surface(struct vmw_private *dev_priv, struct drm_plane *plane, struct drm_plane_state *old_state, struct vmw_framebuffer *vfb, struct vmw_fence_obj **out_fence) argument
1364 struct vmw_private *dev_priv; local
1487 vmw_stdu_init(struct vmw_private *dev_priv, unsigned unit) argument
1639 vmw_kms_stdu_init_display(struct vmw_private *dev_priv) argument
[all...]
H A Dvmwgfx_msg.c805 * @dev_priv: Identifies the drm private device.
809 int vmw_mksstat_get_kern_slot(pid_t pid, struct vmw_private *dev_priv) argument
814 for (i = 0; i < ARRAY_SIZE(dev_priv->mksstat_kern_pids); ++i) {
815 const size_t slot = (i + base) % ARRAY_SIZE(dev_priv->mksstat_kern_pids);
818 if (pid == (pid_t)atomic_read(&dev_priv->mksstat_kern_pids[slot]))
822 if (!atomic_cmpxchg(&dev_priv->mksstat_kern_pids[slot], 0, MKSSTAT_PID_RESERVED)) {
823 const int ret = mksstat_init_kern_id(&dev_priv->mksstat_kern_pages[slot]);
827 dev_priv->mksstat_kern_top_timer[slot] = MKSSTAT_KERN_COUNT;
829 atomic_set(&dev_priv->mksstat_kern_pids[slot], pid);
833 atomic_set(&dev_priv
881 vmw_mksstat_remove_all(struct vmw_private *dev_priv) argument
968 struct vmw_private *const dev_priv = vmw_priv(dev); local
991 struct vmw_private *const dev_priv = vmw_priv(dev); local
1150 struct vmw_private *const dev_priv = vmw_priv(dev); local
[all...]
H A Dvmwgfx_cmdbuf.c74 * @dev_priv: Pointer to the device private struct. Immutable.
115 struct vmw_private *dev_priv; member in struct:vmw_cmdbuf_man
307 vmw_write(man->dev_priv, SVGA_REG_COMMAND_HIGH, val);
311 vmw_write(man->dev_priv, SVGA_REG_COMMAND_LOW, val);
446 vmw_generic_waiter_remove(man->dev_priv,
448 &man->dev_priv->cmdbuf_waiters);
451 vmw_generic_waiter_add(man->dev_priv,
453 &man->dev_priv->cmdbuf_waiters);
613 vmw_cmd_send_fence(man->dev_priv, &dummy);
724 vmw_generic_waiter_add(man->dev_priv,
1222 struct vmw_private *dev_priv = man->dev_priv; local
1289 vmw_cmdbuf_man_create(struct vmw_private *dev_priv) argument
[all...]
/linux-master/drivers/mtd/hyperbus/
H A Dhbmc-am654.c162 struct am654_hbmc_device_priv *dev_priv; local
202 dev_priv = devm_kzalloc(dev, sizeof(*dev_priv), GFP_KERNEL);
203 if (!dev_priv) {
208 priv->hbdev.priv = dev_priv;
209 dev_priv->device_base = res.start;
210 dev_priv->ctlr = &priv->ctlr;
212 ret = am654_hbmc_request_mmap_dma(dev_priv);
224 if (dev_priv->rx_chan)
225 dma_release_channel(dev_priv
235 struct am654_hbmc_device_priv *dev_priv = priv->hbdev.priv; local
[all...]
/linux-master/drivers/gpu/drm/i915/soc/
H A Dintel_dram.c46 static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv) argument
50 tmp = intel_uncore_read(&dev_priv->uncore, CLKCFG);
54 dev_priv->fsb_freq = 533; /* 133*4 */
57 dev_priv->fsb_freq = 800; /* 200*4 */
60 dev_priv->fsb_freq = 667; /* 167*4 */
63 dev_priv->fsb_freq = 400; /* 100*4 */
69 dev_priv->mem_freq = 533;
72 dev_priv->mem_freq = 667;
75 dev_priv->mem_freq = 800;
80 tmp = intel_uncore_read(&dev_priv
84 ilk_detect_mem_freq(struct drm_i915_private *dev_priv) argument
540 icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv) argument
[all...]

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