1/* SPDX-License-Identifier: MIT */ 2/* 3 * Copyright �� 2023 Intel Corporation 4 */ 5 6#ifndef __INTEL_PSR_REGS_H__ 7#define __INTEL_PSR_REGS_H__ 8 9#include "intel_display_reg_defs.h" 10#include "intel_dp_aux_regs.h" 11 12#define TRANS_EXITLINE(trans) _MMIO_TRANS2((trans), _TRANS_EXITLINE_A) 13#define EXITLINE_ENABLE REG_BIT(31) 14#define EXITLINE_MASK REG_GENMASK(12, 0) 15#define EXITLINE_SHIFT 0 16 17/* 18 * HSW+ eDP PSR registers 19 * 20 * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one 21 * instance of it 22 */ 23#define HSW_SRD_CTL _MMIO(0x64800) 24#define _SRD_CTL_A 0x60800 25#define _SRD_CTL_EDP 0x6f800 26#define EDP_PSR_CTL(tran) _MMIO_TRANS2(tran, _SRD_CTL_A) 27#define EDP_PSR_ENABLE REG_BIT(31) 28#define BDW_PSR_SINGLE_FRAME REG_BIT(30) 29#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK REG_BIT(29) /* SW can't modify */ 30#define EDP_PSR_LINK_STANDBY REG_BIT(27) 31#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK REG_GENMASK(26, 25) 32#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 0) 33#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 1) 34#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 2) 35#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES REG_FIELD_PREP(EDP_PSR_MIN_LINK_ENTRY_TIME_MASK, 3) 36#define EDP_PSR_MAX_SLEEP_TIME_MASK REG_GENMASK(24, 20) 37#define EDP_PSR_MAX_SLEEP_TIME(x) REG_FIELD_PREP(EDP_PSR_MAX_SLEEP_TIME_MASK, (x)) 38#define LNL_EDP_PSR_ENTRY_SETUP_FRAMES_MASK REG_GENMASK(17, 16) 39#define LNL_EDP_PSR_ENTRY_SETUP_FRAMES(x) REG_FIELD_PREP(LNL_EDP_PSR_ENTRY_SETUP_FRAMES_MASK, (x)) 40#define EDP_PSR_SKIP_AUX_EXIT REG_BIT(12) 41#define EDP_PSR_TP_MASK REG_BIT(11) 42#define EDP_PSR_TP_TP1_TP2 REG_FIELD_PREP(EDP_PSR_TP_MASK, 0) 43#define EDP_PSR_TP_TP1_TP3 REG_FIELD_PREP(EDP_PSR_TP_MASK, 1) 44#define EDP_PSR_CRC_ENABLE REG_BIT(10) /* BDW+ */ 45#define EDP_PSR_TP2_TP3_TIME_MASK REG_GENMASK(9, 8) 46#define EDP_PSR_TP2_TP3_TIME_500us REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 0) 47#define EDP_PSR_TP2_TP3_TIME_100us REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 1) 48#define EDP_PSR_TP2_TP3_TIME_2500us REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 2) 49#define EDP_PSR_TP2_TP3_TIME_0us REG_FIELD_PREP(EDP_PSR_TP2_TP3_TIME_MASK, 3) 50#define EDP_PSR_TP4_TIME_MASK REG_GENMASK(7, 6) 51#define EDP_PSR_TP4_TIME_0us REG_FIELD_PREP(EDP_PSR_TP4_TIME_MASK, 3) /* ICL+ */ 52#define EDP_PSR_TP1_TIME_MASK REG_GENMASK(5, 4) 53#define EDP_PSR_TP1_TIME_500us REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 0) 54#define EDP_PSR_TP1_TIME_100us REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 1) 55#define EDP_PSR_TP1_TIME_2500us REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 2) 56#define EDP_PSR_TP1_TIME_0us REG_FIELD_PREP(EDP_PSR_TP1_TIME_MASK, 3) 57#define EDP_PSR_IDLE_FRAMES_MASK REG_GENMASK(3, 0) 58#define EDP_PSR_IDLE_FRAMES(x) REG_FIELD_PREP(EDP_PSR_IDLE_FRAMES_MASK, (x)) 59 60/* 61 * Until TGL, IMR/IIR are fixed at 0x648xx. On TGL+ those registers are relative 62 * to transcoder and bits defined for each one as if using no shift (i.e. as if 63 * it was for TRANSCODER_EDP) 64 */ 65#define EDP_PSR_IMR _MMIO(0x64834) 66#define EDP_PSR_IIR _MMIO(0x64838) 67#define _PSR_IMR_A 0x60814 68#define _PSR_IIR_A 0x60818 69#define TRANS_PSR_IMR(tran) _MMIO_TRANS2(tran, _PSR_IMR_A) 70#define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A) 71#define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \ 72 0 : ((trans) - TRANSCODER_A + 1) * 8) 73#define TGL_PSR_MASK REG_GENMASK(2, 0) 74#define TGL_PSR_ERROR REG_BIT(2) 75#define TGL_PSR_POST_EXIT REG_BIT(1) 76#define TGL_PSR_PRE_ENTRY REG_BIT(0) 77#define EDP_PSR_MASK(trans) (TGL_PSR_MASK << \ 78 _EDP_PSR_TRANS_SHIFT(trans)) 79#define EDP_PSR_ERROR(trans) (TGL_PSR_ERROR << \ 80 _EDP_PSR_TRANS_SHIFT(trans)) 81#define EDP_PSR_POST_EXIT(trans) (TGL_PSR_POST_EXIT << \ 82 _EDP_PSR_TRANS_SHIFT(trans)) 83#define EDP_PSR_PRE_ENTRY(trans) (TGL_PSR_PRE_ENTRY << \ 84 _EDP_PSR_TRANS_SHIFT(trans)) 85 86#define HSW_SRD_AUX_CTL _MMIO(0x64810) 87#define _SRD_AUX_CTL_A 0x60810 88#define _SRD_AUX_CTL_EDP 0x6f810 89#define EDP_PSR_AUX_CTL(tran) _MMIO_TRANS2(tran, _SRD_AUX_CTL_A) 90#define EDP_PSR_AUX_CTL_TIME_OUT_MASK DP_AUX_CH_CTL_TIME_OUT_MASK 91#define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK DP_AUX_CH_CTL_MESSAGE_SIZE_MASK 92#define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK DP_AUX_CH_CTL_PRECHARGE_2US_MASK 93#define EDP_PSR_AUX_CTL_ERROR_INTERRUPT REG_BIT(11) 94#define EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK 95 96#define HSW_SRD_AUX_DATA(i) _MMIO(0x64814 + (i) * 4) /* 5 registers */ 97#define _SRD_AUX_DATA_A 0x60814 98#define _SRD_AUX_DATA_EDP 0x6f814 99#define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */ 100 101#define HSW_SRD_STATUS _MMIO(0x64840) 102#define _SRD_STATUS_A 0x60840 103#define _SRD_STATUS_EDP 0x6f840 104#define EDP_PSR_STATUS(tran) _MMIO_TRANS2(tran, _SRD_STATUS_A) 105#define EDP_PSR_STATUS_STATE_MASK REG_GENMASK(31, 29) 106#define EDP_PSR_STATUS_STATE_IDLE REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 0) 107#define EDP_PSR_STATUS_STATE_SRDONACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 1) 108#define EDP_PSR_STATUS_STATE_SRDENT REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 2) 109#define EDP_PSR_STATUS_STATE_BUFOFF REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 3) 110#define EDP_PSR_STATUS_STATE_BUFON REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 4) 111#define EDP_PSR_STATUS_STATE_AUXACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 5) 112#define EDP_PSR_STATUS_STATE_SRDOFFACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 6) 113#define EDP_PSR_STATUS_LINK_MASK REG_GENMASK(27, 26) 114#define EDP_PSR_STATUS_LINK_FULL_OFF REG_FIELD_PREP(EDP_PSR_STATUS_LINK_MASK, 0) 115#define EDP_PSR_STATUS_LINK_FULL_ON REG_FIELD_PREP(EDP_PSR_STATUS_LINK_MASK, 1) 116#define EDP_PSR_STATUS_LINK_STANDBY REG_FIELD_PREP(EDP_PSR_STATUS_LINK_MASK, 2) 117#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK REG_GENMASK(24, 20) 118#define EDP_PSR_STATUS_COUNT_MASK REG_GENMASK(19, 16) 119#define EDP_PSR_STATUS_AUX_ERROR REG_BIT(15) 120#define EDP_PSR_STATUS_AUX_SENDING REG_BIT(12) 121#define EDP_PSR_STATUS_SENDING_IDLE REG_BIT(9) 122#define EDP_PSR_STATUS_SENDING_TP2_TP3 REG_BIT(8) 123#define EDP_PSR_STATUS_SENDING_TP1 REG_BIT(4) 124#define EDP_PSR_STATUS_IDLE_MASK REG_GENMASK(3, 0) 125 126#define HSW_SRD_PERF_CNT _MMIO(0x64844) 127#define _SRD_PERF_CNT_A 0x60844 128#define _SRD_PERF_CNT_EDP 0x6f844 129#define EDP_PSR_PERF_CNT(tran) _MMIO_TRANS2(tran, _SRD_PERF_CNT_A) 130#define EDP_PSR_PERF_CNT_MASK REG_GENMASK(23, 0) 131 132/* PSR_MASK on SKL+ */ 133#define HSW_SRD_DEBUG _MMIO(0x64860) 134#define _SRD_DEBUG_A 0x60860 135#define _SRD_DEBUG_EDP 0x6f860 136#define EDP_PSR_DEBUG(tran) _MMIO_TRANS2(tran, _SRD_DEBUG_A) 137#define EDP_PSR_DEBUG_MASK_MAX_SLEEP REG_BIT(28) 138#define EDP_PSR_DEBUG_MASK_LPSP REG_BIT(27) 139#define EDP_PSR_DEBUG_MASK_MEMUP REG_BIT(26) 140#define EDP_PSR_DEBUG_MASK_HPD REG_BIT(25) 141#define EDP_PSR_DEBUG_MASK_FBC_MODIFY REG_BIT(24) 142#define EDP_PSR_DEBUG_MASK_PRIMARY_FLIP REG_BIT(23) /* hsw */ 143#define EDP_PSR_DEBUG_MASK_HDCP_ENABLE REG_BIT(22) /* hsw/bdw */ 144#define EDP_PSR_DEBUG_MASK_SPRITE_ENABLE REG_BIT(21) /* hsw */ 145#define EDP_PSR_DEBUG_MASK_CURSOR_MOVE REG_BIT(20) /* hsw */ 146#define EDP_PSR_DEBUG_MASK_VBLANK_VSYNC_INT REG_BIT(19) /* hsw */ 147#define EDP_PSR_DEBUG_MASK_DPST_PHASE_IN REG_BIT(18) /* hsw */ 148#define EDP_PSR_DEBUG_MASK_KVMR_SESSION_EN REG_BIT(17) 149#define EDP_PSR_DEBUG_MASK_DISP_REG_WRITE REG_BIT(16) /* hsw-skl */ 150#define EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN REG_BIT(15) /* skl+ */ 151#define EDP_PSR_DEBUG_RFB_UPDATE_SENT REG_BIT(2) /* bdw */ 152#define EDP_PSR_DEBUG_ENTRY_COMPLETION REG_BIT(1) /* hsw/bdw */ 153 154#define _PSR2_CTL_A 0x60900 155#define _PSR2_CTL_EDP 0x6f900 156#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) 157#define EDP_PSR2_ENABLE REG_BIT(31) 158#define EDP_SU_TRACK_ENABLE REG_BIT(30) /* up to adl-p */ 159#define TGL_EDP_PSR2_BLOCK_COUNT_MASK REG_BIT(28) 160#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_2 REG_FIELD_PREP(TGL_EDP_PSR2_BLOCK_COUNT_MASK, 0) 161#define TGL_EDP_PSR2_BLOCK_COUNT_NUM_3 REG_FIELD_PREP(TGL_EDP_PSR2_BLOCK_COUNT_MASK, 1) 162#define LNL_EDP_PSR2_SU_REGION_ET_ENABLE REG_BIT(27) 163#define EDP_Y_COORDINATE_ENABLE REG_BIT(25) /* display 10, 11 and 12 */ 164#define EDP_PSR2_SU_SDP_SCANLINE REG_BIT(25) /* display 13+ */ 165#define EDP_MAX_SU_DISABLE_TIME_MASK REG_GENMASK(24, 20) 166#define EDP_MAX_SU_DISABLE_TIME(t) REG_FIELD_PREP(EDP_MAX_SU_DISABLE_TIME, (t)) 167#define EDP_PSR2_IO_BUFFER_WAKE_MASK REG_GENMASK(14, 13) 168#define EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES 8 169#define EDP_PSR2_IO_BUFFER_WAKE(lines) REG_FIELD_PREP(EDP_PSR2_IO_BUFFER_WAKE_MASK, \ 170 EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) 171#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK REG_GENMASK(15, 13) 172#define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5 173#define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) REG_FIELD_PREP(TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK, \ 174 (lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) 175#define EDP_PSR2_FAST_WAKE_MASK REG_GENMASK(12, 11) 176#define EDP_PSR2_FAST_WAKE_MAX_LINES 8 177#define EDP_PSR2_FAST_WAKE(lines) REG_FIELD_PREP(EDP_PSR2_FAST_WAKE_MASK, \ 178 EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) 179#define TGL_EDP_PSR2_FAST_WAKE_MASK REG_GENMASK(12, 10) 180#define TGL_EDP_PSR2_FAST_WAKE_MIN_LINES 5 181#define TGL_EDP_PSR2_FAST_WAKE(lines) REG_FIELD_PREP(TGL_EDP_PSR2_FAST_WAKE_MASK, \ 182 (lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) 183#define EDP_PSR2_TP2_TIME_MASK REG_GENMASK(9, 8) 184#define EDP_PSR2_TP2_TIME_500us REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 0) 185#define EDP_PSR2_TP2_TIME_100us REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 1) 186#define EDP_PSR2_TP2_TIME_2500us REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 2) 187#define EDP_PSR2_TP2_TIME_50us REG_FIELD_PREP(EDP_PSR2_TP2_TIME_MASK, 3) 188#define EDP_PSR2_FRAME_BEFORE_SU_MASK REG_GENMASK(7, 4) 189#define EDP_PSR2_FRAME_BEFORE_SU(a) REG_FIELD_PREP(EDP_PSR2_FRAME_BEFORE_SU_MASK, (a)) 190#define EDP_PSR2_IDLE_FRAMES_MASK REG_GENMASK(3, 0) 191#define EDP_PSR2_IDLE_FRAMES(x) REG_FIELD_PREP(EDP_PSR2_IDLE_FRAMES_MASK, (x)) 192 193#define _PSR_EVENT_TRANS_A 0x60848 194#define _PSR_EVENT_TRANS_B 0x61848 195#define _PSR_EVENT_TRANS_C 0x62848 196#define _PSR_EVENT_TRANS_D 0x63848 197#define _PSR_EVENT_TRANS_EDP 0x6f848 198#define PSR_EVENT(tran) _MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A) 199#define PSR_EVENT_PSR2_WD_TIMER_EXPIRE REG_BIT(17) 200#define PSR_EVENT_PSR2_DISABLED REG_BIT(16) 201#define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN REG_BIT(15) 202#define PSR_EVENT_SU_CRC_FIFO_UNDERRUN REG_BIT(14) 203#define PSR_EVENT_GRAPHICS_RESET REG_BIT(12) 204#define PSR_EVENT_PCH_INTERRUPT REG_BIT(11) 205#define PSR_EVENT_MEMORY_UP REG_BIT(10) 206#define PSR_EVENT_FRONT_BUFFER_MODIFY REG_BIT(9) 207#define PSR_EVENT_WD_TIMER_EXPIRE REG_BIT(8) 208#define PSR_EVENT_PIPE_REGISTERS_UPDATE REG_BIT(6) 209#define PSR_EVENT_REGISTER_UPDATE REG_BIT(5) /* Reserved in ICL+ */ 210#define PSR_EVENT_HDCP_ENABLE REG_BIT(4) 211#define PSR_EVENT_KVMR_SESSION_ENABLE REG_BIT(3) 212#define PSR_EVENT_VBI_ENABLE REG_BIT(2) 213#define PSR_EVENT_LPSP_MODE_EXIT REG_BIT(1) 214#define PSR_EVENT_PSR_DISABLE REG_BIT(0) 215 216#define _PSR2_STATUS_A 0x60940 217#define _PSR2_STATUS_EDP 0x6f940 218#define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(tran, _PSR2_STATUS_A) 219#define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28) 220#define EDP_PSR2_STATUS_STATE_DEEP_SLEEP REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8) 221 222#define _PSR2_SU_STATUS_A 0x60914 223#define _PSR2_SU_STATUS_EDP 0x6f914 224#define _PSR2_SU_STATUS(tran, index) _MMIO_TRANS2(tran, _PSR2_SU_STATUS_A + (index) * 4) 225#define PSR2_SU_STATUS(tran, frame) (_PSR2_SU_STATUS(tran, (frame) / 3)) 226#define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10) 227#define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame)) 228#define PSR2_SU_STATUS_FRAMES 8 229 230#define _PSR2_MAN_TRK_CTL_A 0x60910 231#define _PSR2_MAN_TRK_CTL_EDP 0x6f910 232#define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A) 233#define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31) 234#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21) 235#define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) 236#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(20, 11) 237#define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) 238#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3) 239#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2) 240#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1) 241#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16) 242#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) 243#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0) 244#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK, val) 245#define ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31) 246#define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(14) 247#define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(13) 248 249/* PSR2 Early transport */ 250#define _PIPE_SRCSZ_ERLY_TPT_A 0x70074 251 252#define PIPE_SRCSZ_ERLY_TPT(trans) _MMIO_TRANS2(trans, _PIPE_SRCSZ_ERLY_TPT_A) 253 254#define _SEL_FETCH_PLANE_BASE_1_A 0x70890 255#define _SEL_FETCH_PLANE_BASE_2_A 0x708B0 256#define _SEL_FETCH_PLANE_BASE_3_A 0x708D0 257#define _SEL_FETCH_PLANE_BASE_4_A 0x708F0 258#define _SEL_FETCH_PLANE_BASE_5_A 0x70920 259#define _SEL_FETCH_PLANE_BASE_6_A 0x70940 260#define _SEL_FETCH_PLANE_BASE_7_A 0x70960 261#define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880 262#define _SEL_FETCH_PLANE_BASE_1_B 0x71890 263 264#define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \ 265 _SEL_FETCH_PLANE_BASE_1_A, \ 266 _SEL_FETCH_PLANE_BASE_2_A, \ 267 _SEL_FETCH_PLANE_BASE_3_A, \ 268 _SEL_FETCH_PLANE_BASE_4_A, \ 269 _SEL_FETCH_PLANE_BASE_5_A, \ 270 _SEL_FETCH_PLANE_BASE_6_A, \ 271 _SEL_FETCH_PLANE_BASE_7_A, \ 272 _SEL_FETCH_PLANE_BASE_CUR_A) 273#define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B) 274#define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \ 275 _SEL_FETCH_PLANE_BASE_1_A + \ 276 _SEL_FETCH_PLANE_BASE_A(plane)) 277 278#define _SEL_FETCH_PLANE_CTL_1_A 0x70890 279#define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 280 _SEL_FETCH_PLANE_CTL_1_A - \ 281 _SEL_FETCH_PLANE_BASE_1_A) 282#define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31) 283 284#define _SEL_FETCH_PLANE_POS_1_A 0x70894 285#define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 286 _SEL_FETCH_PLANE_POS_1_A - \ 287 _SEL_FETCH_PLANE_BASE_1_A) 288 289#define _SEL_FETCH_PLANE_SIZE_1_A 0x70898 290#define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 291 _SEL_FETCH_PLANE_SIZE_1_A - \ 292 _SEL_FETCH_PLANE_BASE_1_A) 293 294#define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C 295#define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ 296 _SEL_FETCH_PLANE_OFFSET_1_A - \ 297 _SEL_FETCH_PLANE_BASE_1_A) 298 299#define _ALPM_CTL_A 0x60950 300#define ALPM_CTL(tran) _MMIO_TRANS2(tran, _ALPM_CTL_A) 301#define ALPM_CTL_ALPM_ENABLE REG_BIT(31) 302#define ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(30) 303#define ALPM_CTL_LOBF_ENABLE REG_BIT(29) 304#define ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE REG_BIT(28) 305#define ALPM_CTL_KEEP_FEC_ENABLE_FOR_AUX_WAKE_SLEEP REG_BIT(27) 306#define ALPM_CTL_RESTORE_OCCURED REG_BIT(26) 307#define ALPM_CTL_RESTORE_TO_SLEEP REG_BIT(25) 308#define ALPM_CTL_RESTORE_TO_DEEP_SLEEP REG_BIT(24) 309#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK REG_GENMASK(23, 21) 310#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 0) 311#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_128_SYMBOLS REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 1) 312#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_256_SYMBOLS REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 2) 313#define ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_512_SYMBOLS REG_FIELD_PREP(ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_MASK, 3) 314#define ALPM_CTL_AUX_WAKE_SLEEP_HOLD_ENABLE REG_BIT(20) 315#define ALPM_CTL_ALPM_ENTRY_CHECK_MASK REG_GENMASK(19, 16) 316#define ALPM_CTL_ALPM_ENTRY_CHECK(val) REG_FIELD_PREP(ALPM_CTL_ALPM_ENTRY_CHECK_MASK, val) 317#define ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK REG_GENMASK(13, 8) 318#define ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES 5 319#define ALPM_CTL_EXTENDED_FAST_WAKE_TIME(lines) REG_FIELD_PREP(ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK, (lines) - ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES) 320#define ALPM_CTL_AUX_LESS_WAKE_TIME_MASK REG_GENMASK(5, 0) 321#define ALPM_CTL_AUX_LESS_WAKE_TIME(val) REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val) 322 323#define _ALPM_CTL2_A 0x60954 324#define ALPM_CTL2(tran) _MMIO_TRANS2(tran, _ALPM_CTL2_A) 325#define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK REG_GENMASK(28, 24) 326#define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val) REG_FIELD_PREP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, val) 327#define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK REG_GENMASK(19, 16) 328#define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION(val) REG_FIELD_PREP(ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK, val) 329#define ALPM_CTL2_NUMBER_OF_LTTPR_MASK REG_GENMASK(15, 12) 330#define ALPM_CTL2_NUMBER_OF_LTTPR(val) REG_FIELD_PREP(ALPM_CTL2_NUMBER_OF_LTTPR_MASK, val) 331#define ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME_MASK REG_GENMASK(10, 8) 332#define ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME(val) REG_FIELD_PREP(ALPM_CTL2_LTTPR_AUX_LESS_SLEEP_HOLD_TIME_MASK, val) 333#define ALPM_CTL2_FEC_DECODE_EN_POSITION_AFTER_WAKE_SR REG_BIT(4) 334#define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK REG_GENMASK(2, 0) 335#define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES(val) REG_FIELD_PREP(ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK, val) 336 337#define _PORT_ALPM_CTL_A 0x16fa2c 338#define PORT_ALPM_CTL(tran) _MMIO_TRANS2(tran, _PORT_ALPM_CTL_A) 339#define PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(31) 340#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK REG_GENMASK(23, 20) 341#define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val) 342#define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK REG_GENMASK(19, 16) 343#define PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK, val) 344#define PORT_ALPM_CTL_SILENCE_PERIOD_MASK REG_GENMASK(7, 0) 345#define PORT_ALPM_CTL_SILENCE_PERIOD(val) REG_FIELD_PREP(PORT_ALPM_CTL_SILENCE_PERIOD_MASK, val) 346 347#define _PORT_ALPM_LFPS_CTL_A 0x16fa30 348#define PORT_ALPM_LFPS_CTL(tran) _MMIO_TRANS2(tran, _PORT_ALPM_LFPS_CTL_A) 349#define PORT_ALPM_LFPS_CTL_LFPS_START_POLARITY REG_BIT(31) 350#define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK REG_GENMASK(27, 24) 351#define ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES 5 352#define ALPM_CTL_EXTENDED_FAST_WAKE_TIME(lines) REG_FIELD_PREP(ALPM_CTL_EXTENDED_FAST_WAKE_TIME_MASK, (lines) - ALPM_CTL_EXTENDED_FAST_WAKE_MIN_LINES) 353#define ALPM_CTL_AUX_LESS_WAKE_TIME_MASK REG_GENMASK(5, 0) 354#define ALPM_CTL_AUX_LESS_WAKE_TIME(val) REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val) 355 356#endif /* __INTEL_PSR_REGS_H__ */ 357