Searched refs:dc (Results 226 - 250 of 549) sorted by relevance

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/linux-master/drivers/dma/
H A Dtxx9dmac.h193 static inline bool is_dmac64(const struct txx9dmac_chan *dc) argument
195 return __is_dmac64(dc->ddev);
237 static inline bool txx9dmac_chan_INTENT(struct txx9dmac_chan *dc) argument
239 return (dc->ccr & TXX9_DMA_CCR_INTENT) != 0;
242 static inline void txx9dmac_chan_set_INTENT(struct txx9dmac_chan *dc) argument
244 dc->ccr |= TXX9_DMA_CCR_INTENT;
252 static inline void txx9dmac_chan_set_SMPCHN(struct txx9dmac_chan *dc) argument
254 dc->ccr |= TXX9_DMA_CCR_SMPCHN;
265 static inline bool txx9dmac_chan_INTENT(struct txx9dmac_chan *dc) argument
270 static void txx9dmac_chan_set_INTENT(struct txx9dmac_chan *dc) argument
283 txx9dmac_chan_set_SMPCHN(struct txx9dmac_chan *dc) argument
[all...]
/linux-master/drivers/md/bcache/
H A Dio.c56 void bch_count_backing_io_errors(struct cached_dev *dc, struct bio *bio) argument
60 WARN_ONCE(!dc, "NULL pointer of struct cached_dev");
66 * we shouldn't count failed REQ_RAHEAD bio to dc->io_errors.
70 dc->bdev);
74 errors = atomic_add_return(1, &dc->io_errors);
75 if (errors < dc->error_limit)
77 dc->bdev);
79 bch_cached_dev_error(dc);
H A Drequest.h39 void bch_cached_dev_request_init(struct cached_dev *dc);
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn31/
H A Ddcn31_resource.c28 #include "dc.h"
107 dc->ctx->logger
965 ctx->dc->caps.extended_aux_timeout_support);
1120 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1617 int dcn31x_populate_dml_pipes_from_context(struct dc *dc, argument
1627 pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1631 if (dc->debug.dml_hostvm_override == DML_HOSTVM_NO_OVERRIDE) {
1632 //pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
1633 pipes[i].pipe.src.hostvm = dc
1642 dcn31_populate_dml_pipes_from_context( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, bool fast_validate) argument
1724 dcn31_calculate_wm_and_dlg( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt, int vlevel) argument
1736 dcn31_populate_dml_writeback_from_context(struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes) argument
1746 dcn31_set_mcif_arb_params(struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt) argument
1756 dcn31_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate) argument
1871 dcn31_resource_construct( uint8_t num_virtual_links, struct dc *dc, struct dcn31_resource_pool *pool) argument
2204 dcn31_create_resource_pool( const struct dc_init_data *init_data, struct dc *dc) argument
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/linux-master/drivers/gpu/drm/amd/display/dc/link/accessories/
H A Dlink_dp_trace.c110 link->dp_trace.detect_lt_trace.timestamps.start = dm_get_timestamp(link->dc->ctx);
112 link->dp_trace.commit_lt_trace.timestamps.start = dm_get_timestamp(link->dc->ctx);
119 link->dp_trace.detect_lt_trace.timestamps.end = dm_get_timestamp(link->dc->ctx);
121 link->dp_trace.commit_lt_trace.timestamps.end = dm_get_timestamp(link->dc->ctx);
152 link->dp_trace.edp_trace_power_timestamps.poweroff = dm_get_timestamp(link->dc->ctx);
154 link->dp_trace.edp_trace_power_timestamps.poweron = dm_get_timestamp(link->dc->ctx);
169 if (link != NULL && link->dc->debug.enable_driver_sequence_debug)
/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn316/
H A Ddcn316_resource.c28 #include "dc.h"
957 ctx->dc->caps.extended_aux_timeout_support);
1112 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1612 struct dc *dc, struct dc_state *context,
1622 dcn31x_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1625 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1674 dc->config.enable_4to1MPC = false;
1675 if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1678 dc
1611 dcn316_populate_dml_pipes_from_context( struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes, bool fast_validate) argument
1725 dcn316_resource_construct( uint8_t num_virtual_links, struct dc *dc, struct dcn316_resource_pool *pool) argument
2023 dcn316_create_resource_pool( const struct dc_init_data *init_data, struct dc *dc) argument
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/linux-master/drivers/gpu/drm/amd/display/dc/inc/
H A Dlink.h33 * pointer style. This header is strictly private in dc and should never be
34 * included by DM because it exposes too much dc detail including all dc
41 * DM includes dc.h
42 * dc_link_exports.c or other dc files implement dc.h
45 * dc_link_exports.c or other dc files include link.h
52 * As you can see if you ever need to add a new dc link function and call it on
53 * DM/dc side, it is very difficult because you will need layers of translation.
54 * The most appropriate approach to implement new requirements on DM/dc sid
84 const struct dc *dc; member in struct:link_init_data
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/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/
H A Ddcn35_dccg.c52 if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp)
57 if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp)
62 if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp)
67 if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp)
116 if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp)
372 if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)
378 if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)
384 if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)
390 if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)
409 if (dccg->ctx->dc
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c6 #include "dc.h"
807 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);
837 dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);
865 ctx->dc->caps.extended_aux_timeout_support);
989 384,/*ctx->dc->dml.ip.det_buffer_size_kbytes,*/
990 8, /*ctx->dc->dml.ip.pixel_chunk_size_kbytes,*/
991 1792 /*ctx->dc->dml.ip.config_return_buffer_size_in_kbytes*/);
1103 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1574 dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);
1613 ctx->dc
1713 dcn351_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate) argument
1760 dcn351_resource_construct( uint8_t num_virtual_links, struct dc *dc, struct dcn351_resource_pool *pool) argument
2147 dcn351_create_resource_pool( const struct dc_init_data *init_data, struct dc *dc) argument
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/linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c28 #include "dc.h"
827 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dpp);
857 dcn35_opp_set_fgcg(opp, ctx->dc->debug.enable_fine_grain_clock_gating.bits.opp);
885 ctx->dc->caps.extended_aux_timeout_support);
1009 384,/*ctx->dc->dml.ip.det_buffer_size_kbytes,*/
1010 8, /*ctx->dc->dml.ip.pixel_chunk_size_kbytes,*/
1011 1792 /*ctx->dc->dml.ip.config_return_buffer_size_in_kbytes*/);
1123 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1594 dwbc30, ctx->dc->debug.enable_fine_grain_clock_gating.bits.dwb);
1633 ctx->dc
1733 dcn35_validate_bandwidth(struct dc *dc, struct dc_state *context, bool fast_validate) argument
1781 dcn35_resource_construct( uint8_t num_virtual_links, struct dc *dc, struct dcn35_resource_pool *pool) argument
2164 dcn35_create_resource_pool( const struct dc_init_data *init_data, struct dc *dc) argument
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/linux-master/drivers/video/fbdev/geode/
H A Dsuspend_gx.c31 memcpy(par->dc, par->dc_regs, sizeof(par->dc));
86 for (i = 0; i < ARRAY_SIZE(par->dc); i++) {
95 write_dc(par, i, par->dc[i] & ~(DC_GENERAL_CFG_VIDE |
103 write_dc(par, i, par->dc[i] & ~(DC_DISPLAY_CFG_VDEN |
122 write_dc(par, i, par->dc[i]);
198 write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CFG] &
201 write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG] &
225 write_dc(par, DC_DISPLAY_CFG, par->dc[DC_DISPLAY_CFG]);
227 write_dc(par, DC_GENERAL_CFG, par->dc[DC_GENERAL_CF
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/linux-master/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_detection.c206 &link->dc->res_pool->audio_support;
304 .speed = ddc->ctx->dc->caps.i2c_speed_in_khz };
585 struct audio_support *audio_support = &link->dc->res_pool->audio_support;
600 if (link->dc->debug.disable_dp_plus_plus_wa &&
693 !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around)
736 static bool should_prepare_phy_clocks_for_link_verification(const struct dc *dc, argument
742 for (i = 0; i < dc->current_state->stream_count; i++) {
743 if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {
752 static void prepare_phy_clocks_for_destructive_link_verification(const struct dc *d argument
758 restore_phy_clocks_for_destructive_link_verification(const struct dc *dc) argument
861 struct dc *dc = dc_ctx->dc; local
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/linux-master/drivers/gpu/drm/amd/display/dc/dce/
H A Ddmub_replay.c26 #include "dc.h"
71 struct dc_context *dc = dmub->ctx; local
87 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
121 struct dc_context *dc = dmub->ctx; local
130 dm_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
142 struct dc_context *dc = dmub->ctx; local
146 struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx;
199 !link->dc->debug.disable_fec) &&
202 link->dc->caps.edp_dsc_support)) &&
213 dm_execute_dmub_cmd(dc,
226 struct dc_context *dc = dmub->ctx; local
268 struct dc_context *dc = dmub->ctx; local
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H A DMakefile35 AMD_DAL_DCE = $(addprefix $(AMDDALPATH)/dc/dce/,$(DCE))
/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_dccg.c123 if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)
133 if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream)
185 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
194 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
203 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
212 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
238 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
247 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
256 if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se)
265 if (dccg->ctx->dc
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/linux-master/drivers/gpu/drm/atmel-hlcdc/
H A Datmel_hlcdc_crtc.c49 * @dc: pointer to the atmel_hlcdc structure provided by the MFD device
55 struct atmel_hlcdc_dc *dc; member in struct:atmel_hlcdc_crtc
69 struct regmap *regmap = crtc->dc->hlcdc->regmap;
100 ret = clk_prepare_enable(crtc->dc->hlcdc->sys_clk);
124 prate = clk_get_rate(crtc->dc->hlcdc->sys_clk);
126 if (!crtc->dc->desc->fixed_clksrc) {
181 clk_disable_unprepare(crtc->dc->hlcdc->sys_clk);
190 return atmel_hlcdc_dc_mode_valid(crtc->dc, mode);
198 struct regmap *regmap = crtc->dc->hlcdc->regmap;
220 clk_disable_unprepare(crtc->dc
510 struct atmel_hlcdc_dc *dc = dev->dev_private; local
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/linux-master/fs/f2fs/
H A Dsegment.c947 struct discard_cmd *dc; local
953 dc = f2fs_kmem_cache_alloc(discard_cmd_slab, GFP_NOFS, true, NULL);
954 INIT_LIST_HEAD(&dc->list);
955 dc->bdev = bdev;
956 dc->di.lstart = lstart;
957 dc->di.start = start;
958 dc->di.len = len;
959 dc->ref = 0;
960 dc->state = D_PREP;
961 dc
1006 struct discard_cmd *dc; local
1030 struct discard_cmd *dc; local
1078 __detach_discard_cmd(struct discard_cmd_control *dcc, struct discard_cmd *dc) argument
1093 __remove_discard_cmd(struct f2fs_sb_info *sbi, struct discard_cmd *dc) argument
1122 struct discard_cmd *dc = (struct discard_cmd *)bio->bi_private; local
1215 __submit_zone_reset_cmd(struct f2fs_sb_info *sbi, struct discard_cmd *dc, blk_opf_t flag, struct list_head *wait_list, unsigned int *issued) argument
1253 __submit_discard_cmd(struct f2fs_sb_info *sbi, struct discard_policy *dpolicy, struct discard_cmd *dc, int *issued) argument
1380 struct discard_cmd *dc; local
1405 __relocate_discard_cmd(struct discard_cmd_control *dcc, struct discard_cmd *dc) argument
1411 __punch_discard_cmd(struct f2fs_sb_info *sbi, struct discard_cmd *dc, block_t blkaddr) argument
1453 struct discard_cmd *dc; local
1572 struct discard_cmd *dc; local
1626 struct discard_cmd *dc, *tmp; local
1698 struct discard_cmd *dc, *tmp; local
1721 __wait_one_discard_bio(struct f2fs_sb_info *sbi, struct discard_cmd *dc) argument
1748 struct discard_cmd *dc = NULL, *iter, *tmp; local
1804 struct discard_cmd *dc; local
3223 struct discard_cmd *dc; local
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/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c201 if (!clk_mgr->base.ctx->dc->debug.disable_dtb_ref_clk_switch) {
234 if (clk_mgr_base->ctx->dc->debug.min_disp_clk_khz) {
237 < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz))
239 = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_disp_clk_khz);
245 if (clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz) {
248 < khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz))
250 = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz);
272 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
318 for (i = 0; i < clk_mgr->base.ctx->dc->res_pool->pipe_count; i++) {
355 struct dc *d local
625 struct dc *dc = clk_mgr_base->ctx->dc; local
[all...]
/linux-master/drivers/gpu/drm/loongson/
H A Dlsdc_gfxpll.c44 unsigned sel_out_dc : 1; /* 40 dc output clk enable */
81 unsigned int *dc,
107 if (dc)
108 *dc = dc_mhz;
122 unsigned int dc, gmc, gpu; local
134 this->funcs->get_rates(this, &dc, &gmc, &gpu);
136 drm_printf(p, "dc: %uMHz, gmc: %uMHz, gpu: %uMHz\n", dc, gmc, gpu);
80 loongson_gfxpll_get_rates(struct loongson_gfxpll * const this, unsigned int *dc, unsigned int *gmc, unsigned int *gpu) argument
H A Dlsdc_gfxpll.h29 unsigned int *dc, unsigned int *gmc, unsigned int *gpu);
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn302/
H A Ddcn302_fpu.c195 void dcn302_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) argument
211 if (dc->ctx->dc_bios->vram_info.num_chans)
212 dcn3_02_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
214 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
215 dcn3_02_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
217 dcn3_02_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
218 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
333 dml_init_instance(&dc
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/dml/dcn303/
H A Ddcn303_fpu.c191 void dcn303_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params) argument
207 if (dc->ctx->dc_bios->vram_info.num_chans)
208 dcn3_03_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
210 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
211 dcn3_03_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
213 dcn3_03_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
214 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
352 dml_init_instance(&dc
[all...]
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_init.c132 void dcn201_hw_sequencer_construct(struct dc *dc) argument
134 dc->hwss = dcn201_funcs;
135 dc->hwseq->funcs = dcn201_private_funcs;
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_init.c124 void dcn10_hw_sequencer_construct(struct dc *dc) argument
126 dc->hwss = dcn10_funcs;
127 dc->hwseq->funcs = dcn10_private_funcs;
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_init.c141 void dcn20_hw_sequencer_construct(struct dc *dc) argument
143 dc->hwss = dcn20_funcs;
144 dc->hwseq->funcs = dcn20_private_funcs;

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